METHOD AND DEVICE FOR MANAGING INFORMATION EXCHANGE BETWEEN NFC CONTROLLER AND AUXILIARY ELEMENTS

Abstract

A device, including a main element and a set of at least two auxiliary elements, the main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to the master SWP interface of the NFC element through a controllably switchable SWP link and management circuit configured to control the SWP link switching for selectively activating at once only one slave SWP interface on the SWP link.

Claims

1. A near field communication (NFC) controller for a circuit having a first Universal Integrated Circuit Card (UICC) and a second UICC, the NFC controller comprising a control circuit configured to: receive a low-power mode indicator from a main processor of the circuit, the low-power mode indicator designating an operation of the first UICC in a low-power operating mode, the second UICC being powered OFF when the first UICC is in the low-power operating mode; transmit the low-power mode indicator to the first UICC, the transmitting causing an auxiliary processor of the first UICC to retrieve a configuration indicator from an auxiliary memory of the first UICC, the first UICC using the configuration indicator to switch a single wire protocol (SWP) link for operating the first UICC in the low-power operating mode; and communicate, in the low-power operating mode, with the first UICC, wherein the first UICC is powered by the NFC controller in the low-power operating mode.

2. The NFC controller of claim 1, wherein the control circuit is further configured to exchange communication between the circuit and an external contactless device using an antenna.

3. The NFC controller of claim 2, wherein power provided by the antenna is used to power the NFC controller in the low-power operating mode.

4. The NFC controller of claim 1, wherein the control circuit is further configured to store the configuration indicator in the auxiliary memory in a full-power operating mode of the circuit.

5. The NFC controller of claim 1, wherein the NFC controller provides a voltage to the first UICC in the low-power operating mode.

6. The NFC controller of claim 1, wherein the first UICC and the second UICC conform to a European Telecommunications Standards Institute (ETSI) standard.

7. The NFC controller of claim 1, wherein the control circuit is further configured to: designate an operation of the second UICC in the low-power operating mode; and exchange NFC communications with the second UICC.

8. A universal integrated circuit card (UICC) for a device, the UICC comprising a processor and an auxiliary memory, the processor configured to: receive a low-power mode indicator from a near field communication (NFC) controller of the device, the low-power mode indicator designating an operation of the device in a low-power operating mode; retrieve a configuration indicator from the auxiliary memory in response to receiving the low-power mode indicator, the UICC using the configuration indicator to switch a single wire protocol (SWP) link for operating the UICC in the low-power operating mode; and communicate, in the low-power operating mode, with the NFC controller, wherein the UICC is powered by the NFC controller in the low-power operating mode.

9. The UICC of claim 8, wherein the processor is further configured to store the configuration indicator in the auxiliary memory in a full-power operating mode of the device.

10. The UICC of claim 8, wherein the UICC receives a voltage from the NFC controller in the low-power operating mode.

11. The UICC of claim 8, wherein the processor is further configured to communicate with the NFC controller using a communication link having a switch that selectively links the UICC with the NFC controller.

12. The UICC of claim 8, wherein the UICC conforms to a European Telecommunications Standards Institute (ETSI) standard.

13. The UICC of claim 8, wherein the UICC is a first UICC, the device further comprising a second UICC, and wherein the second UICC is activated in response to de-activating the first UICC.

14. The UICC of claim 8, wherein the processor is further configured to receive a signal from a main processor of the device, the signal de-activating the UICC in the low-power operating mode.

15. A near field communication (NFC) controller comprising a control circuit, the control circuit configured to: exchange, using a single wire protocol (SWP) port, information with a first Universal Integrated Circuit Card (UICC) or a second UICC external to the NFC controller via an SWP communications link; modulate communication of the NFC controller with one of the first UICC or the second UICC via the SWP communications link; provide, by a control port coupled to the control circuit, a control signal indicative of whether the NFC controller is to communicate with the first UICC or the second UICC via the SWP communications link; electrically couple, using a switch arranged along an electrical path between the SWP port and each of the first UICC and the second UICC, the SWP port to one of the first UICC or the second UICC based on the control signal; and concurrently electrically decouple, using the switch, the SWP port from the other of the first UICC or the second UICC.

16. The NFC controller of claim 15, wherein the control circuit is further configured to generate the control signal based on a determination of whether the NFC controller is to communicate with the first UICC or the second UICC via the SWP communications link.

17. The NFC controller of claim 15, wherein the control circuit is further configured to: enable the SWP communications link between the NFC controller and the first UICC based on the control signal; and disable the SWP communications link between the NFC controller and the second UICC based on the control signal.

18. The NFC controller of claim 15, wherein the SWP communications link between the NFC controller and the first UICC comprises an SWP communications channel between the NFC controller and a subscriber identification module (SIM) card.

19. The NFC controller of claim 15, wherein at least one of the first UICC or the UICC comprises a smart card conforming to a European Telecommunications Standards Institute (ETSI) standard.

20. The NFC controller of claim 15, wherein the SWP port, the control circuit, the control port, and the switch are integrated within a single element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Other advantages and features of the invention will appear on examining the detailed description of embodiments, these being in no way limiting, and of the appended drawings in which:

[0053] FIG. 1 illustrates schematically an embodiment of a device according to the invention;

[0054] FIGS. 2 and 3 illustrate connections between a main element and auxiliary elements through a SWP link;

[0055] FIGS. 4, 5a, and 5b illustrate diagrammatically examples of flow charts of several embodiments of a method according to the invention;

[0056] FIGS. 6-9 illustrate diagrammatically examples of frames used in embodiments of the present invention;

[0057] FIGS. 10 and 11 illustrate diagrammatically other examples of flow charts related to initial and subsequent activations;

[0058] FIG. 12 illustrates diagrammatically an embodiment of a multiplexer-demultiplexer switch in the present invention;

[0059] FIGS. 13 and 14 illustrate diagrammatical embodiments of a wireless apparatus according to the invention; and

[0060] FIGS. 15 to 18 illustrate diagrammatically other embodiments of a method and a wireless apparatus according to the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0061] Embodiments of the invention will now be described in the technical field of contactless elements or components connected to secure elements, in particular, embedded in a mobile phone, although the invention is not limited to these particular embodiments.

[0062] A contactless element is an element or a component able to exchange information through an antenna with a contactless device according to a contactless communication protocol.

[0063] An NFC element or component, which is a contactless element, is an element or component compliant with the NFC technology.

[0064] In FIG. 1, an example of a device DIS according to the invention is illustrated, which comprises a contactless front end element ME, for example, an NFC controller, having a SWP interface MINT.

[0065] The device also comprises two auxiliary elements or secure elements. Each secure element SEI (SE2) comprises a SWP interface SLINT 1 (SLINT 2). Each SWP interface SLINTi is connected to the same SWP interface MINT of the NFC controller ME through a controllably switchable SWP link LK.

[0066] A secure element is, for example, an element adapted to contain secure or protected information, for example, banking information and information related to telephone subscriptions, among others.

[0067] Each SWP interface SLINTi comprises an auxiliary management circuit AMGi, while the SWP interface MINT of the NFC controller ME comprises a processing circuit PRM.

[0068] The NFC controller ME is coupled to an antenna ANTI for exchanging information with a contactless reader by using a contactless communication protocol, for example, the one disclosed in ISO/IEC 14443.

[0069] The Single Wire Protocol (SWP) is a bit-oriented, point-to-point communication protocol between a secure element and a contactless front end, and is specified in the standard ETSI TS 102 613, for example, the version V7.7.0 (2009-10) thereof. The man skilled in the art could refer, if necessary, to this document, the content incorporated by reference in the present patent application.

[0070] More precisely, as illustrated in FIG. 2, the NFC controller ME is the master, whereas a secure element SE is a slave. The master and a slave are mutually connected through an SWP link LK.

[0071] An SWP link is a link or line adapted to support the Single Wire Protocol (SWP).

[0072] As disclosed in ETSI TS 102 613, the principle of the single wire protocol (SWP) is based on transmitting digital information in full-duplex mode. The signal S1 from ME to SE is transmitted by a digital modulation (L or H) in the voltage domain, whereas the signal S2 from SE to ME is transmitted by a digital modulation (L or H) in the current domain.

[0073] When the master sends S1 as state H then the slave may either draw a current (state H) or not (state L) and thus transmits S2. With pulse width modulation bit coding of S1, it is possible to transmit a transmission clock, as well as data in full-duplex mode. More details can be found in ETSI TS 102 613.

[0074] FIG. 3 represents an embodiment of the physical link between the contactless element ME and a secure element SE. More precisely, as illustrated in this figure and explained in ETSI TS 102 613, the contact C6 of the secure element is connected to the port SWIO of the contactless element ME for transmission of signals S1 and S2.

[0075] The SWP protocol specified in ETSI TS 102 613 permits only the communication between the master SWP interface of the contactless element and a single slave SWP interface of a single secure element.

[0076] According to an aspect of the invention which will now be described in more detail, it will be possible to connect two or more two auxiliary elements or secure elements SEi provided with an SWP-UICC technology to a single master SWP interface of a contactless element, for example, an NFC controller.

[0077] More precisely, if we refer again to FIG. 1, this will be possible in particular by connecting a controllable multiplexer/demultiplexer switch SW between the master SWP interface MINT and the slave SWP interfaces SLINT1, SLINT2, and by controlling the switch SW by control circuit C TLM for switching the SWP link to the selected slave SWP interface.

[0078] Here, the processing circuit PRM, the control circuit CTLM, and the auxiliary management circuit AMGi form management circuit are configured to control the SWP link switching for selectively activating at once only one selected slave SWP interface on the SWP link.

[0079] The management circuit and the control circuit may be realized by the software module and at least partly by the logic circuit.

[0080] In the present embodiment, where only two auxiliary elements are used, the multiplexer/demultiplexer switch SW has a first terminal T1 coupled to the master SWP interface MINT through a first part LK1 of the SWP link LK and two second terminals T20 and T2 respectively coupled to the two slave SWP interfaces SLINT1, SLINT2 through two second parts LK20, LK21 of the SWP link.

[0081] Of course, although the parts LK1, LK20, and LK21 have been represented here by wires between the terminals T1, T20, T21, and the corresponding terminals of the SWP interfaces, these parts may be reduced to the minimum if for example, the terminals T1, T20, T21 respectively meet the corresponding terminals of the SWP interfaces.

[0082] The switch SW further comprises a control terminal T3 connected to the control circuit CTLM for receiving a control signal SWCTRL for switching the first terminal T1 to either the second terminal T20 or the second terminal T21, depending on the logic value of the control signal.

[0083] For example, as illustrated in FIG. 1, if the control signal SWCTRL has the logic value 0, the first terminal T1 is connected to the second terminal T20 while the first terminal T1 is connected to the second terminal T21 if the control signal SWCTRL has the logic value 1.

[0084] As defined in ETSI TS 102 613, an SWP link may have an activated state, a suspended state and a deactivated state.

[0085] More precisely, in the activated state, the master element and the selected auxiliary element are sending bits.

[0086] In the suspended state, the signal S1 is in state H and S2 is in state L.

[0087] In the deactivated state, the signal S1 is in state L and the signal S2 is in state L.

[0088] As it will be explained in more detail, controlling the switch SW is only performed when the SWP link LK is in its deactivated state.

[0089] Further, when a secure element SE 1, for example, has been selected, the part of the SWP link seen by the other non-selected secure element (SE2, for example), is advantageously in a deactivated state.

[0090] Placing such part of the SWP link in a deactivated state is equivalent to place the C6 contact of the corresponding non-selected secure element in a low state, typically at ground.

[0091] Resistors R20 and R21 respectively connected between the second terminal T20 and a voltage reference, for example, ground, and between second terminal T21 and the voltage reference, are pull-down resistors. And, the pull-down resistor R20 permits to force the part LK20 of the SWP link into a deactivated state when the secure element SE2 has been selected, while pull-down resistor R21 forces the part LK21 of the SWP link into its deactivated state when the secure element SE1 has been selected.

[0092] Further, another pull-down resistor R3 connected between the control input T3 and the voltage reference (ground, for example) permits to force the control input to the logical value 0, thereby forcing the switch in the predetermined configuration in which terminal T1 is connected to terminal T20, in the case the switch SWP is not sufficiently or not at all powered.

[0093] The value of each pull-down resistor is chosen to have, for example, a current having a very small value, for example, 5 ?A or 10 ?A.

[0094] We now refer to FIG. 4, which illustrates a particular embodiment of a method according to the invention.

[0095] After the master element boot, the processing circuit PRM of the master element puts the SWP link in its deactivated state (step 400) to select (step 401) one secure element, for example, secure element SE1. In this respect, the control signal SWCTRL has the logic value o.

[0096] Since the secure element SE1 has been selected, the part LK21 of the SWP link seen by the other non-selected secure element SE2 is forced to be in a deactivated state by the pull-down resistor R21 (the signal S1 is pulled down to state L by the resistor R21).

[0097] Of course, as explained above, forcing the part of the SWP link seen by the non-selected secure element in its deactivated state is equivalent to force the potential of the C6 contact of the secure element to a low state (ground, for example).

[0098] Once the secure element SE1 has been selected, the management circuit (processing circuit and auxiliary management circuit) perform an initial SWP activation (step 402) of the corresponding slave SWP interface, as defined in ETSI TS 102 613.

[0099] Activating a slave SWP interface leads to placing the slave SWP interface in an activated state. For example, activating a slave SWP interface comprises performing an activation phase during which control data are exchanged between the master interface and the slave interface. At the end of the activation phase, the master and the slave have been mutually recognized, and the slave is ready to exchange payload information related to a particular contactless application with the contactless element. The slave interface is thus activated (or in an activated state).

[0100] Once the initial SWP activation sequence is finished, the processing circuit of the main element ME puts the SWP link into its suspended state, and waits for communication from the activated slave interface of the secure element.

[0101] If the conditions are fulfilled to deactivate the secure element, the processing circuit of the main element puts the SWP link in its deactivated state (step 404). Such conditions are, for example, those detailed in point 8.3 of ETSI TS 102 613.

[0102] Now, the main element ME can switch the SWP link between the secure element SE1 and the secure element SE2 (step 406).

[0103] In this respect, the switch control SWCTRL takes the logic value 1.

[0104] An initial SW activation (step 402) is performed for the secure element SE2, while the part LK20 of the SWP link seen by the non-selected secure element SE1 is forced into its deactivated state by the pull-down resistor R20 (step 407).

[0105] For example, an event that can lead to an initial SWP activation of secure element SE2, which is, for example, a UICC, is the reception of a signal from the main processor.

[0106] Once the initial SWP activation sequence is finished for the secure element SE2, the processing circuit of the main element ME puts the SWP link into its suspended state to wait for SWP communication from secure element SE2. If no activity is required on this interface, the processing circuit of the main element puts the SWP link in its deactivated state (step 404).

[0107] If another secure element SE is to be activated, a new selection is performed, followed by the initial activation of this newly selected secure element (step 402).

[0108] If no other secure element is to be activated (step 405), the SWP link remains in its deactivated state.

[0109] At this stage, if SWP communication with a secure element SEi is required (step 501) (upon, for example, reception of an external event coming from the application supported by this secure element), this secure element SEi is selected (step 502).

[0110] Of course, if the switch SWP is already in the configuration for selecting this secure element, no change is performed on the switch.

[0111] Then, a subsequent activation (step 504), as defined in ETSI TS 102 613, is performed for this secure element SEi, while the part of SWP link seen by each non-selected secure element SEj (contact C6 of each non-selected secure element SEj) is in its deactivated state (step 503).

[0112] Once the selected slave interface SLINTi of the secure element SEi has been activated (step 505), a SWP communication between the main element ME and this secure element SEi may be performed (step 506) until the conditions are fulfilled allowing to deactivate the SWP link as for example described within chapter 8.3 of ETST TS 102 613, for example, until the reception of a signal named EVT_HCI_END_OF_OPERATION in ETSI TS 102 622 (step 507).

[0113] Such a signal indicates the end of communication with the secure element SEi.

[0114] After the conditions are fulfilled, the SWP link is put again in its deactivated state (step 508) by the processing circuit PRM of the main element SE.

[0115] If a new SW communication is required with the previously selected secure element SEi, thus, the control signal SWCTRL is not modified (step 510) and a subsequent activation (step 511) is performed for activating the slave interface SLINTi of this secure element SEi (step 512) permitting thus the SWP communication with this secure element (Step 513).

[0116] If an SWP communication is required with a secure element SEj, different from the previously selected secure element SEi, then, this new secure element SEj is selected (step 514) by modifying the value of the control signal SWCTRL.

[0117] A subsequent activation (step 516) is performed for this newly selected secure element SEj, while maintaining the contact C6 of each other non-selected secure element in a low state (step 515).

[0118] Once the slave interface SLINTj of this secure element SEj has been activated (step 517), an SWP communication between the main element ME and the secure element SEj may be performed (step 518).

[0119] An initial activation and subsequent activation of a slave interface are disclosed in ETSI TS 102 613.

[0120] The man skilled in the art may refer to this standard if necessary.

[0121] Some details about these activations are now briefly described with reference to FIGS. 6-11.

[0122] According to ETSI TS 102 613, particular control frames, called ACT frames, are exchanged between the NFC controller ME and a secure element SE during an activation phase.

[0123] Such an ACT frame, referenced CPR, is diagrammatically illustrated in FIG. 6.

[0124] More precisely, the first three bits of byte 1 of the frame CPR declare the SWP frame as an ACT frame. The FR bit indicates an eventually corrupted previously received ACT frame (only used by the NCF controller ME). The INF bit indicates that the last payload byte contains the ACT INFORMATION field and the ACT CTRL bits b1 b2 b3 define the meaning of the ACT frame. After byte 1, 0-3 payload bytes follow, the content thereof depending of the content of ACT_CTRL and FR fields.

[0125] More precisely, when the bits b1 b2 b3 have respectively the binary values 000, the corresponding frame CFR1 is a so-called ACT_READY frame indicating that the secure element has been activated and is ready for exchanging information with the contactless element (FIG. 7).

[0126] When the bits b1, b2, b3 have respectively the binary values 001, the corresponding frame CFR2 is a so-called ACT_SYNC frame sent by a secure element and containing the identification SYNC_ID of this secure element (FIG. 8).

[0127] When the bits b1 b2 b3 have respectively the binary values 010, the corresponding frame CFR3 (FIG. 9) is a so-called ACT POWER MODE frame sent by the contactless element and indicating the power mode (full power or low power).

[0128] FIG. 10 is more particularly directed to an initial activation of a slave interface. An initial activation is performed in particular after the first powering up of the device or after a new powering up following a power interruption.

[0129] First, the SWTO signal (see FIGS. 2 and 3) which is in its low state L is set to its high state H by the NFC controller (state 80). The SWP link is in its suspended state.

[0130] In ETSI TS 102 613 a secure element that detects such state H on its contact C6 has a predetermined duration (700 ?s) for resuming the SWP link.

[0131] The auxiliary management circuit of the slave interface of the secure element SE, which is the selected secure element, sends, after having resumed the SWP link, an ACT_SYNC frame CFR2 (step 83).

[0132] Then, the activation process continues depending on the power mode (step 85).

[0133] More precisely, the NFC controller ME sends an ACT_POWER_MODE frame CFR3 (step 86) in the case of a full power mode.

[0134] Upon receipt of this frame CFR3, the auxiliary management circuit of the selected secure element SE sends an ACT READY frame CFR1 (step 87).

[0135] The SWP interface of the secure element SEn is thus considered activated.

[0136] If the power mode is a low power mode, the interface of the selected secure element SE is considered to be activated after step 83.

[0137] FIG. 11 illustrates diagrammatically a subsequent activation of secure element SE.

[0138] In step 91, the auxiliary management circuit of the secure element SE sends on the link LK the ACT_SYNC frame.

[0139] The slave SWP interface of the secure element SE is thus considered to be subsequently activated.

[0140] FIG. 12 illustrates diagrammatically an embodiment of an analog multiplexer/demultiplexer switch SW allowing connection with two secure elements.

[0141] In this embodiment, the switch SW is a passive switch. It comprises, for example, two NMOS transistors TRA and TRB. The input control T3 of the switch SW is connected to the gate of transistor TRA and the gate of transistor TRB through an inverter INV.

[0142] The terminal T20 of the switch SW is connected to one electrode (the drain, for example) of the transistor TRA, while the terminal T21 of the switch SW is connected to the electrode (the drain, for example) of transistor TRB.

[0143] The other electrode (the source, for example) of each transistor TRA and TRB are both connected to the terminal Tl of the switch SW.

[0144] It is also possible to use an active multiplexer/demultiplexer switch, for example, the one available at the company STMicroelectronics under the reference STG5123.

[0145] Such an active multiplexer/demultiplexer switch which is a high-speed CMOS low voltage single analog SPDT (Single-Pole Double Throw) switch or 2:1 multiplexer/demultiplexer switch, has a lower resistivity and a lower input capacity.

[0146] As illustrated in FIG. 13 and FIG. 14, the device DIS may be incorporated in a wireless apparatus WP such as a mobile phone. More precisely, the mobile phone comprises here conventionally a main processor (application or baseband processor) exchanging information with the secure element SE1, for example, a UICC, of the device through signal CLK, RST, I/O compliant with ETSI TS 102 221 permitting thus the telephone functionality through the antenna ANT2.

[0147] The NFC controller ME is connected to the main processor through another bus, for example, an I.sup.2C bus.

[0148] The secure element SE2 is, for example, used for banking operations.

[0149] The secure element SE2 is embedded in an integrated circuit containing the NFC controller ME and is, for example, packed with the NFC controller in a single package SPCK.

[0150] While the secure element SE2 is thus permanently fixed within the apparatus WP, the secure element SE1 (UTCC) is removably lodged within the apparatus WP and connected to the NFC controller.

[0151] The NFC controller is powered by the voltage VPS_main from a power management unit PMU connected to a battery. The NFC controller is also directly connected to the battery.

[0152] At last, an antenna ANTI permitting an NFC communication with a contactless device is coupled to the NFC controller.

[0153] Information related to two different applications may be thus exchanged between the secure elements SE1 or SE2 through the NFC controller and the antenna ANTI.

[0154] In both embodiments disclosed in FIGS. 13 and 14, the NFC controller ME may, in a full power operation mode, either select the secure element SE1 or the secure element SE2 through the switch SW for performing an SWP communication with the selected secure element.

[0155] However, in the embodiment disclosed in FIG. 13, in a low power mode (for example, when the battery is off), the secure element SE1 is powered by the NFC controller ME and SWP communication is only possible with this secure element SE1.

[0156] The secure element SE1 is connected to terminal T20 of the switch SW and, in a low power mode, the switch SW is forced by the pull-down resistor R3 to be in a configuration where terminal Tl is connected to terminal T20.

[0157] As indicated above, the power Vcc of the secure element SE1 is delivered by the NFC controller.

[0158] To be compliant with ETSI TS 102 221, which requires the same power value between the main processor and the ETSI TS 102 221 interface of the secure element SE1, an additional signal Vref indicating the voltage value of the main processor is delivered to the NFC controller.

[0159] In the embodiment disclosed in FIG. 14, the secure element SE2 is powered by the NFC controller ME in low power mode and SWP communication is only possible between the NFC controller and this secure element SE2 in low power mode.

[0160] In this respect, as in a low power mode, switch SW is forced by pull-down resistor R3 into a configuration in which terminal Tl is connected to terminal T20, the secure element SE2 is connected to terminal 20 while secure element SE1 is connected to terminal T21 of the switch SW.

[0161] FIGS. 15 to 18 illustrate diagrammatically another embodiment of the present invention permitting, for example, the user of the wireless apparatus to choose which auxiliary element will be able to cooperate with the main element (NFC controller) in the low power mode, i.e. when the battery is off.

[0162] As for the embodiments illustrated in FIGS. 13 and 14, the device has a first state in which all the auxiliary elements can operate in a first operation mode, for example, in a full power mode.

[0163] As it will be explained now more in details the device illustrated in FIG. 15 has a second state in which at least the secure element SE2 is able to operate in a second operation mode, for example in the low power mode.

[0164] Thus, the device comprises auxiliary selection circuit at least partly incorporated in the secure element SE2 and configured, when the device is in its second state, to control the SWP link switching for selecting only one auxiliary element operating in a second operation mode, here the secure element SE2.

[0165] More precisely, the secure element SE2 is powered by Vcc1 provided by the NFC controller ME.

[0166] The contact C1 of the secure element SE1 is connected to the voltage Vcc provided by the main processor in the full power mode, and to the voltage Vcc1 through a PMOS transistor TRP. The gate of this transistor TRP is connected to Vcc1 through a pull-up resistor R4.

[0167] The gate of the transistor TRP is also connected to an input/output port I/O2 of the secure element SE2.

[0168] This port I/O2 is also connected to a first input of a EXNOR gate LGT.

[0169] The second input of the EXNOR gate LGT is connected to the NFC controller for receiving the control signal SWCTRL in the first operation mode, and to the pull-down resistor R3 to be forced to the logical value 0 in the second operation mode.

[0170] The output of the EXNOR gate LGT is connected to the control input of the switch SW.

[0171] Both EXNOR gate LGT and switch SW are powered by Vcc1, which is still available in the second operation mode.

[0172] The output terminal T20 of the switch is connected to the contact C6 of the secure element SE1, and the input terminal T1 of the switch is switched to the terminal T20 when the signal present at the control input of the switch has the logical value 1.

[0173] The output terminal T21 of the switch is connected to the SWP interface of the secure element SE2, and the input terminal T1 of the switch is switched to the terminal T21 when the signal present at the control input of the switch has the logical value 0.

[0174] The secure element also comprises an auxiliary processing circuit PRA connected to the auxiliary memory circuit MMA, port I/O2, and another input/output port I/O1. The auxiliary processing circuit may be realized by a logic circuit and/or by software.

[0175] The main processor is also configured to receive from a user interface an indication designating the auxiliary element, which is chosen to be able to cooperate with the main element (NFC controller) in the low power mode. This indication is processed by the main processor and sent to the NFC controller through the I.sup.2C bus, and then to the secure element SE2 during an SWP transaction in full power mode. The auxiliary processing circuit PRA of the secure element is thus configured to store in the auxiliary memory circuit MMA a corresponding configuration indication CFI.

[0176] The main processor also comprises a detection circuit configured to detect the passage from the first state of the device (full power operation mode) to the second state (low power operation mode) and to deliver a corresponding detection signal SDT to port I/O1. For example, this signal SDT represents the state ON or OFF of the main processor. For example, when the processor is ON, it sets the signal SDT to the logical value 1, whereas the signal SDT is forced to the logical value 0 by a pull-down resistor R S when the processor is OFF.

[0177] The circuits PRA, MMA, DTM, TRP, LGT, R4 form the auxiliary selection circuit.

[0178] The operation of the device in the first state (full power mode) is now described with reference to FIG. 16.

[0179] In this state, all the elements are fully powered by the battery.

[0180] The auxiliary control signal CTRLA, provided at the first input of the EXNOR gate LGT, has the logical value 1 due to the pull-up resistor R4.

[0181] The transistor TRP is off and the secure element SE1 is powered by the Vcc voltage delivered by the main processor.

[0182] In this full power operation mode, the NFC controller ME may either select the secure element SE1 or the secure element SE2 through the switch SW for performing an SWP communication with the selected secure element.

[0183] Because the signal CTRLA has the logical value 1 the logical value of the control signal SWCTRL delivered by the NFC controller will be the logical value of the signal fed at the control input of the switch SW.

[0184] Further, as explained above, during this full power operation mode, the configuration indication CFI may be delivered to secure element SE2 and stored by the auxiliary processing circuit PRA in the auxiliary memory circuit MMA.

[0185] Reference is now made to FIG. 17, to illustrate the case where secure element SE2 is designated by the configuration indication CFI for cooperating with the NFC controller ME through the SWP link during the low power mode.

[0186] In the low power mode, the secure element SE2 is powered by the voltage Vcc1 provided by the NFC controller. As in the embodiments illustrated in FIGS. 13 and 14, the NFC controller is powered by the electromagnetic field received by the antenna ANT1 during an NFC communication with a contactless device.

[0187] Upon receipt of the detection signal SDT having the logical value 0, the auxiliary processing circuit PRA read the configuration indication CFI stored in the auxiliary memory circuit and delivers the control signal CTRLA having here the logical value 1.

[0188] Further, the control signal SWCTRL is forced to the logical value 0 by the pull-down resistor R3.

[0189] Consequently, the EXNOR gate LGT powered by Vcc1, delivers a logical value 0 to the control input of the switch SW, also powered by Vcc1, allowing the selection of the secure element SE2.

[0190] It should be noted here that, in this non-limiting example, the transistor TRP is off, and thus the secure element SE1 is not powered.

[0191] Reference is now made to FIG. 18, to illustrate the case where secure element SE1 is designated by the configuration indication CFI for cooperating with the NFC controller ME through the SWP link during the low operation mode.

[0192] In the low power mode, the secure element SE2 is powered by the voltage Vcc1 provided by the NFC controller.

[0193] Upon receipt of the detection signal SDT having the logical value 0, the auxiliary processing circuit PRA reads the configuration indication CFI stored in the auxiliary memory circuit and delivers the control signal CTRLA having here the logical value 0.

[0194] Consequently, the transistor TRP is ON, and the secure element SE1 is powered by the voltage Vcc1.

[0195] Since the control signal SWCTRL is forced to the logical value 0 by the pull-down resistor R3, the EXNOR gate LGT powered by Vcc1, delivers a logical value 1 to the control input of the switch SW also powered by Vcc1, allowing the selection of the secure element SE 1.

[0196] It should be noted here that the secure element SE1 is powered before being selected by the switch SW due to the delay introduced by the EXNOR gate LGT.

[0197] The circuit PRA, MMA, TRP, R4 form also auxiliary power control circuit configured to control the powering of secure element SE1 and SE2 from the configuration indication.

[0198] Of course, as both secure elements SE1, SE2 are powered in the low power operation mode, the part LK21 of the SWP link seen by the non-selected secure element SE2 is forced in its deactivated state by the pull-down resistor R21.

[0199] According to an aspect of the invention, it is thus possible to exchange information between a main element and two auxiliary elements through a controllable multiplexer/demultiplexer switch without modifying the operating system of the secure element. Further, only a small modification of the operating system of the NFC controller is needed for controlling the analog multiplexer/demultiplexer switch SW.

[0200] Although different embodiments of the invention have been disclosed with two secure elements, other embodiments including more than two secure elements connected to the master SWP interface through a multiplexer/demultiplexer switch SW are also possible.

[0201] Further, although the analog switch SW has been located outside the main element and the slave elements, it would be possible to integrate the switch (and eventually the EXNOR gate) within the single package SPCK or directly within the main element. In such a case, the outputs of the main element would be, for example, the terminals T20 and T21 of the switch, and terminal Tl of the switch would be connected to the processing circuit of the master interface within the main element.