Abstract
The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
Claims
1. A radiation-damage-compensation-circuit fabricated with a SOI-MOSFET, comprising: a MOSFET-channel to detect a voltage threshold shift due to a radiation-induced positive charge in the BOX; a path generating an external voltage under a control of the MOSFET-channel, applying a negative voltage corresponding to the voltage threshold shift to a current-source and applying a negative charge of the current-source to a buried p-well below the BOX.
2. A SOI-MOSFET, having the radiation-damage-compensation-circuit according to claim 1, connecting the MOSFET-channel, an external voltage-source, a silicon-diffusion-layer, the buried p-well and the BOX.
3. A SOI-MOSFET, having the radiation-damage-compensation-circuit according to claim 1, connecting the MOSFET-channel, a transistor, an external voltage-source, a via, the buried p-well and the BOX.
4. A SOI-MOSFET, having the radiation-damage-compensation-circuit according to claim 1, connecting a transistor, an external voltage-source, a via, the buried p-well and the BOX.
5. The SOI-MOSFET according to claim 2, having a buried n-well replaced with the buried p-well.
6. The SOI-MOSFET according to claim 2, having a partially or completely depletion.
7. The radiation-damage-compensation-circuit according to claim 1, for use to cancel a radiation-induced positive charge of a semiconductor-device requiring radiation resistance, said the radiation-damage-compensation-circuit being able to cancel the radiation-induced-positive-charge by applying an external voltage on the beneath of a transistor of the semiconductor-device.
Description
BRIEF DESCRIPTION OF DRAWINGS
(1) FIG. 1 shows a structure of the conventional MOSFET.
(2) FIG. 2 shows the conventional SOI-MOSFET.
(3) FIG. 3 shows the characteristics of the conventional SOI-MOSFET before and after X-ray irradiation.
(4) FIG. 4 shows a radiation-damage-compensation-circuit.
(5) FIG. 5 shows a structure of the SOI-MOSFET (A).
(6) FIG. 6 shows the characteristics of the SOI-MOSFET (A) before and after X-ray irradiation.
(7) FIG. 7 shows a structure of the SOI-MOSFET (B).
(8) FIG. 8 shows a structure of the SOI-MOSFET (C).
(9) FIG. 9 shows a structure of the SOI-MOSFET (D).
(10) FIG. 10 shows a working mechanism of the MOSFET (D).
(11) FIG. 11 shows a structure of the SOI-MOSFET (E).
(12) FIG. 12 shows a structure of the SOI-MOSFET (F).
(13) FIG. 13 shows the characteristics of the SOI-MOSFET (F) before and after X-ray irradiation.
(14) FIG. 14 shows the characteristics of the SOI-MOSFET with complete depletion before and after X-ray radiation.
(15) FIG. 15 shows the characteristics of the SOI-MOSFET with complete depletion before and after reapplication of voltage.
(16) FIG. 16 shows an application of the radiation-damage-compensation-circuit on a semiconductor device.
DESCRIPTION OF EMBODIMENTS
(17) Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with accompanying drawings. Hereinafter, the present invention will be specially explained as an execution embodiment using the following drawings. It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.
(18) Reference 1
(19) FIG. 1 shows the conventional MOSFET. The conventional MOSFET comprises a silicon-substrate (1), a silicon-membrane (2) and a gate-electrode (3) on the silicon-substrate (1), as shown in FIG. 1. The silicone-membrane (2) comprises a source, a channel and a drain. The conventional MOSFET has no BOX, therefore, has no system to cancel radiation-induced positive charges.
(20) Reference 2
(21) FIG. 2 shows the conventional SOI-MOSFET. The conventional SOI-MOSFET comprises a silicon-substrate (1), BOX (4) above the silicon-substrate (1) and the silicon-membrane (2) and gate-electrode (3) above the silicon-membrane (2), as shown in FIG. 2. The conventional SOI-MOSFET has no system to cancel radiation-induced positive charge, therefore, is not available for an X-ray imaging sensor under X-ray irradiation
(22) Control 1
(23) The conventional SOI-MOSFET is irradiated with X-ray of 250 Gy. Radiation-damage of the SOI-MOSFET characteristics after the X-ray-irradiation can be evaluated with a behavior of gate-voltage vs. drain-current before and after the X-ray irradiation. The result is shown in FIG. 3. Generally, a threshold of the gate-voltage Vt is shifted to a lower voltage side after the irradiation. Before the irradiation, a threshold of a gate-voltage Vt is about 0.5 V (see curve-a). After the irradiation, the Vt is shifted to about 0.5 V (see curve-b).
Example 1
(24) FIG. 4 shows a radiation-damage-compensation-circuit that is fabricated with a MOSFET. The radiation-damage-compensation-circuit comprises a MOSFET-channel (10) to detect a voltage threshold shift due to a radiation-induced positive charge in the BOX (4), a path generating an external voltage under a control of the MOSFET-channel (10), a path applying a negative voltage corresponding to the voltage threshold shift to a current-source (7), a buried p-well (5) below the BOX (4), a path applying a negative charge of the current-source to the buried p-well (5) and a path diffusing the negative charge to the BOX (4). In this way, the radiation-damage compensation-circuit is able to cancel the radiation-induced positive charge with monitoring an amount of radiation-induced positive charge. The applied source voltage depends on the thickness of the BOX. When the BOX is thick, comparatively higher voltage is required. When the BOX is thin, comparatively lower voltage is required. Even when the BOX is thick, an application of high voltage is allowed because the buried p-well (5) is in the silicon-substrate (1). The current-source (7) may be replaced with electric resistance (7), which is a more convenient circuit.
(25) All of the following SOI-MOSFET according to the present invention has the above radiation-damage compensation-circuit.
(26) FIG. 5 shows a SOI-MOSFET having the radiation-damage compensation-circuit connecting the MOSFET-channel (10), an external voltage-source (12), a silicon-diffusion-layer (7), the buried p-well (5), the BOX (4). The MOSFET-channel (10) comprises a set of the n-well (5), the p-well (5) and the silicon-layer (6) that is fabricated with the SOI-MOSFET and connected with a wire (8) as detecting the voltage threshold shift due to the radiation-induced positive charge in the BOX (4). The wire (8) leads to the ground. Here, an assembly of the silicon-substrate (1), buried p-well (5), silicon-layer (6), ground (8) and connecting wire (9) corresponds to the SOI-MOSFET channel (10) in FIG. 4 and the silicon-diffusion-layer (7) corresponds to the current-source (7) in FIG. 4. A polysilicon may be used for the silicon diffusion-layer (7). In FIG. 5, the silicon-substrate (1) is, for example, a n-type one. The buried p-well (5) is formed by doping a dopant such as boron of the III-family which has an opposite polarity to the n-type.
(27) FIG. 6 shows the characteristics of the SOI-MOSFET (A) before and after the irradiation. A threshold Vt before the irradiation is about 0 V. After the irradiation, the V t is shifted to a negative side. This shift is corresponding to the contribution of the radiation-induced positive charge. The radiation-induced positive charge is canceled by applying negative voltage corresponding to the threshold sift to the buried p-well. Experi-mentally, when a BOX is 200 nm thick and the irradiation is 100 kGy, the Vt is in the range 1015 V. Therefore, application of 15 V of the voltage source (12) to the buried p-well (5) performs complete recovery of the SOI-MOSFET characteristics.
Example 2
(28) FIG. 7 shows the SOI-MOSFET (B). The SOI-MOSFET (B) has an n-type as the silicon-substrate (1) and a well-in-well, the buried n- and p-wells (5) in the buried n-well (5) which is buried in the buried p-well (5). Therefore, it is not required to anchor the silicon-substrate (1) to the ground.
Example 3
(29) FIG. 8 shows the SOI-MOSFET (C). The SOI-MOSFET (C) is a p-type in which the silicon-substrate (1) is a p-type, the buried n-well (5) is in the p-typed silicon-substrate (5), the buried p-well (5) as a source and the buried n-well (5) as a drain are together in the buried n-well (5).
Example 4
(30) In recently years, a double SOI-MOSFET that has a structure in which an additional silicon-diffusion-layer is formed in the BOX has been presented (the Patent Literature 2). The double SOI-MOSFET is able to use the additional silicon-diffusion-layer as an electrode for shielding the top silicon-diffusion-layer and the under silicon-substrate, therefore, is able to suppress the crosstalk between the top silicon-diffusion-layer and the under silicon-substrate. However, the double SOI-MOSFET does not have good radiation-resistance as with the conventional SOI-MOSFET. Because, the radiation-induced positive charge is generated in the BOX including the middle silicon-diffusion-layer. To solve the problem, the SOI-MOSFET (D) as shown in FIG. 9 will be presented. The SOI-MOSFET (D) has a structure in which the middle silicon diffusion-layer (5) is formed inside the BOX, the middle silicon diffusion-layer is a [p+pp+] type, the buried n-well (5) is formed under the BOX, and the silicon-substrate (1) is a p-type. The top silicon diffusion-layer (6) and the middle buried n-well (5) in the BOX are together available as a gate-electrode. When using an n-typed silicon-substrate, the middle silicon diffusion layer (5) has to be a [n+nn+] type. The top silicon diffusion layer (6) and the middle silicon diffusion layer (5) are connected together with wires (9) through electric contact, working as a single gate. Therefore, the SOI-MOSFET (D) is able to detect the radiation-induced positive charge.
(31) FIG. 10 shows a working mechanism of the SOI-MOSFET (D).
(32) 10a: when the gate and the drain are diode-contacted with wires and a drain-voltage and a gate-voltage are together positive, upper and under parts of the channel are lying in the depletion state due to the field-effect. There is no current between the source and the drain, an off-state.
(33) 10b: when the gate-voltage and the drain-voltage are together minus voltage, the depletion state of the channel turns back due to the field-effect of the gate, followed by appearance of a semiconducting region with non-depletion state. A current passes from the drain to the source, an on-state.
(34) 10c: In the on-state, the channel merely works as a semiconducting resistance. Comparatively high voltage can be applied to even a thin silicon-diffusion-layer.
(35) The SOI-MOSFET (D) before and after the irradiation shows a behavior of gate-voltage vs. drain-current similar to that in FIG. 6. After the irradiation, the V.sub.t is shifted to a minus voltage side. By applying voltage corresponding to a shift of the V.sub.t to the middle silicon-diffusion layer in the BOX, the characteristics of the SOI-MOSFET (D) after the irradiation can be recovered.
Example 5
(36) FIG. 11 shows a SOI-MOSFET (E) having the radiation-damage compensation-circuit connecting the MOSFET-channel (10), a transistor (1b), an external voltage-source, a via (13), the buried p-well (5), the BOX (4). The via (13), that is placed in the BOX (4) as penetrating the BOX (4), is a device connecting the gate and the p-well (5). After X-ray irradiation, a voltage of the external voltage-source (12) controlled by the MOSFET-channel (10) is applied to the gate, applied to the buried p-well (5) through the via (13), negative electron of the buried p-well diffuses in the BOX (4) and the negative electron cancels the radiation-induced positive charge. The buried p-well (5) of the SOI-MOSFET (E) may be replaced with a buried n-well.
Example 6
(37) The SOI-MOSFET with partial depression may be used for. A thickness of the SOI-membrane (2) is usually 100 nm or more.
Example 7
(38) The SOI-MOSFET with complete depression may be used for. A thickness of the SOI-membrane (2) is usually 100 nm or less.
Example 8
(39) FIG. 12 shows a SOI-MOSFET (F) having the radiation-damage compensation-circuit connecting a transistor, an external voltage-source, a via, the buried p-well, the BOX. After the X-ray irradiation, a voltage of the external voltage-source (12) controlled by the transistor (1b) is applied to the buried p-well (5) through the via (13), negative electron of the buried p-well diffuses in the BOX (4) and the negative electron cancels the radiation-induced positive charge. Here, an external detector connected with a wire (9) is capable of detecting the voltage threshold sift due to the radiation-induced positive charge in the BOX in a similar way as the MOSFET-channel. The via (13) may be replaced with a wire leading to the buried p-well (5).
Example 9
(40) FIG. 13 shows the characteristics of the SOI-MOSFET (F) before and after the X-ray-irradiation of 250 Gy. A voltage of 140 V (7 MV/cm) is applied for 3 seconds. It is found that the characteristics are completely recovered to the same (curve-c) as the original state (curve-a) before irradiation by applying the voltage.
Example 10
(41) FIG. 14 shows the characteristics of the SOI-MOSFET with complete depletion before and after the X-ray-irradiation of 250 Gy. A voltage of 140 V is applied for 3 seconds. It is found that the characteristics are completely recovered to the same (curve-c) as the original state (curve-a) before the irradiation by applying the voltage, except for an increase of drain-current. The curve-c is a peculiar behavior of the SOI-MOSFET with complete depletion.
Example 11
(42) FIG. 15 shows the characteristics of the SOI-MOSFET with complete depletion before and after the X-ray-irradiation of 250 Gy. A voltage of 140 V is applied for 3 seconds, successively a voltage of 140 V for 3 seconds. It is found that the characteristics are completely recovered to the same (curve-c) as the original state (curve-a) before irradiation by applying the voltage, except for an increase of drain-current.
Example 12
(43) The SOI-MOSFET having the buried n-well instead of the buried p-well shows the same behavior as those of the SOI-MOSFET.
Example 13
(44) FIG. 16 shows a semiconductor-device that has the radiation-damage compensation-circuit (14). Due to X-ray, the semiconductor-device tends to accumulate the radiation-induced positive charge at the beneath (15) of their transistor (1b). The radiation-damage compensation-circuit (14) detects a voltage threshold shift due to the above charge and cancels the charge by applying an external voltage on the beneath (15).
INDUSTRIAL APPLICABILITY
(45) The present invention relates to the radiation-damage-compensation-circuit, the SOI-MOSFET with high radiation-resistance and the semiconductor devices requiring the radiation-resistance such as an aerospace device and an X-ray imaging sensor. Therefore, the present invention is available for many radiation-resistant applications.
REFERENCE SIGNS LIST
(46) 1a gate 1b transistor 1 silicon-substrate 2 silicon-membrane 3 gate-electrode 4 BOX 5 buried p-well or buried n-well 6 silicon layer 7 current-source (silicon diffusion-layer) 8 wire leading to the ground 9 wire 10 MOSFET (MOSFET-channel) 11 SOI-MOSFET 12 external voltage source 13 via 14 radiation-damage-compensation-circuit 15 beneath of a transistor
