MEMORY CARD PIN LAYOUT FOR AVOIDING CONFLICT IN COMBO CARD CONNECTOR SLOT

Abstract

A SD card is disclosed including an arrangement of interface pins enabling the SD card to be used in a combination connector having a slot configured to receive both SD cards and SIM cards. In examples, the SD card may include multiple rows and/or columns of interface pins configured at positions such that, when the SD card is inserted into a multi-card connector, the positions of the SD card interface pins do not overlap with the positions of SIM card contacts in the connector.

Claims

1. A microSD (OD) card configured for insertion in a combo slot comprising SD and non-SD contacts, the SD card comprising: a first group of interface pins configured to mate with the SD contacts upon insertion of the SD card into the combo slot; and a second group of one or more interface pins whose positions are configured to avoid contact with the non-SD contacts in the combo slot upon insertion of the SD card into the combo slot.

2. A SD card as recited in claim 1, wherein the first and second groups of interface pins are configured to operate according to the PCIe bus standard.

3. A SD card as recited in claim 1, wherein the first and second groups of interface pins are configured to operate according to the SD bus standard.

4. A SD card as recited in claim 1, the first group of interface pins are in positions corresponding to positions of interface pins on SD cards including a single row of interface pins.

5. A SD card as recited in claim 3, wherein the second group of one or more interface pins comprise a plurality of interface pins arranged in two or more rows, the interface pins in the two more rows having a length parallel to a length of the interface pins in the first group of interface pins.

6. A SD card as recited in claim 3, wherein the second group of one or more interface pins comprise a plurality of interface pins arranged in one or more columns, the interface pins in the one more columns having a length orthogonal to a length of the interface pins in the first group of interface pins.

7. A SD card as recited in claim 1, further comprising a third group of one or more interface pins whose positions contact the non-OD contacts upon insertion of the SD card into the combo slot, wherein conflict of the third group of one or more interface pins with the non-OD contacts is mitigated by design.

8. A SD card as recited in claim 1, wherein the second group of one or more interface pins comprise a plurality of interface pins arranged in two or more rows, the interface pins in the two more rows being centrally positioned in the same horizontal position as existing second row of pins in a UHS-II SD card.

9. A microSD (OD) card, comprising: a first group of interface pins configured to mate with SD contacts upon insertion of the SD card into a ST19 Series 3-in-2 card connector of the host device; and a second group of one or more interface pins whose positions have been configured to avoid contact with nano-SIM contacts upon insertion of the SD card into a ST19 Series 3-in-2 card connector of the host device.

10. A SD card as recited in claim 9, wherein the first and second groups of interface pins are configured to operate according to the SD and PCIe bus standard.

11. A SD card as recited in claim 10, wherein the first group of interface pins comprise a row of eight interface pins, and the second group of interface pins comprise between eight and ten interface pins.

12. A SD card as recited in claim 11, wherein the first group of interface pins are positioned a row of interface pins corresponding to the positions of a legacy SD card comprising a single row of interface pins.

13. A SD card as recited in claim 12, wherein the second group of one or more interface pins are positioned in positions other than directly beneath the row of interface pins.

14. A SD card as recited in claim 12, wherein the second group of one or more interface pins comprise a plurality of interface pins arranged in two or more rows, the interface pins in the two more rows having a length parallel to a length of the interface pins in the first group of interface pins.

15. A SD card as recited in claim 12, wherein the second group of one or more interface pins comprise a plurality of interface pins arranged in one or more columns, the interface pins in the one more columns having a length orthogonal to a length of the interface pins in the first group of interface pins.

16. A SD card as recited in claim 9, wherein the second group of one or more interface pins comprise a plurality of interface pins arranged in two or more rows, the interface pins in the two more rows being centrally positioned in the same horizontal position as existing second row of pins in a UHS-II SD card.

17. A SD card as recited in claim 9, further comprising a third group of one or more interface pins whose positions contact the nano-SIM contacts upon insertion of the SD card inserted into the ST19 Series 3-in-2 card connector of the host device, wherein conflict of the third group of one or more interface pins with the non-SD contacts is mitigated by design.

18. A SD card as recited in claim 17, wherein the third group of contacts is positioned in same position as a second row of interface pins in a UHS-II SD card.

Description

DESCRIPTION OF THE DRAWINGS

[0005] FIGS. 1 and 2 are bottom views of conventional SD cards including one row of interface pins and two rows of interface pins, respectively.

[0006] FIG. 3 is a prior art illustration of a conventional connector for receiving both a SD card and a nano-SIM card.

[0007] FIG. 4 is a prior art illustration of a conventional nano-SIM card.

[0008] FIG. 5 is a bottom view of a SD card according to an embodiment of the present technology enabling the SD card to be used in a card slot including both SD and nano-SIM card contacts.

[0009] FIG. 6 is an illustration of a card connector and the SD card of FIG. 5.

[0010] FIGS. 7-12 are views of SD cards including different arrangements of interface pins according to different embodiments of the present technology.

DETAILED DESCRIPTION

[0011] The present technology will now be described with reference to the figures, which in embodiments, relate to a SD card including an arrangement of interface pins enabling a SD card with multiple rows of interface pins to be used in a connector having a combination slot configured to receive both legacy SD cards and memory cards configured according to another standard, such as SIM cards. In embodiments, the SD card of the present technology may include a first row of interface pins configured to mate with legacy SD card contacts in a card slot. The SD card of the present technology may further include one or more additional rows and/or columns of interface pins configured at positions such that, when the SD card is inserted into a combination slot, the positions of the SD card interface pins do not conflict with or overlap with the positions of SIM (or other standard) card contacts in the slot.

[0012] It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.

[0013] The terms top/bottom, upper/lower and vertical/horizontal, and forms thereof, as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms substantially and/or about mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is 0.25% of a defined component dimension.

[0014] Referring now to FIG. 5, there is shown a OD card 100 including a plurality of interface pins 102 including multiple rows of interface pins 102. In one embodiment, the SD card 100 is configured to operate according to the PCI-Express (PCIe) expansion bus standard adapted into a SD card form factor. However, it is understood that the SD card 100 may be configured according to any of a variety of other standard and non-standard bus protocols which include interface pins in addition to a single row of legacy interface pins. As one further example, the SD card 100 may be configured to operate according to the UHS-II standard. In another example, the card 100 may be configured as a Universal Flash Storage (UFS) card, which has a very similar shape to a SD card, including multiple rows of interface pins that may be inserted in a connector, such as in the opening 90 of the combination connector 70 shown in FIG. 3 and may be configured to operate according to the UFS specification.

[0015] The embodiment shown in FIG. 5 includes a first row 104 of legacy interface pins 102, conforming in number and position to interface pins provided for example on a UHS-I SD card having a single row of interface pins. The first row 104 may include interface pins conforming in number and/or position to interface pins of a memory card standard other than UHS-I in further embodiments.

[0016] The embodiment of the SD card 100 in FIG. 5 further includes a second row 106 and a third row 108 of interface pins 102. In FIG. 5 and the embodiments explained below, interface pins 102 in SD card 100 in rows or columns other than row 104 of legacy interface pins may be referred to as non-legacy interface pins 102.

[0017] The illustrated embodiment of FIG. 5 includes four vertically oriented non-legacy interface pins 102 in the second row 106, and four vertically oriented non-legacy interface pins 102 in the third row 108. It is understood that the number and size of the interface pins 102 in rows 106 and 108 may vary in further embodiments, based for example in part on functionality of the respective pins 102. The vertical position (i.e., along the length dimension of the SD card 100) of the pins 102 in the rows 106 and/or 108 may vary from that shown in FIG. 5 in further embodiments.

[0018] In embodiments, the three rows 104, 106 and 108 provide sixteen interface pins 102 supporting power, ground and signal transfer of both, SD and PCIe bus standard. However, there may be more or less pins than that in further embodiments. In one further example explained below with respect to FIGS. 11 and 12, there may be seventeen or eighteen interface pins 102, in multiple rows such as for example three rows, which together are configured to operate according to the SD and PCIe bus standard.

[0019] As noted, the interface pins may be configured to operate according to other bus standards in further embodiments. In one such further embodiment, the SD card 100 may operate according to the UHS-II SD standard, with the pins 102 in the row 104 conforming in size and functionality to the size and functionality of the interface pins in the first row of a conventional UHS-II SD card. The interface pins in the rows 106 and 108 may likewise conform to the size and functionality of the interface pins in the second row of a conventional UHS-II SD card.

[0020] FIG. 6 is a cross-sectional top view of a combination card connector 120 for accepting flash memory cards of different configurations. In one example, the card connector 120 may be the ST19 Series 3-in-2 card connector from JAE described above, mounted within a slot 122 of a host device 124. The card connector 120 is shown with an inserted tray 126 including the SD card 100 of FIG. 5 as explained below. The combination card connector 120 may be used in any of a variety of host devices 124, including for example mobile smart phones, tablets, laptops, desktops, gaming devices, automotive devices, servers and other mobile or stationary systems.

[0021] As noted, the card connector 120 may be a ST19 Series 3-in-2 card connector where the connector 120 is configured to receive either a pair of nano-SIM cards, or a SD card and a nano-SIM card. In particular, the connector 120 includes a combo area 130 having a first group of contacts 134 configured to mate with the legacy interface pins 102 in the first row 104 of a SD card 100. The combo area 130 further includes a second group of contacts 136 configured to mate with the interface pins on a standard nano-SIM card. The contacts 136 are numbers C1 to C7 in FIG. 6. The contacts C1 to C7 may be affixed within slot 122 by a frame (not shown) mounted to the card connector 120.

[0022] In FIG. 6, SD card 100 of FIG. 5 has been flipped over and inserted into the tray 126 of the combination connector 120, and the tray 126 is shown in FIG. 6 inserted into the slot 122 of the combination connector 120. As set forth in the Background section, if the interface pins 102 shown in the second and third rows 106, 108 were instead included in a single, second row as in the UHS-II SD card 60 (prior art FIG. 2), certain pins in the second row would conflict with certain contacts 136 provided for the nano-SIM card. For example, a conflict may exist between SIM card contact C3 and interface pins 14, 15 or 16, and/or between SIM card contact C7 and interface pins 9 and 17. A conflict as used herein refers to an overlap between a SD card interface pin and a nano-SIM card contact resulting in electrical connection between the interface pin and the nano-SIM card contact.

[0023] However, in accordance with aspects of the present technology, by arranging the interface pins 102 into multiple rows, such as rows 106 and 108, conflict between the SD interface pins 102 and the nano-SIM card contacts is avoided. As shown in FIG. 6, the legacy interface pins 102 in row 104 align with their proper respective SD contacts 134. Additionally, none of the interface pins in rows 106 and 108 conflict with any of the SIM contacts 136. That is, there is no overlap between the interface pins in rows 106 and 108 with any of the SIM contacts 136.

[0024] Thus, the SD card 100 of FIG. 5 may operate within the connector 120 using the legacy interface pins 102 in row 104 according to legacy data transfer standards. As explained below, the slot 120 may alternatively be configured with SD contacts that mate not only with the legacy interface pins, but also SD contacts provided to mate with the non-legacy interface pins 102 of rows 106 and 108. In such an embodiment, data may be transferred to/from the SD card 100 at the enhanced data transfer rates of, for example, the PCIe, UHS-II and/or UFS bus standards.

[0025] When operating within the ST19 Series combination 3-in-2 card connector 120 from JAE, it is understood that the non-legacy interface pins 102 of SD card 100 may be arranged in a variety of different configurations that have no conflict with the SIM contacts C1 to C7, some of which are explained below. Additionally, it is understood that the non-legacy interface pins of SD card 100 may be arranged in a wide variety of configurations to avoid contact with the non-OD card contacts in combination connectors configured to a wide variety of other standards. In such other combination connectors, the second standard may be a SIM or other standard.

[0026] FIGS. 7-12 show further examples of SD card 100 including interface pins 102 arranged vertically (along the length dimension of card 100) and/or horizontally (along the width dimension of card 100) which can be used within the combination connector 120 (or some other combination connector) without conflict between the interface pins 102 and the non-OD contacts in the combination connector.

[0027] FIG. 7 shows a row 104 of legacy interface pins 102, and columns 140 and 142 of non-legacy interface pins 102 at bottom left and right corners of SD card 100. Such a configuration of interface pins may operate in a combination connector 120 having no non-SD contacts in the lower corners of the connector, thus avoiding conflict the non-legacy interface pins 122 and any non-SD contacts. Alternatively, the configuration of interface pins shown in FIG. 7 may operate in a combination slot 120 having no non-OD contacts in only one of the lower corners of the slot. In such an alternative embodiment, a conflict may exist in the opposite corner, which conflict may be resolved by design (such as by default disconnection of any conflicting SD interface pins, and connecting such pins only when needed). This feature is explained below.

[0028] The illustrated embodiment of FIG. 7 includes four horizontally oriented non-legacy interface pins 102 in the column 140, and four horizontally oriented non-legacy interface pins 102 in the column 142. It is understood the number and functionality of the interface pins 102 in columns 140 and 142 may vary in further embodiments, based for example in part on functionality of the respective pins 102. The vertical position (i.e., along the length dimension of the SD card 100) of the pins 102 in the column 140 and/or 142 may vary from that shown in FIG. 7 in further embodiments. It is also contemplated that the non-legacy interface pins 102 in the lower corners be oriented vertically, instead of horizontally as shown FIG. 7.

[0029] In embodiments, the row 104 and columns 106 and 108 provide sixteen interface pins 102 supporting power, ground and signal transfer according to the SD and PCIe bus standard. However, there may be more or less pins than that in further embodiments. In one further example, there may be seventeen or eighteen interface pins 102, with eight pins in the row 104 and the remaining pins in columns 140 and 142, which together are configured to operate according to the SD and PCIe bus standard. The interface pins in row 104 and columns 140, 142 may be configured to operate according to other bus standards in further embodiments, including for example the UHS-II SD standard.

[0030] FIGS. 8A and 8B show interface pins 102 on a back and front surface, respectively, of SD card 100 according to a further embodiment of the present technology. In particular, a back surface 146 shown in FIG. 8A may include the legacy interface pins 102, and a front surface 148 shown in FIG. 8B may include the non-legacy pins 102. The surfaces which have the legacy and non-legacy pins 102 may be switched in further embodiments.

[0031] In embodiments, the interface pins 102 on surfaces 146 and 148 provide sixteen interface pins 102 supporting power, ground and signal transfer according to the SD and PCIe bus standard. However, there may be more or less pins than that in further embodiments. In one further example, there may be seventeen or eighteen interface pins 102, with eight pins on surface 146 and the remaining pins on surface 148, which together are configured to operate according to the SD and PCIe bus standard. The interface pins on surfaces 146 and 148 may be configured to operate according to other bus standards in further embodiments, including for example the UHS-II SD standard.

[0032] The SD card 100 of FIGS. 8A and 8B may operate within the connector 120 shown in FIG. 6 using the legacy interface pins 102 on back surface 146 according to legacy data transfer standards. The non-legacy interface pins 102 on front surface 148 have no conflict with any non-OD contacts. In an alternative embodiment, the SD card 100 of FIGS. 8A and 8B may be used in a connector slot that may have the legacy SD contacts on a first surface of the slot (as in FIG. 6) for mating with the legacy interface pins 102 on back surface 146. The connector slot in this alternative embodiment may further include non-legacy SD contacts on a second surface of the slot, opposed to the first surface, for mating with the non-legacy interface pins 102 on front surface 148. In such an embodiment, data may be transferred to/from the SD card 100 at the enhanced data transfer rates of, for example, the PCIe, UHS-II or other standards.

[0033] FIG. 9 shows a SD card 100 including a row 104 of legacy interface contacts 102 as described above. The embodiment of FIG. 9 further includes a single column 150 of horizontally oriented interface pins 102. It is understood the number and functionality of the interface pins 102 in column 150 may vary in further embodiments, based for example in part on functionality of the respective pins 102. The vertical position (i.e., along the length dimension of the SD card 100) of the pins 102 in the column 150 may vary from that shown in FIG. 9 in further embodiments.

[0034] In embodiments, the row 104 and columns 150 provide sixteen interface pins 102 supporting power, ground and signal transfer according to the SD and PCIe bus standard. However, there may be more or less pins than that in further embodiments. In one further example, there may be seventeen or eighteen interface pins 102, with eight pins 102 in row 104 and the remaining interface pins in column 150, which together are configured to operate according to the SD and PCIe bus standard. The interface pins in row 104 and column 150 may be configured to operate according to other bus standards in further embodiments, including for example the UHS-II SD standard.

[0035] FIG. 10 shows a SD card 100 including a row 104 of legacy interface contacts 102 as described above. The embodiment of FIG. 10 further includes a single row 152 of vertically oriented interface pins 102. It is understood the number and functionality of the interface pins 102 in row 152 may vary in further embodiments, based for example in part on functionality of the respective pins 102. The vertical position of the pins 102 in the row 152 may vary from that shown in FIG. 10 in further embodiments.

[0036] In embodiments, the rows 104 and 152 provide seventeen interface pins 102 supporting power, ground and signal transfer according to the SD and PCIe bus standard. However, there may be more or less pins than that in further embodiments. In one further example, there may be sixteen or eighteen interface pins 102, with eight pins 102 in row 104 and the remaining interface pins in row 152, which together are configured to operate according to the SD and PCIe bus standard. The interface pins in rows 104 and 152 may be configured to operate according to other bus standards in further embodiments, including for example the UHS-II SD standard.

[0037] In embodiments described above, the non-legacy interface pins 102 of SD card 100 may avoid all conflict with the non-OD contacts. That is, the non-legacy interface pins 102 of SD card 100 may be located at positions which do not overlap with any non-SD contacts when the SD card 100 is inserted into the slot.

[0038] However, in further embodiments, a first group of non-legacy interface pins 102 may avoid conflict with the non-OD contacts, while a second group of interface pins 102 may overlap non-OD contacts, but the conflict of the second group is managed by design. Such design may for example entail a default disconnection of the internal circuit to the second group of interface pins, and connecting them only when they are needed. In this regard, a conflict of some interface pins may not be resolvable by design (e.g., they need to be connected in their default state). Such interface pins need to avoid conflict by selective positioning of those interface pins away from non-OD contacts.

[0039] Two examples of this further embodiment will now be explained with reference to FIGS. 11 and 12. In FIGS. 11 and 12, the SD card 100 may include interface pins 1-8 in the first row, and 9-17 in the second row (9-18 in second row of FIG. 12). These interface pins 102 may be configured to operate according to the PCIe, UHS-II SD or other bus standard, but the size and vertical position of the interface pins are configured to, at least in part, avoid conflict with non SD contacts in a combo connector such as that shown in FIG. 6. For example, as noted above, when a conventional multi-row SD card is used in a ST19 Series 3-in-2 card connector from JAE, a conflict may exist between SD interface pins 9 and 17 and nano-SIM contact C3 (FIG. 6). A conflict may also exist between SD interface pins 14, 15 or 16 and nano-SIM contact C7.

[0040] The SD interface pins 14 and 15 may typically be RX/RX+ of PCIe, which is the output of differential interface that is expected to operate in high bit rates such as 8 Gb/s. Therefore, it would be difficult to protect this pins without degradation of their performance. The SD interface pin 16 is typically VSS (ground), which might short the nano-SIM contact C7 which is CLK output signal of the SIM. Accordingly, conflict with these pins is avoided by making these pins smaller in length and/or moving these pins nearer to the first row (or elsewhere on the SD card), as shown in FIGS. 11 and 12, to avoid conflict with the nano-SIM contact C7.

[0041] In contrast, the SD interface pins 9 and 17 may typically be used as either power supply or single ended input output signal lines. These pins are less critical, and, to the extent a conflict may exist with nano-SIM contact C3, the conflict can be resolved by design, such as default disconnection, and connecting them when needed.

[0042] The solution of FIGS. 11 and 12 for example provides a simple solution that eliminates conflicts for certain interface pins (14, 15 and 16), while keeping the rest of the contacts of existing connectors in the same horizontal position. By keeping the same horizontal position, the same contact path is kept in push-pull and push-push type of connectors used for such cards in the market. Such a solution minimizes effort in feasibility study, standardization and implementation.

[0043] The solution of FIG. 12 for example provides a simple solution that eliminates conflicts for certain interface pins (14, 15 and 16), while keeping the rest of the contacts of existing connectors in the same position as of existing SD UHS-II card. Such a solution further minimizes effort in feasibility study, standardization and implementation.

[0044] The examples set forth in FIGS. 5 and 7-12 are not intended to be exhaustive of all possible positions for the non-legacy interface pins 102. It is understood that the non-legacy interface pins may be provided in a wide variety of other configurations to avoid conflict with SIM contacts in a ST19 Series 3-in-2 card connector from JAE.

[0045] It is also understood that the present technology is not limited only to repositioning of non-legacy interface pins 102 to avoid conflict with the host contacts of a ST19 Series 3-in-2 card connector from JAE. The present technology may reposition non-legacy interface pins 102 in a wide variety of other locations to avoid conflict with the host contacts of any of a wide variety of other combination card connectors in further embodiments, some of which are shown in the figures.

[0046] In summary, the present technology relates to a microSD (SD) card configured for insertion in a combo slot comprising SD and non-SD contacts, the SD card comprising: a first group of interface pins configured to mate with the SD contacts upon insertion of the SD card into the combo slot; and a second group of one or more interface pins whose positions are configured to avoid contact with the non-SD contacts in the combo slot upon insertion of the SD card into the combo slot.

[0047] In another example, the present technology relates to a microSD (OD) card, comprising: a first group of interface pins configured to mate with SD contacts upon insertion of the SD card into a ST19 Series 3-in-2 card connector of the host device; and a second group of one or more interface pins whose positions have been configured to avoid contact with nano-SIM contacts upon insertion of the SD card into a ST19 Series 3-in-2 card connector of the host device.

[0048] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.