Abstract
A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.
Claims
1. A 3D semiconductor device, the device comprising: first transistors; second transistors, overlaying said first transistors; third transistors, overlaying said second transistors; and fourth transistors, overlaying said third transistors, wherein said second transistors, said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step, wherein at least one said third transistors comprises a source, channel, and drain, and wherein said source, said channel, and said drain have a similar doping type, and wherein at least one of said first transistors is part of a control circuit controlling at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors.
2. The device according to claim 1, further comprising: a memory peripheral circuit, wherein said memory peripheral circuit comprises said control circuit.
3. The device according to claim 1, wherein said third transistors each comprises a polysilicon channel.
4. The device according to claim 1, wherein at least one of said second transistors comprises SiGe.
5. The device according to claim 1, wherein said first transistors each comprises a single crystal channel.
6. The device according to claim 1, further comprising: a memory cell, wherein said memory cell comprises at least one of said third transistors.
7. The device according to claim 1, further comprising: a memory peripheral circuit, wherein said memory peripheral circuit comprises at least one of said first transistors.
8. A 3D semiconductor device, the device comprising: first transistors; second memory cells, atop said first transistors; third memory cells, atop said second memory cells; and fourth memory cells, atop said third memory cells, wherein at least one of said second memory cells, at least one of said third memory cells and at least one of said fourth memory cells are self-aligned, being processed following the same lithography step, wherein said third memory cells comprise third transistors, wherein at least one of said third transistors comprises a source, channel, and drain, wherein said source, said channel, and said drain have a similar doping type, and wherein at least one of said first transistors is part of a control circuit, said control circuit controlling at least one of said second memory cells, at least one of said third memory cells and at least one of said fourth memory cells.
9. The device according to claim 8, further comprising: a memory peripheral circuit, wherein said memory peripheral circuit comprises said control circuit.
10. The device according to claim 8, wherein said third memory cells each comprises a polysilicon channel transistor.
11. The device according to claim 8, wherein said third memory cells each comprises at least one second transistor which comprises SiGe.
12. The device according to claim 8, wherein said first transistors each comprises a single crystal channel.
13. The device according to claim 8, wherein said control circuit functions as a memory peripheral circuit.
14. The device according to claim 8, further comprising: a memory peripheral circuit, wherein said memory peripheral circuit comprises at least one of said first transistors.
15. A 3D semiconductor device, the device comprising: first transistors; second transistors, overlaying said first transistors; third transistors, overlaying said second transistors; fourth transistors, overlaying said third transistors, wherein said second transistors, said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step; and a memory peripheral circuit, wherein said memory peripheral circuit comprises at least one of said first transistors, and wherein said memory peripheral circuit controls at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors.
16. The device according to claim 15, wherein at least one said third transistors comprises a source, channel, and drain, and wherein said source, said channel, and said drain have a similar doping type, and wherein said third transistors each comprises a single crystal channel.
17. The device according to claim 15, wherein at least one said third transistors comprises a source, channel, and drain, and wherein said source, said channel, and said drain have a similar doping type, and wherein said third transistors each comprises a polysilicon channel.
18. The device according to claim 15, wherein at least one said third transistors comprises a source, channel, and drain, and wherein said source, said channel, and said drain have a similar doping type; and wherein at least one of said third transistors comprises SiGe.
19. The device according to claim 15, wherein said first transistors each comprises a single crystal channel.
20. The device according to claim 15, further comprising: a memory cell, wherein said memory cell comprises at least one of said third transistors.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Various embodiments of the invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
(2) FIGS. 1A-1D show different types of junction-less transistors (JLT) that could be utilized for 3D stacking;
(3) FIGS. 2A-2K show a zero-mask per layer 3D floating body DRAM;
(4) FIGS. 3A-3J show a zero-mask per layer 3D resistive memory with a junction-less transistor;
(5) FIGS. 4A-4K show an alternative zero-mask per layer 3D resistive memory;
(6) FIGS. 5A-5G show a zero-mask per layer 3D charge-trap memory;
(7) FIGS. 6A-6B show periphery on top of memory layers;
(8) FIGS. 7A-7E show polysilicon select devices for 3D memory and peripheral circuits at the bottom according to some embodiments of the current invention; and
(9) FIGS. 8A-8F show polysilicon select devices for 3D memory and peripheral circuits at the top according to some embodiments of the current invention.
DETAILED DESCRIPTION
(10) Embodiments of the present invention are now described with reference to FIGS. 1-8, it being appreciated that the figures illustrate the subject matter not to scale or to measure. Many figures describe process flows for building devices. These process flows, which are essentially a sequence of steps for building a device, have many structures, numerals and labels that are common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in previous steps' figures.
(11) FIG. 1A-1D shows that JLTs that can be 3D stacked fall into four categories based on the number of gates they use: One-side gated JLTs as shown in FIG. 1A, two-side gated JLTs as shown in FIG. 1B, three-side gated JLTs as shown in FIG. 1C, and gate-all-around JLTs as shown in FIG. 1D. The JLTS shown may include n+Si 102, gate dielectric 104, gate electrode 106, n+ source region 108, n+ drain region 110, and n+ region under gate 112. As the number of JLT gates increases, the gate gets more control of the channel, thereby reducing leakage of the JLT at 0V. Furthermore, the enhanced gate control can be traded-off for higher doping (which improves contact resistance to source-drain regions) or bigger JLT cross-sectional areas (which is easier from a process integration standpoint). However, adding more gates typically increases process complexity.
(12) Some embodiments of this invention may involve floating body DRAM. Background information on floating body DRAM and its operation is given in Floating Body RAM Technology and its Scalability to 32nm Node and Beyond, Electron Devices Meeting, 2006. IEDM '06. International , vol., no., pp.1-4, 11-13 Dec. 2006 by T. Shino, N. Kusunoki, T. Higashi, et al., Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond, Solid-State Electronics, Volume 53, Issue 7, Papers Selected from the 38th European Solid-State Device Research ConferenceESSDERC'08, July 2009, Pages 676-683, ISSN 0038-1101, DOI: 10.1016/j.sse.2009.03.010 by Takeshi Hamamoto, Takashi Ohsawa, et al., New Generation of Z-RAM, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, vol., no., pp.925-928, 10-12 Dec. 2007 by Okhonin, S.; Nagoga, M.; Carman, E, et al. The above publications are incorporated herein by reference.
(13) FIG. 2A-K describe a process flow to construct a horizontally-oriented monolithic 3D DRAM. This monolithic 3D DRAM utilizes the floating body effect and double-gate transistors. No mask is utilized on a per-memory-layer basis for the monolithic 3D DRAM concept shown in FIG. 2A-K, and all other masks are shared between different layers. The process flow may include several steps in the following sequence. Step (A): Peripheral circuits with tungsten wiring 202 are first constructed and above this a layer of silicon dioxide 204 is deposited. FIG. 2A shows a drawing illustration after Step (A). Step (B): FIG. 2B illustrates the structure after Step (B). A wafer of p? Silicon 208 has an oxide layer 206 grown or deposited above it. Following this, hydrogen is implanted into the p? Silicon wafer at a certain depth indicated by 214. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p? Silicon wafer 208 forms the top layer 210. The bottom layer 212 may include the peripheral circuits 202 with oxide layer 204. The top layer 210 is flipped and bonded to the bottom layer 212 using oxide-to-oxide bonding. Step (C): FIG. 2C illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane 3014 using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide 218 is then deposited atop the p? Silicon layer 216. At the end of this step, a single-crystal p? Si layer 216 exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques. Step (D): FIG. 2D illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p? silicon layers 220 are formed with silicon oxide layers in between. Step (E): FIG. 2E illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure, including layer regions of p? silicon 221 and associated isolation/bonding oxides 222. Step (F): FIG. 2F illustrates the structure after Step (F). Gate dielectric 226 and gate electrode 224 are then deposited following which a CMP is done to planarize the gate electrode 224 regions. Lithography and etch are utilized to define gate regions. Step (G): FIG. 2G illustrates the structure after Step (G). Using the hard mask defined in Step (F), p? regions not covered by the gate are implanted to form n+ silicon regions 228. Spacers are utilized during this multi-step implantation process and layers of silicon present in different layers of the stack have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, is then conducted to activate n+ doped regions. Step (H): FIG. 2H illustrates the structure after Step (H). A silicon oxide layer 230 is then deposited and planarized. For clarity, the silicon oxide layer is shown transparent, along with word-line (WL) 232 and source-line (SL) 234 regions. Step (I): FIG. 21 illustrates the structure after Step (I). Bit-line (BL) contacts 236 are formed by etching and deposition. These BL contacts are shared among all layers of memory. Step (J): FIG. 2J illustrates the structure after Step (J). BLs 238 are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory, VLSI Technology, 2007 IEEE Symposium on, vol., no., pp.14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (J) as well. FIG. 2K shows cross-sectional views of the array for clarity. Double-gated transistors may be utilized along with the floating body effect for storing information. A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistorsi.e. current flowing in substantially the horizontal direction in transistor channels (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
(14) With the explanations for the formation of monolithic 3D DRAM with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D DRAM array, and this nomenclature can be interchanged. Each gate of the double gate 3D DRAM can be independently controlled for better control of the memory cell. To implement these changes, the process steps in FIG. 2 may be modified. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown in FIG. 2A-K. Various other types of layer transfer schemes that have been described in Section 1.3.4 of the parent application (Ser. No. 12/901,890, U.S. Pat. No. 8,026,521) can be utilized for construction of various 3D DRAM structures. Furthermore, buried wiring, i.e. where wiring for memory arrays is below the memory layers but above the periphery, may also be used. In addition, other variations of the monolithic 3D DRAM concepts are possible.
(15) While many of today's memory technologies rely on charge storage, several companies are developing non-volatile memory technologies based on resistance of a material changing. Examples of these resistance-based memories include phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types is given in Overview of candidate device technologies for storage-class memory, IBM Journal of Research and Development, vol.52, no.4.5, pp.449-464, July 2008 by Burr, G. W.; Kurdi, B. N.; Scott, J. C.; Lam, C. H.; Gopalakrishnan, K.; Shenoy, R. S.
(16) FIGS. 3A-J describe a novel memory architecture for resistance-based memories, and a procedure for its construction. The memory architecture utilizes junction-less transistors and has a resistance-based memory element in series with a transistor selector. No mask is utilized on a per-memory-layer basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in FIG. 3A-J, and all other masks are shared between different layers. The process flow may include several steps that occur in the following sequence. Step (A): Peripheral circuits 302 are first constructed and above this a layer of silicon dioxide 304 is deposited. FIG. 3A shows a drawing illustration after Step (A). Step (B): FIG. 3B illustrates the structure after Step (B). A wafer of n+ Silicon 308 has an oxide layer 306 grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by 314. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted n+ Silicon wafer 308 forms the top layer 310. The bottom layer 312 may include the peripheral circuits 302 with oxide layer 304. The top layer 310 is flipped and bonded to the bottom layer 312 using oxide-to-oxide bonding. Step (C): FIG. 3C illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane 314 using either an anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide 318 is then deposited atop the n+ Silicon layer 316. At the end of this step, a single-crystal n+ Si layer 316 exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques. Step (D): FIG. 3D illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers 320 are formed with silicon oxide layers in between. Step (E): FIG. 3E illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure, including layer regions of n+ silicon 321 and associated bonding/isolation oxides 322. Step (F): FIG. 3F illustrates the structure after Step (F). Gate dielectric 326 and gate electrode 324 are then deposited following which a CMP is performed to planarize the gate electrode 324 regions. Lithography and etch are utilized to define gate regions. Step (G): FIG. 3G illustrates the structure after Step (G). A silicon oxide layer 330 is then deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL) 332 and source-line (SL) 334 regions. Step (H): FIG. 3H illustrates the structure after Step (H). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material 336 is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact 340. A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with junctionless transistors are created after this step. Step (I): FIG. 31 illustrates the structure after Step (I). BLs 338 are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in in Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory, VLSI Technology, 2007 IEEE Symposium on , vol., no., pp.14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be achieved in steps prior to Step (I) as well. FIG. 3J shows cross-sectional views of the array for clarity. A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistorsi.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
(17) FIGS. 4A-4K describe an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. No mask is utilized on a per-memory-layer basis for the monolithic 3D resistance change memory (or resistive memory) concept shown in FIGS. 4A-4K, and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence. Step (A): Peripheral circuits with tungsten wiring 402 are first constructed and above this a layer of silicon dioxide 404 is deposited. FIG. 4A shows a drawing illustration after Step (A). Step (B): FIG. 4B illustrates the structure after Step (B). A wafer of p? Silicon 408 has an oxide layer 406 grown or deposited above it. Following this, hydrogen is implanted into the p? Silicon wafer at a certain depth indicated by 414. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p? Silicon wafer 408 forms the top layer 410. The bottom layer 412 may include the peripheral circuits 402 with oxide layer 404. The top layer 410 is flipped and bonded to the bottom layer 412 using oxide-to-oxide bonding. Step (C): FIG. 4C illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane 414 using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide 418 is then deposited atop the p? Silicon layer 416. At the end of this step, a single-crystal p? Si layer 416 exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques. Step (D): FIG. 4D illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p? silicon layers 420 are formed with silicon oxide layers in between. Step (E): FIG. 4E illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure, including layer regions of p? silicon 421 and associated bonding/isolation oxide 422. Step (F): FIG. 4F illustrates the structure on after Step (F). Gate dielectric 426 and gate electrode 424 are then deposited following which a CMP is done to planarize the gate electrode 424 regions. Lithography and etch are utilized to define gate regions. Step (G): FIG. 4G illustrates the structure after Step (G). Using the hard mask defined in Step (F), p? regions not covered by the gate are implanted to form n+ silicon regions 428. Spacers are utilized during this multi-step implantation process and layers of silicon present in different layers of the stack have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, is then conducted to activate n+ doped regions. Step (H): FIG. 4H illustrates the structure after Step (H). A silicon oxide layer 430 is then deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL) 432 and source-line (SL) 434 regions. Step (I): FIG. 41 illustrates the structure after Step (I). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material 436 is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact 440. A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with transistors are created after this step. Step (J): FIG. 4J illustrates the structure after Step (J). BLs 438 are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory, VLSI Technology, 2007 IEEE Symposium on, vol., no., pp.14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (I) as well. FIG. 4K shows cross-sectional views of the array for clarity. A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistorsi.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control linese.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
(18) While explanations have been given for formation of monolithic 3D resistive memories with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D resistive memory array, and this nomenclature can be interchanged. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown in FIG. 3A-3J and FIG. 4A-4K. Various other types of layer transfer schemes that have been described in Section 1.3.4 of the parent application can be utilized for construction of various 3D resistive memory structures. One could also use buried wiring, i.e. where wiring for memory arrays is below the memory layers but above the periphery. Other variations of the monolithic 3D resistive memory concepts are possible.
(19) While resistive memories described previously form a class of non-volatile memory, others classes of non-volatile memory exist. NAND flash memory forms one of the most common non-volatile memory types. It can be constructed of two main types of devices: floating-gate devices where charge is stored in a floating gate and charge-trap devices where charge is stored in a charge-trap layer such as Silicon Nitride. Background information on charge-trap memory can be found in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, Artech House, 2009 by Bakir and Meindl (Bakir) and A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device, Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. The architectures shown in FIG. 5A-5G are relevant for any type of charge-trap memory.
(20) FIGS. 5A-5G describes a memory architecture for single-crystal 3D charge-trap memories, and a procedure for its construction. It utilizes junction-less transistors. No mask is utilized on a per-memory-layer basis for the monolithic 3D charge-trap memory concept shown in FIG. 5A-5G, and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence. Step (A): Peripheral circuits 502 are first constructed and above this a layer of silicon dioxide 504 is deposited. FIG. 5A shows a drawing illustration after Step (A). Step (B): FIG. 5B illustrates the structure after Step (B). A wafer of n+ Silicon 508 has an oxide layer 506 grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by 514. Alternatively, some other atomic species such as Helium could be implanted. This hydrogen implanted n+ Silicon wafer 508 forms the top layer 510. The bottom layer 512 may include the peripheral circuits 502 with oxide layer 504. The top layer 510 is flipped and bonded to the bottom layer 512 using oxide-to-oxide bonding. Step (C): FIG. 5C illustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane 514 using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide 518 is then deposited atop the n+ Silicon layer 516. At the end of this step, a single-crystal n+ Si layer 516 exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques. Step (D): FIG. 5D illustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers 520 are formed with silicon oxide layers in between. Step (E): FIG. 5E illustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure. Step (F): FIG. 5F illustrates the structure after Step (F). Gate dielectric 526 and gate electrode 524 are then deposited following which a CMP is done to planarize the gate electrode 524 regions. Lithography and etch are utilized to define gate regions. Gates of the NAND string 536 as well gates of select gates of the NAND string 538 are defined. Step (G): FIG. 5G illustrates the structure after Step (G). A silicon oxide layer 530 is then deposited and planarized. It is shown transparent in the figure for clarity. Word-lines, bit-lines and source-lines are defined as shown in the figure. Contacts are formed to various regions/wires at the edges of the array as well. SL contacts can be made into stair-like structures using techniques described in Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory, VLSI Technology, 2007 IEEE Symposium on, vol., no., pp.14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be performed in steps prior to Step (G) as well. A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistorsi.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control linese.g., bit lines BL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of single-crystal silicon obtained with ion-cut is a key differentiator from past work on 3D charge-trap memories such as A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device, Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. that used polysilicon.
(21) While FIGS. 5A-5G give two examples of how single-crystal silicon layers with ion-cut can be used to produce 3D charge-trap memories, the ion-cut technique for 3D charge-trap memory is fairly general. It could be utilized to produce any horizontally-oriented 3D monocrystalline-silicon charge-trap memory.
(22) While the 3D DRAM and 3D resistive memory implementations in Section 3 and Section 4 have been described with single crystal silicon constructed with ion-cut technology, other options exist. One could construct them with selective epi technology. Procedures for doing these will be clear to those skilled in the art.
(23) FIGS. 6A-6B show it is not the only option for the architecture to have the peripheral transistors, such as periphery 602, below the memory layers, including, for example, memory layer 604, memory layer 606, and/or memory layer 608. Peripheral transistors, such as periphery 610, could also be constructed above the memory layers, including, for example, memory layer 604, memory layer 606, and/or memory layer 608, and substrate or memory layer 612, as shown in FIG. 6B. This periphery layer would utilize technologies described in this application; parent application and incorporated references, and could utilize transistors, for example, junction-less transistors or recessed channel transistors.
(24) The monolithic 3D integration concepts described in this patent application can lead to novel embodiments of poly-silicon-based memory architectures as well. Poly silicon based architectures could potentially be cheaper than single crystal silicon based architectures when a large number of memory layers need to be constructed. While the below concepts are explained by using resistive memory architectures as an example, it will be clear to one skilled in the art that similar concepts can be applied to NAND flash memory and DRAM architectures described previously in this patent application.
(25) FIGS. 7A-7E show one embodiment of the current invention, where polysilicon junction-less transistors are used to form a 3D resistance-based memory. The utilized junction-less transistors can have either positive or negative threshold voltages. The process may include the following steps as described in the following sequence: Step (A): As illustrated in FIG. 7A, peripheral circuits 702 are constructed above which a layer of silicon dioxide 704 is made. Step (B): As illustrated in FIG. 7B, multiple layers of n+ doped amorphous silicon or polysilicon 706 are deposited with layers of silicon dioxide 708 in between. The amorphous silicon or polysilicon layers 706 could be deposited using a chemical vapor deposition process, such as LPCVD or PECVD. Step (C): As illustrated in FIG. 7C, a Rapid Thermal Anneal (RTA) is conducted to crystallize the layers of polysilicon or amorphous silicon deposited in Step (B). Temperatures during this RTA could be as high as 700? C. or more, and could even be as high as 800? C. The polysilicon region obtained after Step (C) is indicated as 710. Alternatively, a laser anneal could be conducted, either for all layers 706 at the same time or layer by layer. The thickness of the oxide 704 would need to be optimized if that process were conducted. Step (D): As illustrated in FIG. 7D, procedures similar to those described in FIGS. 3E-3H are utilized to construct the structure shown. The structure in FIG. 7D has multiple levels of junction-less transistor selectors for resistive memory devices. The resistance change memory is indicated as 736 while its electrode and contact to the BL is indicated as 740. The WL is indicated as 732, while the SL is indicated as 734. Gate dielectric of the junction-less transistor is indicated as 726 while the gate electrode of the junction-less transistor is indicated as 724, this gate electrode also serves as part of the WL 732. Silicon oxide is indicated as 730. Step (E): As illustrated in FIG. 7E, bit lines (indicated as BL 738) are constructed. Contacts are then made to peripheral circuits and various parts of the memory array as described in embodiments described previously.
(26) FIG. 8A-F show another embodiment of the current invention, where polysilicon junction-less transistors are used to form a 3D resistance-based memory. The utilized junction-less transistors can have either positive or negative threshold voltages. The process may include the following steps occurring in sequence: Step (A): As illustrated in FIG. 8A, a layer of silicon dioxide 804 is deposited or grown above a silicon substrate without circuits 802. Step (B): As illustrated in FIG. 8B, multiple layers of n+ doped amorphous silicon or polysilicon 806 are deposited with layers of silicon dioxide 808 in between. The amorphous silicon or polysilicon layers 806 could be deposited using a chemical vapor deposition process, such as LPCVD or PECVD abbreviated as above. Step (C): As illustrated in FIG. 8C, a Rapid Thermal Anneal (RTA) or standard anneal is conducted to crystallize the layers of polysilicon or amorphous silicon deposited in Step (B). Temperatures during this RTA could be as high as 700? C. or more, and could even be as high as 1400? C. The polysilicon region obtained after Step (C) is indicated as 810. Since there are no circuits under these layers of polysilicon, very high temperatures (such as 1400? C.) can be used for the anneal process, leading to very good quality polysilicon with few grain boundaries and very high mobilities approaching those of single crystal silicon. Alternatively, a laser anneal could be conducted, either for all layers 806 at the same time or layer by layer at different times. Step (D): This is illustrated in FIG. 8D. Procedures similar to those described in FIG. 32E-H are utilized to get the structure shown in FIG. 8D that has multiple levels of junctionless transistor selectors for resistive memory devices. The resistance change memory is indicated as 836 while its electrode and contact to the BL is indicated as 840. The WL is indicated as 832, while the SL is indicated as 834. Gate dielectric of the junctionless transistor is indicated as 826 while the gate electrode of the junction-less transistor is indicated as 824, this gate electrode also serves as part of the WL 832. Silicon oxide is indicated as 830. Step (E): This is illustrated in FIG. 8E. Bit lines (indicated as BL 838) are constructed. Contacts are then made to peripheral circuits and various parts of the memory array as described in embodiments described previously. Step (F): Using procedures described in Section 1 and Section 2 of this patent application's parent, peripheral circuits 898 (with transistors and wires) could be formed well aligned to the multiple memory layers shown in Step (E). For the periphery, one could use the process flow shown in Section 2 where replacement gate processing is used, or one could use sub-400? C. processed transistors such as junction-less transistors or recessed channel transistors. Alternatively, one could use laser anneals for peripheral transistors' source-drain processing. Various other procedures described in Section 1 and Section 2 could also be used. Connections can then be formed between the multiple memory layers and peripheral circuits. By proper choice of materials for memory layer transistors and memory layer wires (e.g., by using tungsten and other materials that withstand high temperature processing for wiring), even standard transistors processed at high temperatures (>1000? C.) for the periphery could be used.
(27) It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, drawings or illustrations may not show n or p wells for clarity in illustration. Further, combinations and sub-combinations of the various features described hereinabove may be utilized to form a 3D IC based system. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims.
