Bonded semiconductor wafer and method for manufacturing bonded semiconductor wafer

Abstract

A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.

Claims

1. A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the first dielectric layer.

2. The bonded semiconductor wafer according to claim 1, wherein the carrier trap layer is a polycrystalline silicon layer deposited on the base wafer.

3. The bonded semiconductor wafer according to claim 1, wherein the carrier trap layer is an ion-implanted layer formed by ion implantation into the base wafer.

4. The bonded semiconductor wafer according to claim 1, wherein the base wafer has a specific resistance of 4 k.Math.cm or less.

5. The bonded semiconductor wafer according to claim 2, wherein the base wafer has a specific resistance of 4 k.Math.cm or less.

6. The bonded semiconductor wafer according to claim 3, wherein the base wafer has a specific resistance of 4 k.Math.cm or less.

7. A method for manufacturing a bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, comprising the steps of: preparing a base wafer composed of a silicon single crystal; forming a first dielectric layer above the base wafer; forming a polycrystalline silicon layer on the first dielectric layer, and polishing the surface of the polycrystalline silicon layer; preparing a bond wafer composed of a silicon single crystal; forming a second dielectric layer on a surface of the bond wafer; bonding the base wafer and the bond wafer such that the polycrystalline silicon layer of the base wafer and the second dielectric layer of the bond wafer are in contact with each other; and thinning the bond wafer to form the single crystal silicon layer; and the method further comprising the step of forming a carrier trap layer between the base wafer and the first dielectric layer.

8. The method for manufacturing a bonded semiconductor wafer according to claim 7, wherein the carrier trap layer is formed by depositing the polycrystalline silicon layer on the base wafer.

9. The method for manufacturing a bonded semiconductor wafer according to claim 7, wherein the carrier trap layer is an ion-implanted layer and formed by ion implantation into the base wafer through the first dielectric layer.

10. The method for manufacturing a bonded semiconductor wafer according to claim 7, wherein the prepared base wafer has a specific resistance of 4 k.Math.cm or less.

11. The method for manufacturing a bonded semiconductor wafer according to claim 8, wherein the prepared base wafer has a specific resistance of 4 k.Math.cm or less.

12. The method for manufacturing a bonded semiconductor wafer according to claim 9, wherein the prepared base wafer has a specific resistance of 4 k.Math.cm or less.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a sectional view showing the bonded semiconductor wafer of Embodiment 1 according to the present invention;

(2) FIG. 2 is a sectional process view showing the method for manufacturing a bonded semiconductor wafer of Embodiment 1 according to the present invention;

(3) FIG. 3 is a sectional view showing the bonded semiconductor wafer of Embodiment 2 according to the present invention;

(4) FIG. 4 is a sectional process view showing the method for manufacturing a bonded semiconductor wafer of Embodiment 2 according to the present invention;

(5) FIG. 5 is a sectional view showing an example of a device produced by using the bonded semiconductor wafer of Embodiment 1 according to the present invention;

(6) FIG. 6 is a diagram showing a distribution of specific resistance in a depth direction of the bonded semiconductor wafer of Embodiment 1 according to the present invention;

(7) FIG. 7 is a diagram showing a distribution of specific resistance in a depth direction of the bonded semiconductor wafer of the conventional example;

(8) FIG. 8 is a sectional view showing the bonded semiconductor wafer of the conventional example.

DESCRIPTION OF EMBODIMENTS

Embodiment 1

(9) Hereinafter, the inventive bonded semiconductor wafer of Embodiment 1 will be described by reference to FIG. 1.

(10) FIG. 1 is a sectional view showing the bonded semiconductor wafer 14 of Embodiment 1 according to the present invention. In the inventive bonded semiconductor wafer 14 of Embodiment 1, the base wafer 1 is a single crystal substrate of silicon referred to as a so-called high specific resistance substrate, having a specific resistance value of 100 .Math.cm or more, preferably 500 .Math.cm or more, more preferably 1 k.Math.cm or more. The specific resistance value of base wafer has a feature such that when the value is about 1 k.Math.cm to 4 k.Math.cm, crystal pulling can be performed to target for the prescribed specific resistance value, and the high resistivity substrate can be produced in high productivity and stability at low cost. However, when the specific resistance value is 4 k.Math.cm or more, it is actual that the prescribed specific resistance value may not be achieved, and the specific resistance value involves many uncertainty elements on how much value will be attained until crystal pulling is performed, and the cost is raised consequently.

(11) On this base wafer 1, the carrier trap layer 2, the first dielectric layer 3, and the polycrystalline silicon layer 4 are formed successively. The carrier trap layer 2 is a polycrystalline silicon layer deposited on the base wafer 1. The first dielectric layer 3 can be formed by a CVD method, but may be formed by another method such as oxidizing the carrier trap layer (polycrystalline silicon layer) 2. The outermost face of the polycrystalline silicon layer 4 is polished to be good flatness by a CMP (Chemical Mechanical Polishing) method, for example, and functions as the bonding plane 18.

(12) The second dielectric layer 5 and the single crystal silicon layer 6 are bonded and delaminated by using a so-called smart cut method, which involves bonding from another substrate (a bond wafer), to complete a trap-rich type SOI substrate.

(13) Each thickness of the carrier trap layer (polycrystalline silicon layer) 2 and the polycrystalline silicon layer 4 may be in a typical value of about 2 m. The carrier trap layer (polycrystalline silicon layer) 2 acts to trap free carriers in the base wafer to prevent formation of an inversion layer on the face of the base wafer 1 at the side on which the carrier trap layer 2 has been formed. The second dielectric layer 5 is over the polycrystalline silicon layer 4 and the first dielectric layer 3 is under the polycrystalline silicon layer 4. This first dielectric layer 3 functions as a diffusion barrier to prevent unintentional impurities from diffusing into the base wafer 1, and can confine impurities and so on in the interior of the polycrystalline silicon layer 4 thereby. The polycrystalline silicon layer 4, being sandwiched between the dielectric layers, does not promote single-crystallization if high-temperature heat treatment is performed. In this case, the lowering of the specific resistance due to unintentional impurities is smaller than in the case of single-crystallized. Each thickness of the first dielectric layer 3 and the second dielectric layer 5 may be a film thickness of 10 nm or more, preferably 100 nm to 400 nm. Since each of the first dielectric layer 3 and the second dielectric layer 5 is not too thin as described above, the thickness can be controlled easily, and the layers are stable without disappearing in high-temperature heat treatment. As described above, these first dielectric layer 3 and second dielectric layer 5 can be formed by CVD or thermal oxidation. It is needless to say that other dielectric material other than the oxide film (e.g., a nitride film, an oxynitride film) can bring the same effect.

(14) In the inventive bonded semiconductor wafer of Embodiment 1 shown in FIG. 1, unintentional impurities can be involved in the bonding plane 18. This reason is specifically considered such that phosphorus atoms or boron atoms, which are diffusion sources of n-type or p-type impurities, can adhere onto the wafer surface in various heat treatments by using an electric furnace; and metallic particles can adhere onto the wafer by mechanical contact as irregularly occurring phenomena. In the present invention, the second dielectric layer 5 and the first dielectric layer 3 lie over and under the polycrystalline silicon layer 4 as described above. They can prevent abnormal diffusion of impurities and can confine these unintentional impurities in the interior of the polycrystalline silicon layer 4 even though the impurities are adhered and involved in the bonding plane 18.

(15) The polycrystalline silicon layer 4 and the carrier trap layer (polycrystalline silicon layer) 2, each of which has a high specific resistance, lie under an active device, which is operated at radio-frequency and is formed on the single crystal silicon layer 6. Accordingly, the total thickness of the polycrystalline silicon layers is naturally thicker than that of the bonded semiconductor wafer 44 of the conventional example shown in FIG. 8, and distortion of radio-frequency and crosstalk signal are decreased for that, thereby making the substrate show excellent radio-frequency characteristic and be suitable for a radio-frequency integrated circuit. As described above, it is difficult to stably perform crystal growth of a base wafer having a specific resistance of 4 k.Math.cm or more, but the polycrystalline silicon layer used for the present invention can achieve a specific resistance of about 10 k.Math.cm relatively easily by controlling the deposition temperature and so on with an epitaxial equipment for silicon. In addition to that, since the polycrystalline silicon layers are laminated in two layers inserting the first dielectric layer; it is obvious that the inventive bonded semiconductor wafer has better radio-frequency characteristic compared to that of the bonded semiconductor wafer of the conventional example shown in FIG. 8.

(16) As described above, the structure of the inventive bonded semiconductor wafer 14 of Embodiment 1 shown in FIG. 1 is excellent in the productivity and repeatability. In addition, distortion of radio-frequency and the amount of crosstalk signals, which are important for forming a radio-frequency integrated circuit, can be largely decreased. Mass-production thereof is also possible, thereby making it possible to provide a bonded semiconductor wafer with excellent radio-frequency characteristic at low cost.

(17) Hereinafter, the inventive method for manufacturing a bonded semiconductor wafer of Embodiment 1 will be described by reference to the sectional production process view shown in FIG. 2.

(18) First, the base wafer 1 with the specific resistance of about 1 k.Math.cm composed of a silicon single crystal is prepared (the step of preparing a base wafer).

(19) Specifically, a silicon single crystal ingot with a specific resistance of about 1 k.Math.cm is grown by using a CZ (Czochralski) method, for example, with a prescribed amount of dopant being introduced into the raw material silicon melt. This silicon single crystal ingot is sliced into a thin disk shape, followed by subjecting to various steps such as chamfering, lapping, etching, and polishing to complete a wafer with a mirror surface (a mirror surface wafer), thereby preparing the base wafer 1 (see FIG. 2 (d)).

(20) In the present invention, the silicon single crystal is grown with a targeted specific resistance of the CZ single crystal being set to about 1 k.Math.cm at this stage, it is markedly easy to control the resistivity compared to the case targeting a specific resistance of more than 4 k.Math.cm, thereby making it possible to improve the yield in producing a silicon single crystal.

(21) In this step, it is preferable to prepare the base wafer 1 with a specific resistance of 4 k.Math.cm or less in order to obtain superior radio-frequency characteristic (a value near 4 k.Math.cm is preferable). Considering the current mass production technology of silicon single crystal, it is relatively easy to produce a silicon single crystal with a specific resistance of 4 k.Math.cm or less. Accordingly, by setting the base wafer 1 to be prepared to have a specific resistance of 4 k.Math.cm or less, it is possible to decrease the production cost for the bonded semiconductor wafer with superior radio-frequency characteristic compared to that of the conventional art.

(22) Then, the carrier trap layer (polycrystalline silicon layer) 2 is formed in a thickness of about 2 m so as to be in contact with the base wafer 1 (the step of forming a carrier trap layer, see FIG. 2 (e)). The carrier trap layer (polycrystalline silicon layer) 2 is normally formed by using an epitaxial equipment. The form of the epitaxial equipment includes an epi-reactor for depositing a single crystal silicon layer, but polycrystalline silicon, not a single crystal, can be deposited in any equipment by selecting conditions such as lowering of the deposition temperature. Thereafter, the first dielectric layer 3 is formed in a thickness of 400 nm, for example, on the upper surface of the carrier trap layer (polycrystalline silicon layer) 2 by a CVD method or thermal oxidation (the step of forming a first dielectric layer). Subsequently, the polycrystalline silicon layer 4 is formed again by using an epitaxial equipment on the surface of the first dielectric layer 3, and the surface is polished (the step of forming a polycrystalline silicon layer and polishing the surface). The polycrystalline silicon layer 4 may be also deposited in a thickness of about 2 m, for example. At this stage, the thicknesses of the carrier trap layer (polycrystalline silicon layer) 2 and the polycrystalline silicon layer 4 are not particularly limited. However, since the polycrystalline silicon layer 4 is flattened by polishing the uppermost surface to be a state that can be bonded with the bond wafer 11, too thin layer such as 1 m or less brings a problem of flatness. Accordingly, the thickness may be set to that value or more (see FIG. 2 (e)).

(23) Concurrently, the bond wafer 11 composed of a silicon single crystal is prepared (the step of preparing a bond wafer), and the second dielectric layer 5 is formed on the bond wafer 11 (the step of forming a second dielectric layer). Specifically, a silicon single crystal wafer is prepared as the bond wafer 11 (see FIG. 2 (a)), for example, and subjected to oxide film growth (e.g., thermal oxidation) to form the dielectric film 12 (see FIG. 2 (b)) to be the second dielectric layer 5 (see FIG. 2 (g)). The thickness of the dielectric film (oxide film) 12 can be several tens nm to several m, for example.

(24) In addition, hydrogen gas ions or rare gas ions are ion-implanted from above the dielectric film (oxide film) 12 by an ion implantation method to form the ion-implanted layer 13 to be a delaminating plane (see FIG. 2 (c)). In this case, an accelerating voltage of the ion implantation is selected so as to obtain a targeted thickness in the delaminated silicon layer (i.e., the single crystal silicon layer 6, see FIG. 2 (g)).

(25) Then, the base wafer 1 and the bond wafer 11 are bonded such that the polished surface of the polycrystalline silicon layer 4 of the base wafer 1 and the dielectric film (oxide film) 12 of the bond wafer are in contact with each other (the step of bonding a base wafer and a bond wafer, see FIG. 2 (f)).

(26) Subsequently, the bonded bond wafer is thinned to form the single crystal silicon layer 6 (the step of thinning a bond wafer to form a single crystal silicon layer). Specifically, the bonded wafer is subjected to heat treatment to evolve a micro bubble layer in the ion-implanted layer 13 (a delamination heat treatment), for example, and the bond wafer is delaminated along the evolved micro bubble layer to produce the bonded semiconductor wafer 14 in which the second dielectric layer 5 and the single crystal silicon layer 6 are formed on the base wafer 1 (see FIG. 2 (g)). At this stage, the delaminated wafer 17 having the delaminated surface 16 is derived.

(27) As described above, a so-called trap-rich type semiconductor wafer is completed. In the above, either of the (a) to (c) and the (d) to (e) in FIG. 2 can be performed earlier, and the both may be performed simultaneously.

(28) As described above, by manufacturing the bonded semiconductor wafer 14 using the inventive method for manufacturing a bonded semiconductor wafer of Embodiment 1, it is possible to stably provide a bonded semiconductor wafer that shows excellent secondary harmonic wave characteristic and extremely small change of specific resistance of the base wafer in high-temperature heat treatment when it is used as a semiconductor substrate for a radio-frequency integrated circuit.

Embodiment 2

(29) Hereinafter, the inventive bonded semiconductor wafer of Embodiment 2 will be described by reference to FIG. 3. FIG. 3 is a sectional view showing the bonded semiconductor wafer of Embodiment 2 according to the present invention. In the bonded semiconductor wafer 24 shown in FIG. 3, many of the basic structure, properties, and effects are common to those of the inventive bonded semiconductor wafer 14 of Embodiment 1 shown in FIG. 1. Accordingly, the differentiate are described below.

(30) In the bonded semiconductor wafer 24 of Embodiment 2 shown in FIG. 3, the carrier trap layer (ion-implanted layer) 7, which is a damaged layer by using an ion implantation method, is formed at the outermost layer part immediately under the face of the base wafer 1 instead of the carrier trap layer (polycrystalline silicon layer) 2 of the bonded semiconductor wafer 14 of Embodiment 1 shown in FIG. 1.

(31) In the ion implantation method, ions of an atom such as argon, helium, and oxygen are implanted into the base wafer 1, but the same effect can be obtained by implanting ions of another atom. Regarding the act of this carrier trap layer (ion-implanted layer) 7, many defects that are formed on the outermost face part of the base wafer 1 by ion implantation, forming a level to capture free carriers, function as an electron trap, for example, as the act of the carrier trap layer (polycrystalline silicon layer) 2. This brings an effect that the lifetimes of the free carriers are extremely short, and the base wafer 1 is prevented from forming an inversion layer at the main face side, which makes the specific resistance remain unchanged in accordance with potential. As a result, it is possible to maintain the effect that distortion of radio-frequency and crosstalk signals are small, and the radio-frequency characteristic is excellent due to the high specific resistance of the base wafer 1.

(32) As another effect of the carrier trap layer (ion-implanted layer) 7 using an ion implantation method, the process can be simplified, and the bonded semiconductor wafer can be improved in the flatness. That is, since the carrier trap layer (ion-implanted layer) 7 by ion implantation can be formed by ion implantation performed while penetrating the first dielectric layer 3, the polishing amount and time for polishing the polycrystalline silicon layer can be decreased compared to those of the inventive bonded semiconductor wafer 14 of Embodiment 1 shown in FIG. 1, in which the carrier trap layer (polycrystalline silicon layer) 2 and the polycrystalline silicon layer 4 are deposited twice; thereby being excellent in flatness, which is an important point to be determined in bonded semiconductor wafers.

(33) Hereinafter, the inventive method for manufacturing the bonded semiconductor wafer 24 of Embodiment 2 will be described by reference to the sectional production process view shown in FIG. 4. In the sectional process view of FIG. 4 showing the production method of the bonded semiconductor wafer 24 of Embodiment 2 according to the present invention, many parts are common to those in the sectional process view of FIG. 2 showing the production method of the bonded semiconductor wafer 14 of Embodiment 1 according to the present invention. Accordingly, the differentiate are described below.

(34) The base wafer 1 is prepared, and the carrier trap layer (ion-implanted layer) 7, which is a damaged layer formed by using an ion implantation method, is formed at the outermost layer part immediately under the surface of the base wafer 1 as shown in FIG. 4 (e) instead of forming the carrier trap layer (polycrystalline silicon layer) 2 of Embodiment 1 as shown in FIG. 2 (e) (the step of forming a carrier trap layer). In the ion implantation method, ions of an atom such as argon, helium, and oxygen are implanted into the base wafer 1, but the same effect can be obtained by implanting ions of another atom. This carrier trap layer (ion-implanted layer) 7 is formed such that the base wafer 1 is subjected to thermal oxidation in a prescribed film thickness such as a film thickness of 10 nm or more, preferably 100 nm to 400 nm to form the first dielectric layer 3, and then ion implantation is performed penetrating the first dielectric layer (oxide film) 3 to form the carrier trap layer immediately under the oxide film. After this step, the polycrystalline silicon layer 4 is deposited onto the first dielectric layer 3 with an epitaxial equipment, which step is shown in FIG. 4 (e).

(35) Since other steps of the inventive production method of the bonded semiconductor wafer 24 of Embodiment 2 in FIG. 4 are the same with those of the inventive production method of the bonded semiconductor wafer 14 of Embodiment 1 in FIG. 2, the specific explanation will be omitted. By manufacturing through such a flow, it is possible to stably provide a bonded semiconductor wafer that shows excellent secondary harmonic wave characteristic and extremely small change of specific resistance of the base wafer in high-temperature heat treatment when it is used as a semiconductor substrate for a radio-frequency integrated circuit.

(36) Subsequently, regarding a device formed on the bonded semiconductor wafer 14 of Embodiment 1 according to the present invention, a sectional view of an example of the device is shown in FIG. 5.

(37) In FIG. 5, a MOS type transistor is formed on the silicon layer 6 as the active region A by diffusion and so on. The metal electrode M is in ohmic contact with a drain domain and a source domain to pass current between the source S and the drain D. The gate oxide film 10 and the gate G are formed on a channel to control this current.

(38) The active region A is formed on a domain surrounded by the buried gutter 9, and passive elements and other active elements are formed on another device domain B. The structure of the inventive bonded semiconductor wafer 14 of Embodiment 1 can bring remarkably decreased radio-frequency electricity and noise leaked from the active region A to the domain B of other devices, extremely decreased interaction between the devices, and improved yield by performing operation according to the basic design by each device. In addition to that, the base wafer shows extremely small change in specific resistance when high-temperature heat treatment is performed. It is the character of the inventive bonded semiconductor wafer and the production method thereof that such an excellent radio-frequency integrated circuit can be mass-produced stably.

(39) It is to be noted that FIG. 5 shows an example of forming a device by using the inventive bonded semiconductor wafer 14 of Embodiment 1, but the device can be formed by using the inventive bonded semiconductor wafer 24 of Embodiment 2 in the same way, and the same effect can be obtained thereby.

(40) The distribution of specific resistance of bonded semiconductor wafers will be described regarding how the distribution in a depth direction is improved when adopting the structure of the inventive bonded semiconductor wafer 14 of Embodiment 1 by comparing FIG. 6 and FIG. 7.

(41) FIG. 6 is a diagram showing a distribution of specific resistance in a depth direction of the inventive bonded semiconductor wafer 14 of Embodiment 1. FIG. 7 is a diagram showing a distribution of specific resistance in a depth direction of the bonded semiconductor wafer 44 of the conventional example as described above. In the upper part of each graph showing a distribution of specific resistance in a depth direction, simplified sectional view of the bonded semiconductor wafer is shown so as to clearly illustrate the part where the specific resistance is shown in the graph by comparing them.

(42) In FIG. 6, the single crystal silicon layer 6 also has a specific resistance of 10 .Math.cm, and the base wafer 1 also has a specific resistance of 1 k.Math.cm as in the bonded semiconductor wafer of the conventional example in FIG. 7. Each of the carrier trap layer (polycrystalline silicon layer) 2 and the polycrystalline silicon layer 4 deposited by using an epitaxial equipment has a specific resistance of 10 k.Math.cm after the deposition. The first dielectric layer 3 and the second dielectric layer 5 shows very high specific resistance, but each specific resistance is described as 600 k.Math.cm on the graph.

(43) In the inventive bonded semiconductor wafer 14 of Embodiment 1, two substrates are bonded on the bonding plane 18. As described above, the bonding plane 18 can involve unintentional impurities. This reason is specifically considered such that phosphorus atoms or boron atoms, which are diffusion sources of n-type or p-type impurities, can adhere onto the wafer surface in various heat treatments by using an electric furnace; and metallic particles can adhere onto the wafer by mechanical contact as irregularly occurring phenomena.

(44) In the present invention, the second dielectric layer 5 and the first dielectric layer 3 lie on the both sides of the polycrystalline silicon layer 4 and can prevent diffusion of impurities even when such impurities are involved or adhered to the bonding plane 18, thereby confining these unintentional impurities in the interior of the polycrystalline silicon layer 4. As a result, the specific resistance of the base wafer is naturally unchanged, not only is the specific resistance of the carrier trap layer (polycrystalline silicon layer) 2 unchanged. This is a remarkable difference with the conventional example shown in FIG. 7, in which the specific resistance of the base wafer 31 is largely lowered. The polycrystalline silicon layer 4 is sandwiched between the first dielectric layer 3 and the second dielectric layer 5, thereby being extremely difficult to single-crystallize. This is also the reason why the specific resistance of the polycrystalline silicon layer 4 is unchanged. In a polycrystalline silicon layer, decrease of the specific resistance is scarcely observed even when slight impurities have been diffused. The absence of lowering of the specific resistance is equivalent to the maintenance of the excellent radio-frequency characteristic. In the inventive bonded semiconductor wafer 14 of Embodiment 1, excellent radio-frequency characteristic can be realized since the distribution of specific resistance in a depth direction shown in FIG. 6 can be realized, and change and lowering of the specific resistance is extremely small.

(45) It is to be noted that the above has described the distribution of specific resistance in a depth direction of the inventive bonded semiconductor wafer 14 of Embodiment 1, but similar distribution of specific resistance in a depth direction and the same effects can be obtained in the inventive bonded semiconductor wafer 24 of Embodiment 2.

(46) In a radio-frequency integrated circuit formed on the inventive bonded semiconductor wafer in which the circuit is composed of a passive element and an active element, not only a passive element, to handle radio-frequency signals of several GHz used for mobile phones and so on, the radio-frequency is less distorted, signals treated on one circuit is prevented from crosstalk to another neighboring circuit or interfering with signals of another circuit mutually, and each circuit block can be operated as designed.

(47) Specifically, in a bonded semiconductor wafer provided with the base wafer 1 composed of a silicon single crystal, having the first dielectric layer 3, the polycrystalline silicon layer 4, the second dielectric layer 5, and the single crystal silicon layer 6 above the base wafer in this order, with the carrier trap layer (2 or 7) being formed between the base wafer 1 and the first dielectric layer 3; the first dielectric layer 3, being set to 10 nm or more and several m or less, for example, can prevent the polycrystalline silicon layer 4 from single-crystallization and securely functions as a diffusion barrier to unintentional impurities into the base wafer 1. Immediately under the first dielectric layer 3, the carrier trap layer (2 or 7) lies and functions to trap free carriers to prevent formation of the inversion layer 45. Accordingly, it is possible to provide a bonded semiconductor wafer with excellent radio-frequency characteristic that can be mass-produced at a lower cost with its stable properties and good yield.

EXAMPLE

(48) Hereinafter, the present invention will be more specifically described by showing Examples and Comparative Example, but the present invention is not limited thereto.

Examples 1 and 2

(49) The inventive bonded semiconductor wafers (14 and 24) of Embodiment 1 and Embodiment 2 having structures of FIG. 1 and FIG. 3 were produced under the conditions described in Table 1. Onto each silicon single crystal layer (SOI layer) 6 of the outermost surface, a radio-frequency integrated circuit device was produced.

(50) On each produced device, the secondary harmonic wave characteristic was evaluated. The results are also described in Table 1. It is to be noted that smaller secondary harmonic wave shows superior properties of device. In each bonded semiconductor wafer used for producing the radio-frequency integrated circuit device, the specific resistance was also measured on the face of the base wafer. The results are also described in Table 1.

(51) TABLE-US-00001 TABLE 1 Example 1 (FIG. 1) Example 2 (FIG. 3) <Structure> Single crystal Si SOI layer 160 nm SOI layer 160 nm layer Second dielectric BOX layer 400 nm BOX layer 400 nm layer Polycrystalline Si Polycrystalline 2 m Polycrystalline 2 m layer Si layer Si layer First dielectric SiO2 layer 400 nm SiO2 layer 200 nm layer Carrier trap layer Polycrystalline 2 m Ion-implanted Ar, Si layer layer 1E16/cm.sup.2 Base wafer 1000 .Math. cm 1000 .Math. cm (specific resistance) <Effect> Secondary 86 dBm 84 dBm harmonic wave Base wafer face 1000 .Math. cm 1000 .Math. cm (specific resistance)

Comparative Example

(52) The bonded semiconductor wafer 44 having the structure of the conventional example shown in FIG. 8 was produced under the conditions shown in Table 2. Onto the silicon single crystal layer (SOI layer) 36 of the outermost surface, a radio-frequency integrated circuit device was produced.

(53) On the produced device, the secondary harmonic wave characteristic was evaluated. The results are also described in Table 2. In the bonded semiconductor wafer used for producing the radio-frequency integrated circuit device, the specific resistance was also measured on the face of the base wafer. The results are also described in Table 2.

(54) TABLE-US-00002 TABLE 2 Comparative Example (FIG. 8) <Structure> Single-crystal Si layer SOI layer 160 nm Second dielectric layer BOX layer 400 nm Polycrystalline Si Polycrystalline 2 m layer Si layer Dielectric thin film SiO2 layer 2 nm Base wafer 1000 .Math. cm (specific resistance) <Effect> Secondary harmonic wave 30 dBm Base wafer face 6 .Math. cm (specific resistance)

(55) In each of the bonded semiconductor wafers of Examples, the face of the base wafer did not show lowering of the specific resistance due to impurities involved in the bonding plane, and superior secondary harmonic wave characteristic was obtained thereby compared to the bonded semiconductor wafer of Comparative Example.

(56) It is to be noted that the present invention is not limited to the foregoing embodiment. The embodiment is just an exemplification, and any examples that have substantially the same feature and demonstrate the same functions and effects as those in the technical concept described in claims of the present invention are included in the technical scope of the present invention.