Formation of field-tunable silicon carbide defect qubits with optically transparent electrodes and silicon oxide surface passivation
10262871 ยท 2019-04-16
Assignee
Inventors
- Osama Nayfeh (San Diego, CA, US)
- Anna Leese de Escobar (San Diego, CA, US)
- Brad Liu (San Diego, CA, US)
- Patrick Sims (San Diego, CA, US)
- Sam Carter (Waldorf, MD, US)
- David Kurt Gaskill (Alexandria, VA)
- Tom Reinecke (Alexandria, VA, US)
Cpc classification
H01L21/049
ELECTRICITY
B82Y40/00
PERFORMING OPERATIONS; TRANSPORTING
H01L29/66977
ELECTRICITY
H01L21/322
ELECTRICITY
G06N10/00
PHYSICS
B82Y10/00
PERFORMING OPERATIONS; TRANSPORTING
H01L29/423
ELECTRICITY
H01L21/76826
ELECTRICITY
G02F1/0054
PHYSICS
International classification
H01L21/311
ELECTRICITY
H01L21/04
ELECTRICITY
H01L21/02
ELECTRICITY
G06N10/00
PHYSICS
C30B25/10
CHEMISTRY; METALLURGY
H01L21/027
ELECTRICITY
G02F1/00
PHYSICS
H01L21/768
ELECTRICITY
Abstract
A method includes depositing a layer of silicon oxide onto a layer of silicon carbide; ion implanting the layer of silicon carbide, annealing the ion implanted layer of silicon carbide to produce defects within the layer of silicon carbide, performing photolithography using a mask layer on regions of the layer of silicon carbide to define regions for electrode deposition, removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition, forming one or more electrodes by depositing indium tin oxide (ITO) in each of the regions for electrode deposition, performing a first lift-off operation to remove the mask layer surrounding the electrodes, depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes, and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.
Claims
1. A method comprising the steps of: depositing a layer of silicon oxide onto a layer of silicon carbide; ion implanting the layer of silicon carbide; annealing the ion implanted layer of silicon carbide to produce defects within the layer of silicon carbide; performing photolithography using a mask layer on one or more regions of the layer of silicon carbide to define one or more regions for electrode deposition; removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition; forming one or more electrodes by depositing indium tin oxide (ITO) in each of the one or more regions for electrode deposition; performing a first lift-off operation to remove the mask layer surrounding the electrodes; depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes; and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.
2. The method of claim 1, wherein the step of ion implanting is performed using .sup.12C.
3. The method of claim 1, wherein the step of ion implanting is performed using an energy level between a range of about 20 keV to about 50 keV.
4. The method of claim 1, wherein the step of annealing is performed at a temperature between a range of about 900 degrees Celsius to about 1000 degrees Celsius.
5. The method of claim 1, wherein the step of removing the layer of silicon oxide from the layer of silicon carbide is performed using a dilute H.sub.2O:HF etch.
6. The method of claim 1, wherein the step of depositing ITO is performed by RF sputtering at 200 W in argon.
7. The method of claim 1, wherein the step of performing a first lift-off operation is performed in acetone with ultrasonic agitation.
8. The method of claim 1, wherein the step of depositing a layer of silicon oxide onto a layer of silicon carbide is performed by atomic layer deposition.
9. The method of claim 1, wherein the layer of silicon carbide comprises 4H silicon carbide.
10. The method of claim 1, wherein the layer of silicon carbide comprises 6H silicon carbide.
11. A method comprising the steps of: depositing a layer of silicon oxide onto a layer of silicon carbide using atomic layer deposition; ion implanting the layer of silicon carbide using .sup.12C using an energy level between a range of about 20 keV to about 50 keV; annealing the ion implanted layer of silicon carbide at a temperature between a range of about 900 degrees Celsius to about 1000 degrees Celsius to produce defects within the layer of silicon carbide; performing photolithography on one or more regions of the layer of silicon carbide to define one or more regions for electrode deposition; removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition using a dilute H.sub.2O:HF etch; depositing indium tin oxide (ITO) in each of the one or more regions for electrode deposition; performing a first lift-off operation to remove the mask layer surrounding the electrodes; depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes; and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.
12. The method of claim 11, wherein the step of depositing ITO is performed by RF sputtering at 200 W in argon.
13. The method of claim 1, wherein the step of performing a first lift-off operation is performed in acetone with ultrasonic agitation.
14. The method of claim 1, wherein the layer of silicon carbide comprises one of 4H silicon carbide and 6H silicon carbide.
15. A method comprising the steps of: depositing a layer of silicon oxide onto a layer of silicon carbide using atomic layer deposition, wherein the layer of silicon carbide comprises one of 4H silicon carbide and 6H silicon carbide; ion implanting the layer of silicon carbide using .sup.12C using an energy level between a range of about 20 keV to about 50 keV; annealing the ion implanted layer of silicon carbide at a temperature between a range of about 900 degrees Celsius to about 1000 degrees Celsius to produce defects within the layer of silicon carbide; performing photolithography on one or more regions of the layer of silicon carbide to define one or more regions for electrode deposition; removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition using a dilute H.sub.2O:HF etch; depositing indium tin oxide (ITO) in each of the one or more regions for electrode deposition using RF sputtering at 200 W in argon; performing a first lift-off operation to remove the mask layer surrounding the electrodes by using acetone with ultrasonic agitation; depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes; and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION OF SOME EMBODIMENTS
(20) Reference in the specification to one embodiment or to an embodiment means that a particular element, feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment. The appearances of the phrases in one embodiment, in some embodiments, and in other embodiments in various places in the specification are not necessarily all referring to the same embodiment or the same set of embodiments.
(21) Some embodiments may be described using the expression coupled and connected along with their derivatives. For example, some embodiments may be described using the term coupled to indicate that two or more elements are in direct physical or electrical contact. The term coupled, however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments are not limited in this context.
(22) As used herein, the terms comprises, comprising, includes, including, has, having or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, or refers to an inclusive or and not to an exclusive or.
(23) Additionally, use of the a or an are employed to describe elements and components of the embodiments herein. This is done merely for convenience and to give a general sense of the invention. This detailed description should be read to include one or at least one and the singular also includes the plural unless it is obviously meant otherwise.
(24) The disclosed embodiments include a method for constructing silicon carbide defect qubits by ion implantation and high temperature annealing to form vacancies. Optically transparent indium tin oxide (ITO) electrodes are integrated in a layout suitable for microwave/RF excitation and optical input/output. The surface is passivated by an atomic layer deposited silicon oxide thin film to preserve the vacancy configurations. The devices are formed through 12C ion implantation and high-temperature annealing of 4H and 6H silicon carbide. The processing of the disclosed embodiments results in good contact being formed between ITO and SiC. The photoluminescence (PL) signature of silicon vacancies is readily detected both in the silicon oxide/silicon carbide (SiC) and ITO/SiC regions and is consistent with emission in SiC only regions. The density of vacancies is estimated and lower dose implant is found to result in a consistent reduction in the vacancy densities.
(25) A qubit is a two-level system that can be based on atoms, ions, quantum dots or even defects in crystals. The difference between these two-level systems and those based on classical objects are that they obey quantum mechanics and thus can permit quantum physics operation such as tunneling and entanglement on these two levels that effectively comprise quantum information states |0> and |1>. Using defects in crystals for qubits is advantageous in that they can be constructed using micro-nanofabrication techniques and can benefit from many of the advantages of high tech electronics such as scalability, low cost, large scale integration, compatibility with supporting components etc. There are a few types of solid state qubits being investigated worldwide and these include nitrogen vacancies in diamond, dopants in silicon, vacancies in silicon carbide and rare-earth ions in crystals. Regardless of the type of system used, the atom-like element must meet certain criteria to be used as a qubit.
(26) Vacancy defects in silicon-carbide are being pursued for use as qubits due to meeting several criteria specifically regarding spin states that can be controlled (i.e. rotated and flipped) with substantial quantum coherence time of these spin states via optical and microwave excitation, a kind of hybrid process that combines concepts from nuclear/electronic magnetic resonance and spintronic that can be implemented in the solid state with atom-like defects in a host crystal.
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(29) According to recent density functional theory and experimental validation analysis, the physical effects behind a possible electric field tuning captured via an effective Stark-like effect of the qubit response is due largely to a combination of distortion of the atomic/ionic lattice as well as direct field-induced shifts of the wave-functions, where the latter is expected to be greater. Owing to the high polarizability with dielectric constant of 10 of SiC, the effects can be quite substantial and even stronger than that of diamond crystals.
(30) The embodiments of the methods disclosed herein address the need to passivate the surface of a silicon carbide defect qubit device to protect the vacancy configuration and the need to integrate contacts that are optically transparent so that the qubit can be excited and the optical emission can be detectable from the regions beneath the contacts. The embodiments of the disclosed methods further address implementation of a layout where microwave power can be inputted at frequencies commensurate with the driving frequencies for the energy level of the transitions of the qubit system. The embodiments of the disclosed methods also provide the ability to apply electric field in the c-axis direction (i.e. between contact and bottom of wafer) as well as in two-dimensions, i.e. in the channel region between contacts.
(31) The tunability of the qubits is enabled by utilizing the gates to immerse the qubits in an electric field and, by virtue of the Hamiltonian that is impacted, the qubit energy levels and spin transitions are modified. The tunability is also enabled by confining the qubit in an electrostatic potential created near the surface with a gate insulator sandwiched to further split the bands. For further control, the qubit can be embedded in the quantum well of a heterostructure formed between for example 4H SiC and Si or a crystalline insular with suitable energy barriers.
(32) In order to understand the operation of the qubits and to quantify the anticipated tuning of the qubit properties, a spin Hamiltonian model is employed and it is modified to include a term in the Hamiltonian corresponding to electric field. The objective is to recalculate the effect of electric field on the energy levels and resulting ODMR spectra, to search for possibility of tuning the ODMR or even discovery of potential for new transitions if significant perturbation of the energy levels is expected. The Hamiltonian considered without electric field is
H=g.sub.B{right arrow over (B)}.Math.{right arrow over (S)}+DS.sub.z.sup.2+H.sub.hf(Eq. 1)
where g is the electron factor, .sub.B is the Bohr magneton, {right arrow over (B)} is the magnetic field, 2D is the zero-magnetic field splitting parameter, {right arrow over (S)} is the vector of spin 3/2, and H.sub.hf is considering the hyperfine interaction between the next nearest neighbor (NNN) .sup.29Si nuclear spin and the silicon vacancy (defect) spin. Looking at the full lattice description and full band-structure it is possible that other factors contribute to the overall response of the material, but for the atom-like description and the regime of excitation, these elements are the primary factors of interest to the Hamiltonian in this analysis in describing the system and the elements that can be engineered. Further details on the model can be found in a publication by Carter et al., titled Spin Coherence and Echo Modulation of the Silicon Vacancy in 4HSiC at Room Temperature, Physical Review B, vol. 92, issue 16 (2015), the content of which is fully incorporated by reference herein.
(33) For the embodiments disclosed herein, an additional term is added to consider the effect of the electric field and to examine the impact on the energy levels as a function of magnetic field as well as the calculated optically detected magnetic resonance (ODMR) spectra. Based upon a recent publication by Falk et al., entitled Optical Polarization of Nuclear Spins in Silicon Carbide, Physical Review Letters, vol. 2, issue 24 (2014), the content of which is fully incorporated by reference herein, the modified Hamiltonian becomes with the H.sub.hf term expanded to include electric field matrices.
H=g.sub.B{right arrow over (B)}.Math.{right arrow over (S)}+DS.sub.Z.sup.2+(H.sub.hfE.sub.x(.sub.x.sup.2.sub.y.sup.2)+E.sub.y(.sub.x.sub.y+.sub.y.sub.x))(Eq. 2)
where E.sub.x and E.sub.y are field splitting parameters in the x and y directions, respectively, and .sub.x.sup.2 and .sub.y.sup.2 are the respective components of the appropriate spin vector for the Si vacancy.
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(35) Starting materials are 4 4H and 6H purity semi-insulating silicon carbide, as well as 4 silicon control wafers for comparison. As an example, the wafers were diced into 19.5-x 19.5-mm squares. The size of the diced pieces may be varied based upon factors, such as, for example, ensuring compatibility with the thermal annealing furnace used in the process and making the source large enough to ensure that a device nears the center of the sample is minimally impacted by human wafer handling in the clean-room.
(36) After dicing, 8 nm of silicon oxide (SiOx) was deposited by atomic layer deposition (ALD) to serve as an implant and annealing cap. ALD is beneficial in that it is performed at a low temperature and does not disrupt the qubit properties. It should be noted that different thicknesses of SiOx may be used other than 8 nm. The thickness may be optimized for the specific electric field, passivation protection, and/or alternating materials that are used to form the heterostructure. ALD was performed based on standard recipes using water and (x) precursors at 200 C., although it should be noted that other temperatures may be used. As an example, one method that may be used herein for producing defects is by ion implantation with .sup.12C and subsequent high temperature annealing with 900-1000 C. temperatures. Typical doses range from 10.sup.11-10.sup.13 ions/cm.sup.2 and energies greater than 20 keV. As an example, implantation may span these ranges as well as at 10 keV to attempt to position the vacancies closer to the surface of the SiC in order to have vacancies in regions of highest electric field. Table 1 below shows examples of ion-implantation for various wafers.
(37) TABLE-US-00001 TABLE 1 Wafer # Species Dose (cm.sup.2) Energy (keV) Samples 1 .sup.12C 10.sup.11 200 4H SiC, 6H SiC, Si 2 .sup.12C 10.sup.12 200 4H SiC, 6H SiC, Si 3 .sup.12C 10.sup.13 200 4H SiC, 6H SiC, Si 4 .sup.12C 10.sup.11 50 4H SiC, 6H SiC, Si 5 .sup.12C 10.sup.12 50 4H SiC, 6H SiC, Si 6 .sup.12C 10.sup.13 50 4H SiC, 6H SiC, Si 7 .sup.12C 10.sup.11 20 4H SiC, 6H SiC, Si 8 .sup.12C 10.sup.12 20 4H SiC, 6H SiC, Si 9 .sup.12C 10.sup.13 20 4H SiC, 6H SiC, Si 10 .sup.12C 10.sup.11 10 4H SiC, 6H SiC, Si 11 .sup.12C 10.sup.12 10 4H SiC, 6H SiC, Si 12 .sup.12C 10.sup.13 10 4H SiC, 6H SiC, Si
(38) The ion implantations were simulated to estimate the doping and damage profiles through the depth of the material. The estimations are shown in graphs 200, 300, and 400 shown in
(39) Thermal annealing was performed at 1000 C. for 30 minutes with a ULVAC MILA-3000 Mililamp annealer under low vacuum conditions. The thermal anneal is done to produce vacancies with a large percentage of vacancies that are suitable for use as qubits (i.e. silicon vacancies, and di-vacancies). However, other types of annealing, such as laser annealing, may be used. Following annealing, photolithography was performed to define lift-off regions for deposition of the electrodes. In one example, the mask contains field-effect device structures in a ground-signal-ground (G-S-G) configuration and with 150 m separation, as shown in the finished product in
(40) After sputtering, a first lift-off operation is performed in acetone with ultrasonic agitation. As used herein, the term lift-off refers to the process in semiconductor wafer manufacturing of creating patterns on the wafer surface through an additive process, as opposed to the more familiar patterning techniques that involve subtractive processes, such as etching.
(41) The process then involves depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes, as well as performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes. As used herein, the term optically transparent refers to transparency that permits both the excitation and emission of the desired wavelengths for the qubit operation. These two steps form a gate electrode directly above the qubit region in intimate contact with the SiOx passivation. A lift-off procedure may also be used following deposition of a transparent electrode, such as ITO.
(42) The output 600 is shown in
(43) As an example, scanning PL measurements were taken on both of the 4HSiC and 6HSiC samples at room temperature using an AIST-NT Confocal Raman/Atomic Force Microscopy (AFM) system with a laser excitation source of 785 nm, a Horiba iHR320 imaging spectrometer, and a Horiba Syncerity CCD camera thermoelectrically cooled to 50 C. with a Hamamatsu (S11510) near-IR image sensor. The samples measured include both non-implanted and .sup.12C implanted 4HSiC and 6HSiC with energies ranging from 20-50 keV and doses ranging from 10.sup.12-13. Measurements were also conducted on three different regions of the device to examine the effect of an ITO film on the excitation and transmission of SiC PL.
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(45) The blue and red spectra shown in
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(48) To confirm the effect of energy and dose in introducing defects in 6HSiC, the PL measurements were conducted on three samples. These samples included unprocessed 6HSiC, 6HSiC implanted at 20 keV with dose of 10.sup.12, and 6HSiC implanted at 50 keV with dose of 10.sup.13. The samples were measured using a 785 nm excitation at 100 mW. The average spectra were acquired with an acquisition time of is and 10 accumulations, and were normalized with respect to the 2.sup.nd TO peak of 6HSiC.
(49) To estimate the quantity of photon emitting defects within the excitation volume, the PL of an implanted 6HSiC sample (Energy: 50 keV; Dose: 10.sup.13) was measured at a series of laser powers.
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(51) Method 1600 may begin with step 1610, which involves depositing a layer of silicon oxide onto a layer of silicon carbide, such as 4H or 6H silicon carbide. Step 1620 involves ion implanting the layer of silicon carbide. As an example, step 1620 is performed using .sup.12C. In some embodiments, step 1620 is performed using an energy level between a range of about 20 keV to about 50 keV. Step 1630 involves annealing the ion implanted layer of silicon carbide to produce defects within the layer of silicon carbide. In some embodiments, step 1630 is performed at a temperature between a range of about 900 degrees Celsius to about 1000 degrees Celsius.
(52) Step 1640 involves performing photolithography using a mask layer on regions of the layer of silicon carbide to define regions for electrode deposition. Step 1650 involves removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition. In some embodiments, step 1650 is performed using a dilute H.sub.2O:HF etch. Step 1660 involves forming one or more electrodes by depositing indium tin oxide (ITO) in each of the regions for electrode deposition. As an example, step 1660 is performed by RF sputtering at 200 W in argon.
(53) Step 1670 involves performing a first lift-off operation to remove the mask layer surrounding the electrodes. In some embodiments, step 1670 is performed in acetone with ultrasonic agitation. Step 1680 involves depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes. In some embodiments, step 1680 is performed by atomic layer deposition. Step 1690 involves performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.
(54) Many modifications and variations of the embodiments disclosed herein are possible in light of the above description. Within the scope of the appended claims, the disclosed embodiments may be practiced otherwise than as specifically described. Further, the scope of the claims is not limited to the implementations and embodiments disclosed herein, but extends to other implementations and embodiments as may be contemplated by those having ordinary skill in the art.