Abstract
New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionization current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body/Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) implant into the device structure that increases the total device periphery without correspondingly scaling its device current.
Claims
1. A semiconductor electronic device comprising a Silicon-On-Insulator (SOI) substrate wherein a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is built; the MOSFET comprises: An active semiconductor layer on top of a buried dielectric with an insulating dielectric film separating a Gate electrode from a portion of the active semiconductor layer; the active semiconductor layer comprises: Two highly doped regions having a first conductivity type that form a Drain and a Source and extend laterally under the Gate electrode region from two opposing ends, a highly doped HALO pocket under the Gate electrode next to the Drain that has a second conductivity type opposite to the first conductivity type, a second highly doped pocket under the Gate electrode next to the Source that has second conductivity type and contacts the Source electrically through a layer of Silicide, and a region between both pockets that forms a central Body and has second conductivity type with a less doping level than both pockets;
2. The device of claim 1 wherein the buried insulating material comprises any of Sapphire, Aluminum-Nitride, Diamond, Silicon-Carbide or Silicon-Dioxide as a buried dielectric on top of which an active semiconductor layer lays;
3. The device of claim 1 or claim 2 wherein a highly doped pocket is in the active Silicon layer under a Gate electrode next to Source and has a different size and shape than a second highly doped HALO pocket having a same conductivity type in same Silicon under the Gate electrode next to Drain;
4. The device of claim 1 or claim 2 wherein a Drain region having a first conductivity type is next to a central Body that has a second conductivity type opposite to the first conductivity type and with less doping level and same second conductivity type than a higher doped pocket between same central Body and a Source that has the first conductivity type;
5. The device of claim 1, claim 2, claim 3 or claim 4 wherein a square or a rectangular trenched electrically conductive interconnect contacts the Silicide that electrically bonds a highly doped pocket under a Gate electrode to a Source region;
6. Any and all circuits that use the devices embodiments of claim 1, claim 2, claim 3, claim 4, or claim 5.
Description
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0009] FIG. 1a: Cross-section Cartoon of a new structure for SOI MOSFET showing the high doped Pocket and its shunt to the Source-diffusion region with Silicide. Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions (Since Gate dielectric is excessively ultra-thin any Metal that touches it diffuses and creates effective short(s) to Drain and/or Source). A barrier does exist between the Body under the Gate and the Source. This barrier can be lowered from an impact-ionization current causing a possible Bipolar latch-up unless this impact-ionization current gets diverted away from the barrier. The shortening of the highly doped pocket under the Gate to the Source through Silicide provides this diversion as this figure shows.
[0010] FIG. 1b: Similar device structure as that of FIG. 1a but in which the Silicide does not extend to encompass the entire lateral dimension of the highly doped pocket. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).
[0011] FIG. 2: Cross-section Cartoon of a new structure for SOI MOSFET in which the Silicide covers only a top portion of the Source and does not extend laterally into the highly doped Pocket. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).
[0012] FIG. 3: Cross-section Cartoon of a new structure for SOI MOSFET in which the Silicide covers only a top portion of the Source and extends slightly laterally into the highly doped Pocket. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).
[0013] FIG. 4: Same device structure as that of FIG. 1a but in which a trenched conducting material (e. g. Copper Metals) contact the back Silicide in Source region. (Conducting interconnects also contact the opposing side of same Silicide and the Silicide in Drain region to form the Contacts for inline-interconnects are not shown in this figure). (Also not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).
[0014] FIG. 5: Same device structure as that of FIG. 1b but in which raised Silicide is formed on the back Silicon. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).
[0015] FIG. 6: A generalized figure summarizing the different steps that are required for the formation of high electrically conducting Silicide.
DETAILED DESCRIPTION OF THE INVENTION
[0016] The new device architecture for SOI MOSFET traps the impact-ionization current in a band-engineered highly doped Pocket that extends in the active Silicon underneath the Gate along the entire device Width and routes this impact-ionization current to the Source-diffusion region through a highly electrically conductive path that contains a Silicide formation that solders this Pocket to the Source. This prevents the impact-ionization current from diffusing through the lateral Body-to-Source barrier and lowering it further. The Silicide in Source region can either consume the entire thickness of active Silicon or only the top portion of it. It may also extend laterally into the highly doped Pocket under the Gate. Square or trenched interconnects may also contact the Silicide to further increase the electric conductance between the device Body under the Gate and the Source. The lightly-doped Drain region helps to suppress the injection of Hot-electrons into the Gate. (Lightly doped region(s) may be omitted and replaced with same dopant concentration as in rest of Source and Drain). The FIG. 1a, FIG. 1b, FIG. 2, FIG. 3, FIG. 4 and FIG. 5 illustrate some possible different embodiments for this new device architecture.
[0017] Raised Silicide designs relative to either both sides of the active Silicon in Source region or to only a one side of this active Silicon can be used and may even be essential when this active Silicon is ultra-thinned (7 nm-35 nm). This prevents the Silicide from diffusing closer underneath the Gate and deteriorating the Gate channel.
[0018] Whereas the simpler device structure of FIG. 2 can follow a similar fabrication process to what the today's standard CMOS processes follow provided that some necessary process ramifications are made such to enable the Silicide to form deep into the Silicon and wires to the highly doped Pocket, a more effective wiring of this highly doped pocket to the Source requires more complex processes. In the former process carefully controlled angled Germanium Pre-Amorphousiation Implant (GPI) can be performed after the formation of the Spacer to regulate the depth and the lateral penetration of the Silicide prior to depositing the Metal and the annealing to form Silicide. GPI proved to enable the formation of better Silicide, enables better control for the depth and lateral penetration of Silicide, and prevents or suppresses any metallic pipes from diffusing deeper into the Silicon film closer to the conducting device channel. In the latter process an etch-Stop-Layer (ESL) through the surface of a seed Wafer (that is the Wafer that is to be bounded to a Handle Wafer) is implanted first. This can be followed with the growth of thick epitaxy atop this seed Wafer surface. This epitaxy is the active Silicon film of the MOS device (which can be as ultra-thin as 7-35 nm). Another approach is not to use epitaxy; Carbon is implanted as ESL through the surface of seed Wafer and the portion of Silicon on top of this ESL becomes the active Silicon of the MOS device. Carbon is electrically-inactive in Silicon and when implanted at temperatures close to 500 degC. Crystal damage is lowered or minimized. Other electrically-inactive species (e.g. Nitrogen) can also be implanted instead of Carbon. The surface of the seed Wafer is then thoroughly cleanedThe device Frontend regions are then patterned and implanted and the formation of Silicide that wires the highly doped Pocket to Source can then be accomplished through either one of two separate approaches: [0019] 1The Body, Source and Drain diffusion regions are implanted first and the highly doped Pocked is formed (this can either be through patterning it and then implanting it, and/or through using angled implants on deposited Photoresist). The surface is then polished with Chemical-Mechanical Polish (CMP), cleaned and the Silicide that solders this highly doped pocket to the Source is processed. [0020] 2The center Body is implanted first. This is followed with growth of high quality Silicon or Silicon-Germanium Epitaxy atop the two lateral side edges of the Silicon. This Epitaxy is then implanted to form the Drain, Source and Pocket regions over which the Silicide is formed next. (This epitaxy may also be grown to form the Source and Pocket regions only atop which the Silicide is formed while the Drain region lays exclusively in the bulk Silicon).
[0021] Trenched or rectangular electrically conductive interconnect (e. g. Tungsten, Copper, etc. . . . ) can also contact this Silicide that wires the highly doped Pocket to Source as FIG. 4 shows. Inline dielectric is finally formed or deposited. This Inline dielectric can be thin enough just to enable an effective dielectric-to-dielectric bonding of this seed Wafer to a Handle Wafer. Tough refractory metals that form Silicide stable at high temperatures (900-1000 DegC.) can be used in the formation of this back-Silicide. This is because of the much high temperatures that are necessary and required in the continuation of this fabrication process. This Silicide must be stable and capable to withstand the upcoming heat cycles (e.g. the thermal growth of the Gate dielectric, Source/Drain annealing, etc. . . . ). Examples can be: TiSi.sub.2(C.sub.54), TaSi.sub.2, MoSi.sub.2, WSi.sub.2, CoSi.sub.2. A technique that boosts the thermal stability of Nickel-Silicide at higher temperatures (700-1000 DegC.) may even allow the use of Nickel-Silicide to wire this highly doped pocket to the Source. This requires the deposition of thin Aluminum film (typically 3-5 nm thick) onto the Silicon prior to depositing the Nickel and applying the required heat-cycles to form this Nickel-Silicide. This approach was described and demonstrated in the work of Takashi Shiozawa, Improvement of Thermal Stability of Ni Silicide on Heavily Doped N+-Si, Iwai Laboratory, Department of Electronics and Applied Physics, pp. 41-59, 2007. Because the deposited Inline dielectric into the surface of the seed Wafer can outgas and creates voids upon being subjected to high temperatures after bonding this seed Wafer to the surface dielectric of a Handle Wafer, this Silicided Seed Wafer undergoes prior to this bonding a high temperature anneal that outgases any by-products or gas molecules that were absorbed during the deposition of this Inline dielectric. This pre-bond anneal is typically anywhere between 800 DegC. and 1200 DegC. but may be lower. CMP is followed next and the Seed and Handle Wafers are then bonded together through their surface dielectrics. A post-bond anneal is then performed to strengthen this bond and the two Wafers become one Wafer. The back Silicon of the seed Wafer is then polished. Typically grinding is performed first to thin this back Silicon down to 30-50 m. This grinding can be highly time-efficient in the high-volume manufacturing due to its highest thinning rate. It is a two-step process that includes a coarse grinding (at 5 m/s) and a subsequent fine grinding (at 1 m/s). This second step is necessary to remove most of the damage layer created by the coarse grinding step and to reduce surface roughness. Additional thinning processes are performed next to further thin down this back Silicon down to 100-200 nm prior to utilizing MagnetoRheological Finishing (MRF) and/or Plasma Chemical Vaporization Machining (PCVM) for an exact precise thinning of the Silicon film and for minimizing its surface roughness. These additional thinning processes prior to MRF and/or PCVM can include combinations of dry/wet etching and CMP to substantially further reduce the thickness of this back Silicon. The purpose of the ESL that was implanted into the Seed Wafer at the very beginning is to impede the etch-rate from these dry/wet etch prior to a precision thinning of the Wafer with MRF and/or PCVM. The ESL layer may also be implanted through the back Silicon instead when this back Silicon becomes sufficiently thinned, or it may even be omitted all together when a very precise control of the polish steps can be undertaken with a precise use of MRF and/or PCVM). The FIG. 6 shows or illustrates the main processing steps that are involved in this fabrication process. After the active Silicon film is thinned to its targeted/desired thinness through following the steps described above, devices are then fabricated in following the processes that are same or similar to the today's standard processes for fabricating CMOS. The stronger and thermally-stable back Silicide can be capable to withstand the elevated 800-1100 C. temperatures that are typically required in processing the Frontend. The Gate dielectric can be thermally grown at temperatures lower than 700-900 C., and the Source-Drain-Annealing (SDAL) temperatures can be slightly lowered to below 900-1000 C. given the much thin volume of the active Silicon compared to that of CMOS devices fabricated on bulk Silicon.
