Method for Forming a PN Junction and Associated Semiconductor Device

Abstract

An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.

Claims

1. An integrated circuit comprising: a semiconductor substrate; an insulating layer overlying the semiconductor substrate; a semiconductor layer of a first conductivity type overlying the insulating layer; a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer; and a sequence of PN junctions in the semiconductor layer, each PN junction located at an edge of an associated projecting region and vertically extending from an upper surface of the semiconductor layer to the insulating layer.

2. The integrated circuit according to claim 1, wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer, the disconnected strips being parallel to each other.

3. The integrated circuit according to claim 1, wherein the sequence of PN junctions forms a plurality of diodes, each diode including a heavily doped region of the first conductivity type that abuts a lightly doped region of the first conductivity type that abuts a doped region of a second conductivity type.

4. The integrated circuit according to claim 3, wherein some of the diodes form a current bridge rectifier.

5. The integrated circuit according to claim 4, wherein the current bridge rectifier comprises a Graetz bridge.

6. The integrated circuit according to claim 1, wherein the sequence of PN junctions comprises first areas of a second conductivity type overdoped relative to other portions of the semiconductor layer, and second areas of the first conductivity type overdoped relative to the other portions of the semiconductor layer, a first area lying between two second areas and separated from these two second areas by two interleaved regions of the semiconductor layer located, respectively, under two neighboring projecting regions, each junction between a first area and an interleaved region forming a diode, wherein the first areas comprise P+ doped areas that form anodes of the diodes, and wherein the second areas comprise N+ doped areas that, together with the interleaved regions, form cathodes of the diodes.

7. The integrated circuit according to claim 1, wherein the semiconductor layer is a polysilicon layer.

8. The integrated circuit according to claim 1, wherein each of the plurality of projecting regions comprises a layer of dielectric and a gate material overlying the layer of dielectric.

9. The integrated circuit according to claim 1, further comprising floating gate transistors laterally spaced from the sequence of PN junctions, each floating gate transistor comprising a floating gate and a control gate, wherein the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the plurality of projecting regions is located at the same level as the control gates of the floating gate transistors.

10. An integrated circuit comprising: a semiconductor substrate; an insulating layer overlying the semiconductor substrate; a semiconductor layer overlying the insulating layer; a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer; a plurality of interleaved regions disposed within the semiconductor layer, each interleaved region being located beneath an associated projecting region and being lightly doped with dopants of a first conductivity type; a plurality of first areas disposed within the semiconductor layer, each first area abutting an associated interleaved region at a location near a first edge of the associated projecting region, each first area being heavily doped with dopants of the first conductivity type and extending from an upper surface of the semiconductor layer to the insulating layer; and a plurality of second areas disposed within the semiconductor layer, each second area abutting an associated interleaved region at a location near a second edge of the associated projecting region, each second area being heavily doped with dopants of a second conductivity type and extending from the upper surface of the semiconductor layer to the insulating layer.

11. The integrated circuit according to claim 10, wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer, the disconnected strips being parallel to each other.

12. The integrated circuit according to claim 10, wherein the interleaved regions, the plurality of first areas, and the plurality of second areas form diodes that are connected to form a current bridge rectifier.

13. The integrated circuit according to claim 10, further comprising floating gate transistors laterally spaced from the plurality of projecting regions, each floating gate transistor comprising a floating gate and a control gate, wherein the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the plurality of projecting regions are located at the same level as the control gates of the floating gate transistors.

14. The integrated circuit according to claim 10, wherein the semiconductor layer is a polysilicon layer.

15. The integrated circuit according to claim 10, wherein each of the plurality of projecting regions comprises a layer of dielectric and a gate material overlying the layer of dielectric.

16. An integrated circuit comprising: a semiconductor substrate; an insulating layer overlying the semiconductor substrate; a first semiconductor region having a first conductivity type overlying the insulating layer, wherein the first semiconductor region has a first doping concentration; a second semiconductor region having the first conductivity type overlying the insulating layer, the second semiconductor region abutting the first semiconductor region, wherein the second semiconductor region has a second doping concentration that is less than the first doping concentration; a third semiconductor region having a second conductivity type overlying the insulating layer, the third semiconductor region abutting the second semiconductor region, wherein the second conductivity type is opposite the first conductivity type; a first PN junction at a first interface between the third semiconductor region and the second semiconductor region; a first conductive material overlying and electrically contacting the first semiconductor region; a second conductive material overlying and electrically insulated from the second semiconductor region; and a third conductive material overlying and electrically contacting the third semiconductor region.

17. The integrated circuit according to claim 16, wherein the first conductive material and the third conductive material each comprise a metallic material.

18. The integrated circuit according to claim 16, wherein the second conductive material comprises polysilicon.

19. The integrated circuit according to claim 16, further comprising: a fourth semiconductor region having the first conductivity type overlying the insulating layer, the fourth semiconductor region abutting the third semiconductor region, wherein the fourth semiconductor region has a third doping concentration substantially equal to the second doping concentration; and a second PN junction at a second interface between the fourth semiconductor region and the third semiconductor region.

20. The integrated circuit according to claim 19, further comprising: a fourth conductive material overlying and electrically insulated from the fourth semiconductor region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other advantages and characteristics of the invention will be apparent from a perusal of modes of construction and embodiment of the invention, which are not limiting in any way, and the appended drawings, in which:

[0035] FIG. 1, described above, shows a conventional electronic circuit comprising a diode bridge,

[0036] FIG. 2 shows a sectional view of a mode of construction of an integrated circuit according to the invention, and

[0037] FIG. 3 shows an embodiment of a method according to the invention, and corresponds to a top view of the section of FIG. 2.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0038] FIG. 2 is a sectional view of an integrated circuit comprising three diodes D.sub.1, D.sub.2, D.sub.3 formed on a semiconductor substrate 1. The semiconductor substrate 1 may be, with reference to FIG. 1, the substrate PSUB itself or a box structure formed in the substrate, for example the box structure N-ISO, again with reference to FIG. 1.

[0039] Different manufacturing steps of a method for producing this structure will now be described with reference to FIGS. 2 and 3.

[0040] An insulating layer 3 has been formed on the surface of the substrate 1, for example, by a method similar to a conventional known method for forming a shallow insulating trench.

[0041] A first semiconductor layer 5, for example a layer of polysilicon doped with a first type of conductivity, of the N-type for example, is then formed on the insulating layer 3.

[0042] In a customary method for manufacturing non-volatile memories, this step can be executed jointly with a step of forming polysilicon floating gates of floating-gate transistors.

[0043] In the customary method for manufacturing non-volatile memories, control gates of the floating-gate transistors are then formed, usually comprising a layer of dielectric surmounted by a layer of polysilicon. The control gates are, for example, formed in strips extending in a direction orthogonal to the section plane of FIG. 2.

[0044] The control gates may also be formed from any other gate material, such as a metal.

[0045] Additionally, structures known as dummies are commonly added to the functional structures, notably in order to avoid breaks in periodicity which are harmful in some steps of the manufacture of integrated circuits, but they do not usually have any supplementary function.

[0046] In the method of forming the diodes D.sub.1, D.sub.2, D.sub.3, a layer of dielectric 7 surmounted by a layer of polysilicon 9 is formed on the surface of the first polysilicon layer 5, forming projecting regions CGf on the surface of the first polysilicon layer.

[0047] The projecting regions CGf may advantageously be dummy control gates specified in the context of a method of manufacturing floating-gate transistors.

[0048] In this embodiment, the projecting regions CGf are used as a hard mask for forming implantations of dopants in the first polysilicon layer 5.

[0049] As illustrated in FIG. 3, the projecting regions CGf are arranged here in strips extending in a direction orthogonal to the section plane of FIG. 2, represented by the line II-II.

[0050] An implantation of dopants having the second type of conductivity (P+) is carried out along first implantation surfaces 10 so as to form first areas 11-11 which are overdoped relative to the doping of the first polysilicon layer 5, for example by having a concentration which is higher by a factor of 100.

[0051] The implantation surfaces 10 cover the parts of the first polysilicon layer 5 located between two projecting regions CGf, and may overflow on to a portion of the strips of projecting regions CGf.

[0052] This is because, even if the implantation surfaces 10 are poorly aligned relative to a specified implantation surface (that is to say, the polysilicon surface 5 between two projecting regions CGf), the first resulting implanted areas 11-11 will be delimited precisely and regularly by the edges bCGf of the projecting regions CGf.

[0053] Consequently, the implantation requires no supplementary critical masking step, particularly in a method including the forming of floating-gate transistors.

[0054] This permits a good degree of control of the implantation surfaces, and consequently the lateral distribution of the dopants in the polysilicon layer 5.

[0055] The regions of the first polysilicon layer 5 located under the projecting regions CGf are therefore not implanted, and form regions 12 called interleaved regions.

[0056] On the other hand, the thickness of the first polysilicon layer 5 and the depth of implantation of the dopants are advantageously designed to be such that the implantation 10 is diffused throughout the thickness of the first polysilicon layer 5, as far as the insulating layer 3.

[0057] As a result of the diffusion, the first areas 11-11 comprise a very strongly doped region 11 close to the surface and a deeper less strongly doped region 11, reaching the insulating layer 3.

[0058] Thus PN junctions between the first areas 11-11 and the interleaved regions 12 extend to the insulating layer 3 and are located on the edges of the projecting regions bCGf in the first polysilicon layer 5.

[0059] Since the dopant implantations are not isotropic, the term edges of the projecting regions signifies a region adjacent, or close, to the geometric projection of the contour of the projecting regions in the first polysilicon layer 5.

[0060] Implantations of dopants having the first type of conductivity (N+) are carried out in a corresponding manner along second implantation surfaces 13 so as to form second areas 14-14 which are overdoped relative to the doping of the first polysilicon layer 5.

[0061] The implantation surfaces 13 cover the parts of the first polysilicon layer 5 located between the edges bCGf of two projecting regions CGf, and may also overflow on to a portion of the projecting regions CGf.

[0062] Similarly, the thickness of the first polysilicon layer 5 and the depth of implantation of the dopants are advantageously designed to be such that the implantation is diffused throughout the thickness of the second polysilicon layer 5, forming a very strongly doped region 14 and a less strongly doped region 14 reaching the insulating layer 3.

[0063] In this mode of construction and embodiment, one region out of every two regions located between two strips of projecting regions CGf is doped with the first type of conductivity, while the other is doped with the second type of conductivity.

[0064] The first areas 11-11 form, with the interleaved regions 12 of the first polycrystalline silicon layer 5, PN junctions extending to the insulating layer 3.

[0065] Thus the first areas 11-11 form anode regions and the second areas 14-14 form, with the interleaved regions 12, cathode regions of diodes D.sub.1, D.sub.2, D.sub.3 constructed in this way.

[0066] It is then possible to form, in a conventional manner, spacers 15 of a dielectric material placed on the sides of the projecting regions (or dummy control gates) CGf, and contact terminals for the cathodes 17 and anodes 19, for example by siliciding the surfaces of the anode and cathode regions which are not covered by the spacers 15 or the projecting regions CGf, on which metallic cathode contacts 21 and anode contacts 23 are respectively formed.

[0067] Thus diodes D.sub.1, D.sub.2, D.sub.3 are produced, formed by a PN junction extending to the insulating layer 3, between an anode formed by a first overdoped area 11-11 and a cathode formed by a second overdoped area 14-14 and an interleaved region 12.

[0068] The diodes D.sub.1, D.sub.2, D.sub.3 are therefore completely insulated from the semiconductor substrate 1.

[0069] Additionally, in this embodiment, at least one cathode region 14-14 is common to two different diodes, for example the diodes D.sub.1 and D.sub.2, and lies between two respective anode regions 11-11. Also, at least one anode region 11-11 is common to two different diodes, for example the diodes D.sub.2 and D.sub.3, and lies between two respective cathode regions 14-14.

[0070] This configuration with common electrodes is particularly advantageous for the construction of a diode bridge of the Graetz bridge type, having an anode node common to two diodes and a cathode node common to two diodes.

[0071] Furthermore, the invention is not limited to the present description, but embraces all variants thereof.

[0072] For example, it is feasible for the second implantation 13 to be an implantation of dopants having the second type of conductivity, in a similar manner to the first implantation 10, forming a series of diodes head to tail between the implanted areas and the interleaved areas, the various cathodes being electrically connectable via contacts extending in a plane other than the planes of the attached figures.