Near field communication devices, systems, and methods using Q factor adjustments

Abstract

An NFC (near field communication) device can include a resonance unit and an NFC chip. The resonance unit may communicate with an external device through an electromagnetic wave. The NFC chip can provide output data to the resonance unit, receive input data from the resonance unit, and can reduce a Q factor (quality factor) of the resonance unit when a signal receive operation is performed in a card mode, and can maintain the Q factor of the resonance unit in a reader mode and when a signal transmit operation is performed in the card mode.

Claims

1. A Near Field Communication (NFC) chip comprising: a central processing unit (CPU) configured to generate a mode signal that represents a card mode or a reader mode; and a transmit circuit configured to determine a quality factor (Q factor) based on the mode signal, wherein the mode signal represents a signal receive operation or a signal transmit operation when the mode signal represents the card mode.

2. The NFC chip of claim 1, wherein the transmit circuit connects between a supply voltage and a ground voltage, and includes at least one transistor.

3. The NFC chip of claim 2, wherein the transmit circuit comprises a driving circuit configured to drive the at least one transistor based on the mode signal.

4. The NFC chip of claim 1, wherein the transmit circuit connects a transmit terminal to a supply voltage through a pull-up load, or connects the transmit terminal to a ground voltage through a pull-down load, based on output data in the reader mode, and the transmit circuit connects the transmit terminal to the ground voltage through the pull-down load when the signal receive operation is performed in the card mode, or cuts off the transmit terminal from the ground voltage and the supply voltage when the signal transmit operation is performed in the card mode.

5. The NFC chip of claim 4, further comprising: a driving circuit configured to selectively turn on one of a pull-up transistor and a pull-down transistor based on the output data in the reader mode, to turn off the pull-up transistor while turning on the pull-down transistor when the signal receive operation is performed in the card mode, and to turn off the pull-up transistor and the pull-down transistor when the signal transmit operation is performed in the card mode.

6. The NFC chip of claim 1, wherein the transmit circuit comprises: a pull-up transistor connected between a supply voltage and a transmit terminal; a pull-down transistor connected between a ground voltage and the transmit terminal; and a driving circuit configured to selectively turn on one of the pull-up transistor and the pull-down transistor based on output data and the mode signal.

7. The NFC chip of claim 1, wherein the transmit circuit comprises: first to nth pull-up transistors connected in parallel between a supply voltage and a transmit terminal; first to nth pull-down transistors connected in parallel between a ground voltage and the transmit terminal; and a driving circuit configured to turn on the first to nth pull-up transistors or the first to nth pull-down transistors based on output data in the reader mode, configured to turn off the first to nth pull-up transistors and sequentially turn on the first to nth pull-down transistors during a first time interval when the signal receive operation is performed in the card mode, and configured to turn off the first to nth pull-up transistors and sequentially turn off the first to nth pull-down transistors during the first time interval when the signal transmit operation is performed in the card mode.

8. The NFC chip of claim 1, further comprising: a field detector configured to measure a voltage supplied from a resonance circuit to generate a field intensity signal corresponding to a magnitude of the voltage in the card mode, wherein the transmit circuit controls a reduction degree of the Q factor based on the field intensity signal when the signal receive operation is performed in the card mode.

9. The NFC chip of claim 1 wherein the mode signal is configured to represent the card mode or the read mode at a first time and the mode signal is configured to represent the signal receive operation or the signal transmit operation at a second time.

10. The NFC chip of claim 1 wherein the card mode or the read mode and the signal receive operation or the signal transmit operation are time multiplexed onto the mode signal at different times.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

(2) FIG. 1 is a block diagram illustrating an NFC (near field communication) device according to an example embodiment.

(3) FIG. 2 is a graph to explain the operation of the NFC device of FIG. 1.

(4) FIG. 3 is a block diagram illustrating an example of the NFC device of FIG. 1.

(5) FIG. 4 is a block diagram illustrating an example of a Q sink unit included in the NFC device of FIG. 3.

(6) FIG. 5 is a diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 4.

(7) FIG. 6 is a diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 4.

(8) FIG. 7 is a block diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 4.

(9) FIG. 8 is a block diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 4.

(10) FIG. 9 is a view to explain the operation of a slew control unit included in the pull-down unit of FIGS. 7 and 8.

(11) FIG. 10 is a block diagram illustrating an example of the NFC device of FIG. 1.

(12) FIG. 11 is a block diagram illustrating an example of a Q sink unit included in the NFC device of FIG. 10.

(13) FIG. 12 is a diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 11.

(14) FIG. 13 is a diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 11.

(15) FIG. 14 is a block diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 11.

(16) FIG. 15 is a block diagram illustrating an example of a pull-down unit included in the Q sink unit of FIG. 11.

(17) FIG. 16 is a view to explain the operation of the NFC devices of FIGS. 3 and 10.

(18) FIGS. 17A and 17B are views to explain the effects of the NFC devices of FIGS. 3 and 10.

(19) FIG. 18 is a block diagram illustrating an example of the NFC device of FIG. 1.

(20) FIG. 19 is a block diagram illustrating an example of a transmit unit included in the NFC device of FIG. 18.

(21) FIG. 20 is a block diagram illustrating an example of a transmit unit included in the NFC device of FIG. 18.

(22) FIG. 21 is a view to explain the operation of a driving unit included in the transmit unit of FIG. 20.

(23) FIG. 22 is a block diagram illustrating an example of the NFC device of FIG. 1.

(24) FIG. 23 is a block diagram illustrating an example of a transmit unit included in the NFC device of FIG. 22.

(25) FIG. 24 is a view to explain the operation of a driving unit included in the transmit unit of FIG. 23.

(26) FIG. 25 is a block diagram illustrating an electronic system according to example embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS ACCORDING TO THE INVENTIVE CONCEPT

(27) Various example embodiments will be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. The present inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout this application.

(28) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present inventive concept. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

(29) It will be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., between versus directly between, adjacent versus directly adjacent, etc.).

(30) The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventive concept. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes and/or including, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(31) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(32) FIG. 1 is a block diagram illustrating an NFC (near field communication) device according to an example embodiment.

(33) The NFC device 10 illustrated in FIG. 1 makes communication with an external device through an NFC scheme. The NFC device 10 makes data communication with an external reader based on an electromagnetic wave (EMW) supplied from the external reader in a card mode, where the NFC device 10 serves as a card and makes data communication with an external card based on the EMW generated from the NFC device 10 in a reader mode where the NFC device 10 serves as a reader.

(34) Referring to FIG. 1, the NFC device 10 includes a resonance unit 100 and an NFC chip 200.

(35) Upon the signal receive operation, the resonance unit 100 receives input data from the external device through the EMW and the NFC chip 200 receives the input data from the resonance unit 100. Upon the signal transmit operation, the NFC chip 200 provides output data to the resonance unit 100 and the resonance unit 100 transmits the output data to the external device through the EMW.

(36) The resonance unit 100 may include a resonance circuit including an antenna having an inductance component and a resonance capacitor.

(37) In the card mode, the resonance unit 100 provides a signal, which is induced in response to the EMW received from the external device, to the NFC chip 200 and the NFC chip 200 performs the signal receive operation by generating the input data by demodulating the signal. In the card mode for a signal transmit operation, the NFC chip 200 provides a modulation signal, which is generated by modulating the output data, to the resonance unit 100 and the resonance unit 100 may perform the signal transmit operation by reflecting the EMW received from the external device based on the modulation signal.

(38) In the reader mode, the NFC chip 200 can provide a transmit signal as part of a signal transmit operation, which is obtained by synthesizing the modulation signal generated by modulating the output data with a carrier signal, to the resonance unit 100 and the resonance unit 100 provides the transmit signal in the form of the EMW to the external device to perform the signal transmit operation. In the reader mode, the NFC chip 200 can provide a signal as part of a signal receive operation, which is induced in response to the EMW reflected from the external device, and the NFC chip 200 generates the input data by demodulating the signal to perform the signal receive operation.

(39) The NFC chip 200 reduces the Q factor (quality factor) of the resonance unit 100 when the signal receive operation is performed in the card mode and maintains the Q factor in the reader mode and when the signal transmit operation is performed in the card mode.

(40) For instance, the NFC chip 200 may reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode by connecting a terminal connected to the resonance unit 100 to a ground voltage GND through a pull-down load. In addition, the NFC chip 200 may maintain the Q factor in the reader mode and when the signal transmit operation is performed in the card mode by cutting off the terminal connected to the resonance unit 100 from the ground voltage GND.

(41) FIG. 2 is a graph to explain the operation of the NFC device of FIG. 1.

(42) In FIG. 2, a first graph A represents the frequency characteristic of the resonance unit 100.

(43) Referring to FIG. 2, the resonance unit 100 may have the longitudinal frequency characteristic having the center on the carrier frequency fc. The resonance unit 100 may have the maximum gain MAX1 at the carrier frequency fc and may have a first bandwidth BW1 where a first frequency f1 and a second frequency f2 serve as cutoff frequencies. The Q factor of the resonance unit 100 may have a value obtained by dividing the carrier frequency fc by the first bandwidth BW1.

(44) Since the NFC chip 200 maintains the Q factor of the resonance unit 100 in the reader mode and when the signal transmit operation is performed in the card mode, the resonance unit 100 may have the frequency characteristic as shown in the first graph A in the reader mode and when the signal transmit operation is performed in the card mode.

(45) As appreciated by the present inventors, if the frequency characteristic of the resonance unit 100 is not changed when the signal receive operation is performed in the card mode, as shown in FIG. 2, a high-speed signal having the high frequency fu equal to or higher than the second frequency f2 (for instance, the high frequency of 848 Kbps or more) is filtered by the resonance unit 100, so the NFC chip 200 may not normally demodulate the input data provided from the external device. Thus, the NFC device 100 may not perform the high-speed communication.

(46) The bandwidth BW1 of the resonance unit 100 is reduced as the size of the antenna included in the resonance unit 100 becomes reduced and the intensity of the EMW received from the external device becomes weak, so the available communication speed of the NFC device 10 may be further limited.

(47) However, as described above, the NFC chip 200 included in the NFC device 10 can reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode. For instance, the NFC chip 200 reduces the gain of the resonance unit 100 by connecting the terminal connected to the resonance unit 100 to the ground voltage GND through the pull-down load when the signal receive operation is performed in the card mode, so the resonance unit 100 may have the frequency characteristic as shown in a second graph B of FIG. 2. At this time, the resonance unit 100 may have the maximum gain MAX2 at the carrier frequency fc and may have a second bandwidth BW2 where a third frequency f3 and a fourth frequency f4 serve as cutoff frequencies. Since the Q factor of the resonance unit 100 may have a value obtained by dividing the carrier frequency fc by the second bandwidth BW2, the Q factor of the resonance unit 100 is reduced.

(48) In this case, as shown in FIG. 2, even when the resonance unit 100 receives the high-speed signal having the high frequency fu equal to or higher than the second frequency f2 (for instance, the high frequency of 848 Kbps or more), the high-speed signal can be normally received without being filtered. Thus, the available communication speed of the NFC device 10 may be increased.

(49) Meanwhile, since the load modulation characteristic is lowered as the gain of the resonance unit 100 is reduced in the signal transmit operation, as described above, the NFC chip 200 cuts off the terminal connected to the resonance unit 100 from the ground voltage GND when the signal transmit operation is performed, so that the Q factor of the resonance unit 100 can be maintained.

(50) In one example embodiment, the NFC chip 200 may measure a voltage supplied from the resonance unit 100 through the terminal connected to the resonance unit 100 when the signal receive operation is performed in the card mode in order to control the reduction degree of the Q factor of the resonance unit 100 based on the magnitude of the measured voltage. For instance, if the voltage supplied from the resonance unit 100 has a relatively great magnitude (that is, when operated in a near field), the Q factor of the resonance unit 100 is relatively small. In addition, if the voltage supplied from the resonance unit 100 has a relatively small magnitude (that is, when operated in a far field), the Q factor of the resonance unit 100 is relatively great. Therefore, the NFC chip 200 may increase the reduction degree of the Q factor of the resonance unit 100 as the voltage supplied from the resonance unit 100 is small when the signal receive operation is performed in the card mode.

(51) FIG. 3 is a block diagram illustrating an example of the NFC device of FIG. 1.

(52) Only elements to operate the NFC device 10a in the card mode are illustrated in FIG. 3 and elements to operate the NFC device 10a in the reader mode are omitted in FIG. 3

(53) Referring to FIG. 3, the NFC device 10a may include a resonance unit 100 and an NFC chip 200a.

(54) The NFC chip 200a may be connected to the resonance unit 100 through a first power terminal L1 and a second power terminal L2.

(55) The resonance unit 100 may include a resonance circuit having an antenna L and a first capacitor C1 and a filter having a second capacitor C2 to provide an induction voltage induced in response to the EMW to the first power terminal L1 and the second power terminal L2 and a third capacitor C3. The resonance unit 100 may supply the induction voltage induced in response to the EMW to the NFC chip 200a as a first voltage V1 through the filter.

(56) The configuration of the resonance unit 100 illustrated in FIG. 3 is an example only and the configuration of the resonance unit 100 according to example embodiments may not be limited to the above, but may be variously modified.

(57) The NFC chip 200a may receive the first voltage V1 from the resonance unit 100 through the first power terminal L1 and the second power terminal L2.

(58) The NFC chip 200a may include a rectifier 210, a regulator 220, a Q sink unit 230, a central processing unit (CPU) 240, a power switch PSW, a memory 250, a demodulator 251 and a modulator 253.

(59) The rectifier 210 can generate a second voltage V2 by rectifying the first voltage V1.

(60) The regulator 220 can generate an internal voltage Vint having a voltage level of a predetermined magnitude usable in the NFC chip 200a by using the second voltage V2 and can provide the internal voltage Vint to a first node N1.

(61) The CPU 240 can control the overall operation of the NFC chip 200a. The CPU 240 may operate by receiving a supply voltage VDD from a power source, such as a battery. In addition, the CPU 240 may receive the internal voltage Vint through the power switch PSW. When the supply voltage VDD has a predetermined level or more, the CPU 240 may operate by using the supply voltage VDD and disable a power control signal PCS to turn off the power switch PSW. Meanwhile, when the supply voltage VDD has a level less than the predetermined level, the CPU 240 enables the power control signal PCS to turn on the power switch PSW such that the CPU 240 can be operated by using the internal voltage Vint supplied from the regulator 220.

(62) When the signal receive operation is performed in the card mode, the demodulator 251 generates the input data by demodulating the signal supplied from the resonance unit 100 through the first and second power terminals L1 and L2 to provide the input data to the CPU 240. The CPU 240 may store the input data in the memory 250.

(63) When the signal transmit operation is performed in the card mode, the CPU 240 reads out the output data from the memory 250 to provide the output data to the modulator 253 and the modulator 253 may modulate the output data to provide a modulation signal to the first and second power terminals L1 and L2. For instance, the modulator 253 can generate the modulation signal by performing load modulation with respect to the output data.

(64) The Q sink unit 230 may be connected between the first node N1 and the ground voltage GND. The Q sink unit 230 is turned on when the signal receive operation is performed in the card mode to reduce the Q factor of the resonance unit 100 and turned off in the reader mode and when the signal transmit operation is performed in the card mode to maintain the Q factor of the resonance unit 100.

(65) In one example embodiment, the CPU 240 provides a mode signal MD, which represents the card mode or the reader mode and the signal receive operation or the signal transmit operation, to the Q sink unit 230, whereupon the Q sink unit 230 may selectively reduce the Q factor of the resonance unit 100 based on the mode signal MD.

(66) FIG. 4 is a block diagram illustrating an example of the Q sink unit included in the NFC device of FIG. 3.

(67) Referring to FIG. 4, the Q sink unit 230 may include a pull-down unit 231 and a Q sink controller 233.

(68) The Q sink controller 233 may generate a Q sink signal QSS which is enabled when the signal receive operation is performed in the card mode and is disabled in the reader mode and when the signal transmit operation is performed in the card mode. For instance, the Q sink controller 233 may generate the Q sink signal QSS based on the mode signal MD received from the CPU 240.

(69) The pull-down unit 231 may connect the first node N1 to the ground voltage GND through the pull-down load when the Q sink signal QSS is enabled and cut off the first node N1 from the ground voltage GND when the Q sink signal QSS is disabled.

(70) FIG. 5 is a diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 4.

(71) Referring to FIG. 5, the pull-down unit 231a may include a switch SW and a current source Io.

(72) The switch SW may be connected between the first node N1 and the current source Io and the current source Io may be connected between the switch SW and the ground voltage GND. Otherwise, the current source Io may be connected between the first node N1 and the switch SW and the switch SW may be connected between the current source Io and the ground voltage GND.

(73) The switch SW may be turned on when the Q sink signal QSS is enabled and turned off when the Q sink signal QSS is disabled.

(74) The current source Io may generate a current having a constant magnitude.

(75) As illustrated in FIG. 5, the pull-down unit 231a may selectively reduce the Q factor of the resonance unit 100 by connecting a current load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(76) FIG. 6 is a diagram illustrating another example of the pull-down unit included in the Q sink unit of FIG. 4.

(77) Referring to FIG. 6, the pull-down unit 231b may include a switch SW and a resistor Ro.

(78) The switch SW may be connected between the first node N1 and the resistor Ro and the resistor Ro may be connected between the switch SW and the ground voltage GND. Otherwise, the resistor Ro may be connected between the first node N1 and the switch SW and the switch SW may be connected between the resistor Ro and the ground voltage GND.

(79) The switch SW may be turned on when the Q sink signal QSS is enabled and turned off when the Q sink signal QSS is disabled.

(80) The resistor Ro may have a constant resistance value.

(81) As illustrated in FIG. 6, the pull-down unit 231b may selectively reduce the Q factor of the resonance unit 100 by connecting a resistive load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(82) FIG. 7 is a block diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 4.

(83) Referring to FIG. 7, the pull-down unit 231c may include a slew control unit 232, first to n.sup.th switches SW1, SW2, . . . , and SWn and first to n.sup.th current sources Io-1, Io-2, . . . , and Io-n, wherein N is an integer of 2 or more.

(84) FIG. 9 is a view to explain the operation of the slew control unit included in the pull-down unit of FIG. 7.

(85) Referring to FIG. 9, the slew control unit 232 may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially enabled at a first time interval Td, when the Q sink signal QSS is enabled and may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially disabled at the first time interval Td, when the Q sink signal QSS is disabled.

(86) Referring again to FIG. 7, the first to n.sup.th switches SW1, SW2, . . . , and SWn are connected in parallel to the first node N1, the first to n.sup.th current sources Io-1, Io-2, . . . , and Io-n are connected in parallel to the ground voltage GND, and the first to n.sup.th switches SW1, SW2, . . . , and SWn as well as the first to n.sup.th current sources Io-1, Io-2, . . . , and Io-n are connected with each other in series, respectively.

(87) The first to n.sup.th switches SW1, SW2, . . . , and SWn may be turned on when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are enabled, respectively, and may be turned off when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are disabled, respectively.

(88) The first to n.sup.th current sources Io-1, Io-2, . . . , and Io-n may generate the current having a constant magnitude.

(89) As shown in FIG. 7, the pull-down unit 231c may selectively reduce the Q factor of the resonance unit 100 by connecting a current load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(90) As appreciated by the present inventors, when the pull-down unit 231c concurrently turns on or turns off the first to n.sup.th switches SW1, SW2, . . . , and SWn, the magnitude of the first voltage V1 supplied to the NFC chip 200a from the resonance unit 100 may sway in a moment so that the error may occur during the data communication unless otherwise addressed.

(91) As described above, since the pull-down unit 231c sequentially turns on the first to n.sup.th current sources Io-1, Io-2, . . . , and Io-n at the first time interval Td when the Q sink signal QSS is enabled and sequentially turns off the first to n.sup.th current sources Io-1, Io-2, . . . , and Io-n at the first time interval Td when the Q sink signal QSS is disabled, the pull-down unit 231c can reduce the sway of the first voltage V1 when changing the Q factor of the resonance unit 100.

(92) FIG. 8 is a block diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 4.

(93) Referring to FIG. 8, the pull-down unit 231d may include a slew control unit 232, first to n.sup.th switches SW1, SW2, . . . , and SWn and first to n.sup.th resistors Ro-1, Ro-2, . . . , and Ro-n, wherein N is an integer of 2 or more.

(94) FIG. 9 is a view to explain the operation of the slew control unit included in the pull-down unit of FIG. 8.

(95) Referring to FIG. 9, the slew control unit 232 may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially enabled at a first time interval Td, when the Q sink signal QSS is enabled and may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially disabled at the first time interval Td, when the Q sink signal QSS is disabled.

(96) Referring again to FIG. 8, the first to n.sup.th switches SW1, SW2, . . . , and SWn are connected in parallel to the first node N1, the first to n.sup.th resistors Ro-1, Ro-2, . . . , and Ro-n are connected in parallel to the ground voltage GND, and the first to n.sup.th switches SW1, SW2, . . . , and SWn as well as the first to n.sup.th resistors Ro-1, Ro-2, . . . , and Ro-n are connected with each other in series, respectively.

(97) The first to n.sup.th switches SW1, SW2, . . . , and SWn may be turned on when the first to nth Q sink sub-signals QSS1, QSS2, . . . , and QSSn are enabled, respectively, and may be turned off when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are disabled, respectively.

(98) The first to n.sup.th resistors Ro-1, Ro-2, . . . , and Ro-n may have a constant resistance value.

(99) As shown in FIG. 8, the pull-down unit 231d may selectively reduce the Q factor of the resonance unit 100 by connecting a resistive load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(100) As appreciated by the present inventors, when the pull-down unit 231d concurrently turns on or turns off the first to n.sup.th switches SW1, SW2, . . . , and SWn, the magnitude of the first voltage V1 supplied to the NFC chip 200a from the resonance unit 100 may sway in a moment so that the error may occur during the data communication unless otherwise addressed.

(101) As described above, since the pull-down unit 231d sequentially connects the first to n.sup.th resistors Ro-1, Ro-2, . . . , and Ro-n between the first node N1 and the ground voltage GND at the first time interval Td when the Q sink signal QSS is enabled and sequentially cuts off the first to n.sup.th resistors Ro-1, Ro-2, . . . , and Ro-n connected between the first node N1 and the ground voltage GND at the first time interval Td when the Q sink signal QSS is disabled, the pull-down unit 231d can prevent the sway of the first voltage V1 when changing the Q factor of the resonance unit 100.

(102) FIG. 10 is a block diagram illustrating an example of the NFC device of FIG. 1.

(103) Only elements to operate the NFC device 10b in the card mode are illustrated in FIG. 10 and elements to operate the NFC device 10b in the reader mode are omitted in FIG. 10

(104) Referring to FIG. 10, the NFC device 10b may include a resonance unit 100 and an NFC chip 200b.

(105) The NFC device 10b of FIG. 10 is similar to the NFC device 10a of FIG. 3 except that the NFC device 10b of FIG. 10 further includes a field detector 260 and the Q sink unit 230 is replaced with a Q sink unit 235. Thus, in order to avoid redundancy, the following description will be made while focusing on the field detector 260 and the Q sink unit 235 without explaining the elements illustrated in the NFC device 10a.

(106) The field detector 260 may receive the first voltage V1 from the resonance unit 100 to measure the magnitude of the first voltage V1 and may generate a field intensity signal FIS corresponding to the magnitude of the first voltage V1. As the intensity of the EMW received from the external device becomes strong, the magnitude of the first voltage V1 generated from the resonance unit 100 is increased, so the field intensity signal FIS may represent the intensity of EMW received from the external device.

(107) The Q sink unit 235 may be connected between the first node N1 and the ground voltage GND. Based on the mode signal MD supplied from the CPU 240, the Q sink unit 235 is turned on to reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode and turned off to maintain the Q factor of the resonance unit 100 in the reader mode and when the signal transmit operation is performed in the card mode. In addition, the Q sink unit 235 may control the reduction degree of the Q factor of the resonance unit 100 based on the field intensity signal FIS when the signal receive operation is performed in the card mode.

(108) FIG. 11 is a block diagram illustrating an example of the Q sink unit included in the NFC device of FIG. 10.

(109) Referring to FIG. 11, the Q sink unit 235 may include a pull-down unit 236 and a Q sink controller 238.

(110) The Q sink controller 238 may generate a Q sink signal QSS which is enabled when the signal receive operation is performed in the card mode and is disabled in the reader mode and when the signal transmit operation is performed in the card mode. For instance, the Q sink controller 238 may generate the Q sink signal QSS based on the mode signal MD received from the CPU 240.

(111) In addition, the Q sink controller 238 may generate a Q factor tuning signal QTS[M-1:0] based on the field intensity signal FIS supplied from the field detector 260. The Q factor tuning signal QTS is an m-bit signal and may have a value proportional to a magnitude of the field intensity signal FIS, wherein m is a positive integer.

(112) The pull-down unit 236 may connect the first node N1 to the ground voltage GND through the pull-down load having a magnitude corresponding to a magnitude of the Q factor tuning signal QTS when the Q sink signal QSS is enabled and cut off the first node N1 from the ground voltage GND when the Q sink signal QSS is disabled.

(113) FIG. 12 is a diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 11.

(114) Referring to FIG. 12, the pull-down unit 236a may include a switch SW and a variable current source IV.

(115) The switch SW may be connected between the first node N1 and the variable current source IV and the variable current source IV may be connected between the switch SW and the ground voltage GND. Otherwise, the variable current source IV may be connected between the first node N1 and the switch SW and the switch SW may be connected between the variable current source IV and the ground voltage GND.

(116) The switch SW may be turned on when the Q sink signal QSS is enabled and turned off when the Q sink signal QSS is disabled.

(117) The variable current source IV may generate a current having a magnitude corresponding to the magnitude of the Q factor tuning signal QTS.

(118) As illustrated in FIG. 12, the pull-down unit 236a may selectively reduce the Q factor of the resonance unit 100 by connecting a current load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(119) In addition, when the pull-down unit 236a reduces the Q factor of the resonance unit 100, the pull-down unit 236a may adjust the reduction degree of the Q factor of the resonance unit 100 by adjusting the magnitude of the current load connected between the first node N1 and the ground voltage GND based on the Q factor tuning signal QTS.

(120) FIG. 13 is a diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 11.

(121) Referring to FIG. 13, the pull-down unit 236b may include a switch SW and a variable resistor RV.

(122) The switch SW may be connected between the first node N1 and the variable resistor RV and the variable resistor RV may be connected between the switch SW and the ground voltage GND. Otherwise, the variable resistor RV may be connected between the first node N1 and the switch SW and the switch SW may be connected between the variable resistor RV and the ground voltage GND.

(123) The switch SW may be turned on when the Q sink signal QSS is enabled and turned off when the Q sink signal QSS is disabled.

(124) The variable resistor RV may have a resistance value corresponding to the Q factor tuning signal QTS.

(125) As illustrated in FIG. 13, the pull-down unit 236b may selectively reduce the Q factor of the resonance unit 100 by connecting a resistive load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(126) In addition, when the pull-down unit 236b reduces the Q factor of the resonance unit 100, the pull-down unit 236b may adjust the reduction degree of the Q factor of the resonance unit 100 by adjusting the magnitude of the resistive load connected between the first node N1 and the ground voltage GND based on the Q factor tuning signal QTS.

(127) FIG. 14 is a block diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 11.

(128) Referring to FIG. 14, the pull-down unit 236c may include a slew control unit 237, first to n.sup.th switches SW1, SW2, . . . , and SWn and first to n.sup.th variable current sources IV-1, IV-2, . . . , and IV-n, wherein N is an integer of 2 or more.

(129) As illustrated in FIG. 9, the slew control unit 237 may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially enabled at a first time interval Td, when the Q sink signal QSS is enabled and may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially disabled at the first time interval Td, when the Q sink signal QSS is disabled.

(130) The first to n.sup.th switches SW1, SW2, . . . , and SWn are connected in parallel to the first node N1, the first to n.sup.th variable current sources IV-1, IV-2, . . . , and IV-n are connected in parallel to the ground voltage GND, and the first to n.sup.th switches SW1, SW2, . . . , and SWn as well as the first to n.sup.th variable current sources IV-1, IV-2, . . . , and IV-n are connected with each other in series, respectively.

(131) The first to n.sup.th switches SW1, SW2, . . . , and SWn may be turned on when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are enabled, respectively, and may be turned off when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are disabled, respectively.

(132) The first to n.sup.th variable current sources IV-1, IV-2, . . . , and IV-n may generate the current having a magnitude corresponding to the magnitude of the Q factor tuning signal QTS.

(133) As shown in FIG. 14, the pull-down unit 236c may selectively reduce the Q factor of the resonance unit 100 by connecting a current load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(134) As appreciated by the present inventors, when the pull-down unit 236c concurrently turns on or turns off the first to n.sup.th switches SW1, SW2, . . . , and SWn, the magnitude of the first voltage V1 supplied to the NFC chip 200b from the resonance unit 100 may sway in a moment so that the error may occur during the data communication unless otherwise addressed.

(135) As described above, since the pull-down unit 236c sequentially turns on the first to n.sup.th variable current sources IV-1, IV-2, . . . , and IV-n at the first time interval Td when the Q sink signal QSS is enabled and sequentially turns off the first to n.sup.th variable current sources IV-1, IV-2, . . . , and IV-n at the first time interval Td when the Q sink signal QSS is disabled, the pull-down unit 236c can reduce the sway of the first voltage V1 when changing the Q factor of the resonance unit 100.

(136) In addition, when the pull-down unit 236c reduces the Q factor of the resonance unit 100, the pull-down unit 236c may adjust the reduction degree of the Q factor of the resonance unit 100 by adjusting the magnitude of the current load connected between the first node N1 and the ground voltage GND based on the Q factor tuning signal QTS.

(137) FIG. 15 is a block diagram illustrating an example of the pull-down unit included in the Q sink unit of FIG. 11.

(138) Referring to FIG. 15, the pull-down unit 236d may include a slew control unit 237, first to n.sup.th switches SW1, SW2, . . . , and SWn and first to n.sup.th variable resistors RV-1, RV-2, . . . , and RV-n, wherein N is an integer of 2 or more.

(139) As illustrated in FIG. 9, the slew control unit 237 may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially enabled at a first time interval Td, when the Q sink signal QSS is enabled and may generate first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn, which are sequentially disabled at the first time interval Td, when the Q sink signal QSS is disabled.

(140) The first to n.sup.th switches SW1, SW2, . . . , and SWn are connected in parallel to the first node N1, the first to n.sup.th variable resistors RV-1, RV-2, . . . , and RV-n are connected in parallel to the ground voltage GND, and the first to n.sup.th switches SW1, SW2, . . . , and SWn as well as the first to n.sup.th variable resistors RV-1, RV-2, . . . , and RV-n are connected with each other in series, respectively.

(141) The first to n.sup.th switches SW1, SW2, . . . , and SWn may be turned on when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are enabled, respectively, and may be turned off when the first to n.sup.th Q sink sub-signals QSS1, QSS2, . . . , and QSSn are disabled, respectively.

(142) The first to n.sup.th variable resistors RV-1, RV-2, . . . , and RV-n may have a resistance value corresponding to the Q factor tuning signal QTS.

(143) As shown in FIG. 15, the pull-down unit 236d may selectively reduce the Q factor of the resonance unit 100 by connecting a resistive load between the first node N1 and the ground voltage GND based on the Q sink signal QSS.

(144) As appreciated by the present inventors, when the pull-down unit 236d concurrently turns on or turns off the first to n.sup.th switches SW1, SW2, . . . , and SWn, the magnitude of the first voltage V1 supplied to the NFC chip 200b from the resonance unit 100 may sway in a moment so that the error may occur during the data communication unless otherwise addressed.

(145) As described above, since the pull-down unit 236d sequentially connects the first to n.sup.th variable resistors RV-1, RV-2, . . . , and RV-n between the first node N1 and the ground voltage GND at the first time interval Td when the Q sink signal QSS is enabled and sequentially cuts off the first to n.sup.th variable resistors RV-1, RV-2, . . . , and RV-n connected between the first node N1 and the ground voltage GND at the first time interval Td when the Q sink signal QSS is disabled, the pull-down unit 236d can reduce the sway of the first voltage V1 when changing the Q factor of the resonance unit 100.

(146) In addition, when the pull-down unit 236d reduces the Q factor of the resonance unit 100, the pull-down unit 236d may adjust the reduction degree of the Q factor of the resonance unit 100 by adjusting the magnitude of the resistive load connected between the first node N1 and the ground voltage GND based on the Q factor tuning signal QTS.

(147) FIG. 16 is a block diagram to explain the operation the NFC devices of FIGS. 3 to 10.

(148) As illustrated in FIG. 16, the Q sink controllers 233 and 238 may generate the Q sink signal QSS which is enabled when the signal receive operation RX is performed in the card mode and is disabled in the reader mode and when the signal transmit operation TX is performed in the card mode. Therefore, since the Q sink units 230 and 235 are turned on when the signal receive operation is performed in the card mode, the resonance unit 100 may have the frequency characteristic as shown in the second graph B of FIG. 2, so the Q factor of the resonance unit 100 may be reduced. In addition, since the Q sink units 230 and 235 are turned off in the reader mode and when the signal transmit operation is performed in the card mode, the resonance unit 100 may have the frequency characteristic as shown in the first graph A of FIG. 2, so the Q factor of the resonance unit 100 may be maintained.

(149) FIGS. 17A and 17B are views to explain the effects of the NFC devices of FIGS. 3 and 10.

(150) The graph shown in FIG. 17A represents the first voltage V1 supplied to the NFC chips 200a and 200b from the resonance unit 100 in response to the high-speed signal having a frequency of 848 Kbps when the resonance unit 100 has the frequency characteristic as shown in the first graph A of FIG. 2 because the Q factor of the resonance unit 100 is not reduced (i.e., maintained) when the signal receive operation is performed in the card mode, and the graph shown in FIG. 17B represents the first voltage V1 supplied to the NFC chips 200a and 200b from the resonance unit 100 in response to the high-speed signal having a frequency of 848 Kbps when the resonance unit 100 has the frequency characteristic as shown in the second graph B of FIG. 2 because the Q factor of the resonance unit 100 is reduced when the signal receive operation is performed in the card mode.

(151) As shown in the graph of FIG. 17A, if the Q factor of the resonance unit 100 is not reduced, the high-speed signal is filtered through the resonance unit 100 so that a signal corresponding to the first voltage V1 supplied to the NFC chips 200a and 200b from the resonance unit 100 may be distorted. Thus, when the NFC chips 200a and 200b demodulates the signal corresponding to the first voltage V1 through the ASK (magnitude shift keying) scheme, the input data transmitted from the external device may not be normally received.

(152) However, as shown in the graph of FIG. 17B, if the Q factor of the resonance unit 100 is reduced, the high-speed signal is not filtered through the resonance unit 100 so that a signal corresponding to the first voltage V1 supplied to the NFC chips 200a and 200b from the resonance unit 100 may not be distorted (or distorted less). Thus, when the NFC chips 200a and 200b demodulates the signal corresponding to the first voltage V1 through the ASK (magnitude shift keying) scheme, the input data transmitted from the external device may be normally received.

(153) Therefore, the NFC devices 10a and 10b according to example embodiments can stably receive the high-speed signal when the signal receive operation is performed without degrading the characteristic of the load modulation when the signal receive operation is performed.

(154) FIG. 18 is a block diagram illustrating an example of the NFC device of FIG. 1.

(155) Elements used to operate the NFC device 10c in the reader mode as well as elements used to operate the NFC device 10c in the card mode are illustrated in FIG. 18.

(156) Referring to FIG. 18, the NFC device 10c may include a resonance unit 100 and an NFC chip 200c.

(157) The NFC chip 200c may be connected to the resonance unit 100 through a first power terminal L1, a second power terminal L2, a first transmit terminal TX1, a second transmit terminal TX2, and a receive terminal RX.

(158) The resonance unit 100 may include a resonance circuit having an antenna L and a first capacitor C1, a first filter having a second capacitor C2 and a third capacitor C3 to connect the resonance circuit to the first and second power terminals L1 and L2, a second filter having a sixth capacitor C6 to connect the resonance circuit to the receive terminal RX, and a matching unit including a fourth capacitor C4 and a fifth capacitor C5 to connect the resonance circuit to the first transmit terminal TX1 and the second transmit terminal TX2 in order to perform the impedance matching.

(159) The configuration of the resonance unit 100 illustrated in FIG. 18 is an example only and the configuration of the resonance unit 100 according to example embodiments may not be limited to the above, but may be variously modified.

(160) The NFC chip 200c may perform the signal transmit operation and the signal receive operation through the first power terminal L1 and the second power terminal L2 in the card mode, perform the signal transmit operation through the first transmit terminal TX1 and the second transmit terminal TX2 in the reader mode, and perform the signal receive operation through the receive terminal RX in the reader mode.

(161) The NFC chip 200c may include a rectifier 210, a regulator 220, a central processing unit (CPU) 240, a power switch PSW, a memory 250, a first demodulator 251, a first modulator 253, a second demodulator 271, a second modulator 273, an oscillator 275, a mixer 277 and a transmit unit 280.

(162) The rectifier 210, the regulator 220, the power switch PSW, the first demodulator 251 and the first modulator 253 can be equivalent to the regulator 220, the power switch PSW, the demodulator 251 and the modulator 253 included in the NFC device 10a of FIG. 3.

(163) When the signal receive operation is performed in the reader mode, the second demodulator 271 generates the input data by demodulating the signal supplied from the resonance unit 100 through the receive terminal RX to provide the input data to the CPU 240. The CPU 240 may store the input data in the memory 250.

(164) When the signal transmit operation is performed in the reader mode, the CPU 240 may read out the output data TD from the memory 250 to provide the output data TD to the second modulator 273, the second modulator 273 may modulate the output data TD to generate a modulation signal, the oscillator 275 may generate a carrier signal having a frequency corresponding to a carrier frequency (for instance, 13.56 MHz), and the mixer 277 may generate a transmit modulation signal TMS by synthesizing the carrier signal with the modulation signal.

(165) The transmit unit 280 may be connected between the supply voltage VDD and the ground voltage GND.

(166) The transmit unit 280 may receive the transmit modulation signal TMS from the mixer 277 to generate a transmit signal TS corresponding to the transmit modulation signal TMS in the reader mode. The resonance unit 100 may generate the EMW corresponding to the transmit signal TS supplied from the transmit unit 280 through the first transmit terminal TX1 and the second transmit terminal TX2. For instance, in the reader mode, the transmit unit 280 may connect the first transmit terminal TX1 and the second transmit terminal TX2 to the supply voltage VDD through a pull-up load or connect the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through a pull-down load based on the transmit modulation signal TMS so that the transmit signal TS may be generated from the first transmit terminal TX1 and the second transmit terminal TX2.

(167) The transmit unit 280 may reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode and may maintain the Q factor of the resonance unit 100 when the signal transmit operation is performed in the card mode. For instance, the transmit unit 280 may reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode by connecting the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through the pull-down load and may maintain the Q factor of the resonance unit 100 when the signal transmit operation is performed in the card mode by cutting off the first transmit terminal TX1 and the second transmit terminal TX2 from the ground voltage GND and the supply voltage VDD.

(168) In one example embodiment, the CPU 240 may provide the mode signal MD, which represents the card mode or the reader mode and the signal receive operation or the signal transmit operation when the mode is the card mode, to the transmit unit 280 and the transmit unit 280 may selectively reduce the Q factor of the resonance unit 100 based on the mode signal MD.

(169) FIG. 19 is a block diagram illustrating an example of the transmit unit included in the NFC device of FIG. 18.

(170) Referring to FIG. 19, the transmit unit 280a may include a first pull-up transistor MP0, a second pull-up transistor MP1, a first pull-down transistor MN0, a second pull-down transistor MN1 and a driving unit 281.

(171) The first pull-up transistor MP0 and the second pull-up transistor MP1 may be PMOS (p-type metal oxide semiconductor) transistors and the first pull-down transistor MN0 and the second pull-down transistor MN1 may be NMOS (n-type metal oxide semiconductor) transistors.

(172) The first pull-up transistor MP0 may be connected between the supply voltage VDD and the first transmit terminal TX1 and the first pull-down transistor MN0 may be connected between the first transmit terminal TX1 and the ground voltage GND.

(173) The second pull-up transistor MP1 may be connected between the supply voltage VDD and the second transmit terminal TX2 and the second pull-down transistor MN1 may be connected between the second transmit terminal TX2 and the ground voltage GND.

(174) The driving unit 281 may drive the first pull-up transistor MP0 through a first pull-up driving signal UDS0, may drive the first pull-down transistor MN0 through a first pull-down driving signal DDS0, may drive the second pull-up transistor MP1 through a second pull-up driving signal UDS1, and may drive the second pull-down transistor MN1 through a second pull-down driving signal DDS1.

(175) The driving unit 281 may determine whether the NFC chip 200c is in the card mode or the reader mode and may determine the signal receive operation or the signal transmit operation when the mode is the card mode based on the mode signal MD supplied from the CPU 240.

(176) The driving unit 281 may selectively turn on one of the first pull-up transistor MP0 and the first pull-down transistor MN0 and one of the second pull-up transistor MP1 and the second pull-down transistor MN1 based on the transmit modulation signal TMS in the reader mode.

(177) The driving unit 281 may turn off the first pull-up transistor MP0 and the second pull-up transistor MP1 and may turn on the first pull-down transistor MN0 and the second pull-down transistor MN1 when the signal receive operation is performed in the card mode.

(178) The driving unit 281 may turn off all of the first pull-up transistor MP0, the second pull-up transistor MP1, the first pull-down transistor MN0 and the second pull-down transistor MN1 when the signal transmit operation is performed in the card mode.

(179) As described above, the transmit unit 280a drives the first pull-up transistor MP0, the second pull-up transistor MP1, the first pull-down transistor MN0 and the second pull-down transistor MN1 based on the transmit modulation signal TMS in the reader mode to perform the normal operation to provide the transmit modulation signal TMS to the resonance unit 100. In addition, the transmit unit 280a connects the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through the first pull-down transistor MN0 and the second pull-down transistor MN1, respectively, thereby reducing the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode.

(180) FIG. 20 is a block diagram illustrating another example of the transmit unit included in the NFC device of FIG. 18.

(181) Referring to FIG. 20, the transmit unit 280b may include (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n, second-1 to second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n, (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n, second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n, and a driving unit 282.

(182) The (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n and the second-1 to second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n may be PMOS transistors, and the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n may be the NMOS transistors.

(183) The (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n may be connected in parallel between the supply voltage VDD and the first transmit terminal TX1, and the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n may be connected in parallel between the first transmit terminal TX1 and the ground voltage GND.

(184) The second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n may be connected in parallel between the supply voltage VDD and the second transmit terminal TX2 and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n may be connected in parallel between the second transmit terminal TX2 and the ground voltage GND.

(185) The driving unit 282 may drive the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n through (1-1).sup.th to (1-n).sup.th pull-up driving signals UDS0-1, UDS0-2, . . . , and UDS0-n, respectively, drive the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n through (1-1).sup.th to (1-n).sup.th pull-down driving signals DDS0-1, DDS0-2, . . . , and DDS0-n, respectively, drive the second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n through second-1 to second-n pull-up driving signals UDS1-1, UDS1-2, . . . , and UDS1-n, respectively, and drive the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n through second-1 to second-n pull-down driving signals DDS1-1, DDS1-2, . . . , and DDS1-n, respectively.

(186) The driving unit 282 may determine whether the NFC chip 200c is in the card mode or the reader mode and may determine the signal receive operation or the signal transmit operation when the mode is the card mode based on the mode signal MD supplied from the CPU 240.

(187) In the reader mode, the driving unit 282 may turn on the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n or the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and may turn on the second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n or the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n based on the transmit modulation signal TMS.

(188) In the card mode, the driving unit 282 generates the (1-1).sup.th to (1-n).sup.th pull-up driving signals UDS0-1, UDS0-2, . . . , and UDS0-n and the second-1 to second-n pull-up driving signals UDS1-1, UDS1-2, . . . , and UDS1-n having the logic high level, so the driving unit 282 can turn off the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n and the second-1 to second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n.

(189) In addition, as shown in FIG. 21, the driving unit 282 may sequentially turn on the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n at the first time interval Td by sequentially enabling the (1-1).sup.th to (1-n).sup.th pull-down driving signals DDS0-1, DDS0-2, . . . , and DDS0-n and the second-1 to second-n pull-down driving signals DDS1-1, DDS1-2, . . . , and DDS1-n at the first time interval Td when the signal receive operation RX is performed in the card mode.

(190) Further, as shown in FIG. 21, the driving unit 282 may sequentially turn off the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n at the first time interval Td by sequentially disabling the (1-1).sup.th to (1-n).sup.th pull-down driving signals DDS0-1, DDS0-2, . . . , and DDS0-n and the second-1 to second-n pull-down driving signals DDS1-1, DDS1-2, . . . , and DDS1-n at the first time interval Td when the signal transmit operation TX is performed in the card mode.

(191) As described above, the transmit unit 280b drives the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n, the second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n, the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n based on the transmit modulation signal TMS in the reader mode to perform the normal operation to provide the transmit signal TS to the resonance unit 100. In addition, when the signal receive operation is performed in the card mode, the transmit unit 280b connects the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n, respectively, thereby reducing the Q factor of the resonance unit 100.

(192) As appreciated by the present inventors, when the transmit unit 280b concurrently turns on or off the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n in the card mode, the magnitude of the voltage in the first power terminal L1 and the second power terminal L2 may sway in a moment so that the error may occur during the data communication unless otherwise addressed.

(193) As described above, the transmit unit 280b sequentially turns on the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n at the first time interval Td when the signal receive operation is performed in the card mode, and sequentially turns off the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MNO-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n at the first time interval Td when the signal transmit operation is performed in the card mode, thereby preventing the sway of the voltage in the first power terminal L1 and the second power terminal L2 when changing the Q factor of the resonance unit 100.

(194) FIG. 22 is a block diagram illustrating an example of the NFC device of FIG. 1.

(195) Elements used to operate the NFC device 10d in the reader mode as well as elements used to operate the NFC device 10d in the card mode are illustrated in FIG. 22.

(196) Referring to FIG. 22, the NFC device 10d may include a resonance unit 100 and an NFC chip 200d.

(197) The NFC device 10d of FIG. 22 is similar to the NFC device 10c of FIG. 18 except that the NFC device 10d of FIG. 22 further includes a field detector 290 and the transmit unit 280 is replaced with a transmit unit 285. Thus, in order to avoid redundancy, the following description will be made while focusing on the field detector 290 and the transmit unit 285 without explaining the elements illustrated in the NFC device 10c.

(198) The field detector 290 may measure the voltage supplied from the resonance unit 100 through the first power terminal L1 and the second power terminal L2 to generate a field intensity signal FIS corresponding to the magnitude of the measured voltage. As the intensity of the EMW received from the external device becomes strong, the magnitude of the voltage supplied to the first power terminal L1 and the second power terminal L2 from the resonance unit 100 is increased, so the field intensity signal FIS may represent the intensity of EMW received from the external device.

(199) The transmit unit 285 may be connected between the supply voltage VDD and the ground voltage GND.

(200) The transmit unit 285 may determine whether the NFC chip 200d is in the card mode or the reader mode and may determine the signal receive operation or the signal transmit operation when the mode is the card mode based on the mode signal MD supplied from the CPU 240.

(201) The transmit unit 285 may receive the transmit modulation signal TMS from the mixer 277 to generate the transmit signal TS corresponding to the transmit modulation signal TMS in the reader mode. The resonance unit 100 may generate the EMW corresponding to the transmit signal TS supplied from the transmit unit 285 through the first transmit terminal TX1 and the second transmit terminal TX2. For instance, in the reader mode, the transmit unit 285 may connect the first transmit terminal TX1 and the second transmit terminal TX2 to the supply voltage VDD through a pull-up load or connect the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through a pull-down load based on the transmit modulation signal TMS so that the transmit signal TS may be generated from the first transmit terminal TX1 and the second transmit terminal TX2.

(202) The transmit unit 285 may reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode and may maintain the Q factor of the resonance unit 100 when the signal transmit operation is performed in the card mode. For instance, the transmit unit 285 may reduce the Q factor of the resonance unit 100 when the signal receive operation is performed in the card mode by connecting the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through the pull-down load and may maintain the Q factor of the resonance unit 100 when the signal transmit operation is performed in the card mode by cutting off the first transmit terminal TX1 and the second transmit terminal TX2 from the ground voltage GND and the supply voltage VDD. In addition, the transmit unit 285 may control the reduction degree of the Q factor of the resonance unit 100 based on the field intensity signal FIS when the signal receive operation is performed in the card mode.

(203) FIG. 23 is a block diagram illustrating an example of the transmit unit included in the NFC device of FIG. 22.

(204) Referring to FIG. 23, the transmit unit 285a may include (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n, second-1 to second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n, (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n, second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n, and a driving unit 283.

(205) The (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n and the second-1 to second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n may be PMOS transistors, and the (1-1).sup.th (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n may be the NMOS transistors.

(206) The (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n may be connected in parallel between the supply voltage VDD and the first transmit terminal TX1, and the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n may be connected in parallel between the first transmit terminal TX1 and the ground voltage GND.

(207) The second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n may be connected in parallel between the supply voltage VDD and the second transmit terminal TX2 and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n may be connected in parallel between the second transmit terminal TX2 and the ground voltage GND.

(208) The driving unit 283 may drive the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n through (1-1).sup.th to (1-n).sup.th pull-up driving signals UDS0-1, UDS0-2, . . . , and UDS0-n, respectively, drive the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n through (1-1).sup.th to (1-n).sup.th pull-down driving signals DDS0-1, DDS0-2, . . . , and DDS0-n, respectively, drive the second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n through second-1 to second-n pull-up driving signals UDS1, UDS2, . . . , and UDS1-n, respectively, and drive the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n through second-1 to second-n pull-down driving signals DDS1-1, DDS1-2, . . . , and DDS1-n, respectively.

(209) The driving unit 283 may determine whether the NFC chip 200d is in the card mode or the reader mode and may determine the signal receive operation or the signal transmit operation when the mode is the card mode based on the mode signal MD supplied from the CPU 240.

(210) In the reader mode, the driving unit 283 may turn on the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n or the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and may turn on the second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n or the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n based on the transmit modulation signal TMS.

(211) In the card mode, the driving unit 283 may select k pull-down transistors from among the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n based on the field intensity signal FIS. For instance, the driving unit 283 may select the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k, wherein k is a positive integer equal to or less than n.

(212) In the card mode, the driving unit 283 generates the (1-1).sup.th to (1-n).sup.th pull-up driving signals UDS0-1, UDS0-2, . . . , and UDS0-n and the second-1 to second-n pull-up driving signals UDS1-1, UDS1-2, . . . , and UDS1-n having the logic high level, so the driving unit 283 can turn off the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n and the second-1 to second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n. In addition, as shown in FIG. 24, the driving unit 283 generates the (1-(k+1)).sup.th to (1-n).sup.th pull-down driving signals DDS0-(k+1), . . . , and DDS0-n and the second-(k+1) to second-n pull-down driving signals DDS1-(k+1), . . . , and DDS1-n having the logic low level, so the driving unit 283 can turn off the (1-(k+1)).sup.th to (1-n).sup.th pull-down transistors MN0-(k+1), . . . , and MN0-n and the second-(k+1) to second-n pull-down transistors MN1-(k+1), . . . , and MN1-n, which are not selected.

(213) In addition, as shown in FIG. 24, the driving unit 283 may sequentially turn on the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k at the first time interval Td by sequentially enabling the (1-1).sup.th to (1-k).sup.th pull-down driving signals DDS0-1, DDS0-2, . . . , and DDS0-k and the second-1 to second-k pull-down driving signals DDS1-1, DDS1-2, . . . , and DDS1-k at the first time interval Td when the signal receive operation RX is performed in the card mode.

(214) Further, as shown in FIG. 24, the driving unit 283 may sequentially turn off the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k at the first time interval Td by sequentially disabling the (1-1).sup.th to (1-k).sup.th pull-down driving signals DDS-1, DDS-2, . . . , and DDS0-k and the second-1 to second-k pull-down driving signals DDS1-1, DDS1-2, . . . , and DDS1-k at the first time interval Td when the signal transmit operation TX is performed in the card mode.

(215) As described above, the transmit unit 285a drives the (1-1).sup.th to (1-n).sup.th pull-up transistors MP0-1, MP0-2, . . . , and MP0-n, the second-n pull-up transistors MP1-1, MP1-2, . . . , and MP1-n, the (1-1).sup.th to (1-n).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-n and the second-1 to second-n pull-down transistors MN1-1, MN1-2, . . . , and MN1-n based on the transmit modulation signal TMS in the reader mode to perform the normal operation to provide the transmit signal TS to the resonance unit 100. In addition, when the signal receive operation is performed in the card mode, the transmit unit 285a connects the first transmit terminal TX1 and the second transmit terminal TX2 to the ground voltage GND through the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k, respectively, thereby reducing the Q factor of the resonance unit 100. In addition, the transmit unit 285a may control the reduction degree of the Q factor of the resonance unit 100 by adjusting the number (k) of pull-down transistors to be turned on when the signal receive operation is performed in the card mode based on the field intensity signal FIS.

(216) As appreciated by the present inventors, when the transmit unit 285a concurrently turns on or off the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k in the card mode, the magnitude of the voltage in the first power terminal L1 and the second power terminal L2 may sway in a moment so that the error may occur during the data communication unless otherwise addressed.

(217) As described above, the transmit unit 285a sequentially turns on the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k at the first time interval Td when the signal receive operation is performed in the card mode, and sequentially turns off the (1-1).sup.th to (1-k).sup.th pull-down transistors MN0-1, MN0-2, . . . , and MN0-k and the second-1 to second-k pull-down transistors MN1-1, MN1-2, . . . , and MN1-k at the first time interval Td when the signal transmit operation is performed in the card mode, thereby preventing the sway of the voltage in the first power terminal L1 and the second power terminal L2 when changing the Q factor of the resonance unit 100.

(218) FIG. 25 is a block diagram illustrating an electronic system according to example embodiments.

(219) Referring to FIG. 25, an electronic system 1000 includes an application processor AP 1100, an NFC (near field communication) device 1200, a memory device 1300, a user interface 1400 and a power supply 1500. In some embodiments, the electronic system 1000 may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a laptop computer, etc.

(220) The application processor 1100 may control overall operations of the electronic system 1000. The application processor 1100 may execute applications, such as a web browser, a game application, a video player, etc. In some embodiments, the application processor 1100 may include a single core or multiple cores. For example, the application processor 1100 may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. The application processor 1100 may include an internal or external cache memory.

(221) The memory device 1300 may store data used to operate the electronic system 1000. For example, the memory device 1300 may store a boot image for booting the electronic system 1000, data to be output to an external device and input data received from the external device. For example, the memory device 1300 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.

(222) The NFC device 1200 may provide the data stored in the memory device 1300 to the external device through NFC and store the input data received from the external device through NFC into the memory device 1300. The NFC device 1200 may include a resonance unit 1210 and an NFC chip 1220. The resonance unit 1210 may provide data communication with the external device through an electromagnetic wave. The NFC chip 1220 may provide the output data to the resonance unit 1210, receive the input data from the resonance unit 1210, reduce a Q factor (quality factor) of the resonance unit 1210 when a signal receive operation is performed in a card mode, and maintain the Q factor of the resonance unit 1210 in a reader mode and when a signal transmit operation is performed in the card mode. The NFC device 1200 may be embodied with the NFC device 10 of FIG. 1. A structure and an operation of the NFC device 10 are described with reference to FIGS. 1 to 24.

(223) The user interface 1400 may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply 1500 may supply a power supply voltage to the electronic system 1000.

(224) In some embodiments, the electronic system 1000 may further include an image processor, and/or a storage device, such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

(225) In some embodiments, the electronic system 1000 and/or components of the electronic system 1000 may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP).

(226) The foregoing is illustrative of the present inventive concept and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.