HfLaO passivated zinc-oxide thin-film transistor with high field-effect mobility

Abstract

Improved thin film transistor device and method, comprising transparent multi-layer thin-film transistors (TFT) disposed over a flexible polyethylene naphthalate (PEN) substrate with a nano-crystalline ZnO channel layer, and a novel HfLaO passivation layer. This device, which may be made at room temperature, has a high field-effect mobility (.sub.FE) of 345 cm2/Vs, small sub-threshold slope (SS) of 103 mV/dec, high on-current/off-current (I.sub.ON/I.sub.OFF) of 710.sup.6, and a low drain-voltage (V.sub.D) of 2V for low power operation. Although prior art ZnO based TFT had unimpressive performance, use of the novel HfLaO passivation layer appears to greatly improve the performance of ZnO TFT by preventing trace levels of H.sub.2O from forming unwanted ZnOH bonds, thus disrupting ZnO nanocrystals. At least some of the problems with prior ZnO TFT may be attributed to these ZnOH bonds, which damage ZnO crystallinity, create charged scattering centers, and form potential barriers that degrade mobility.

Claims

1. An apparatus comprising: a flexible or a rigid substrate layer; at least one multi-layer thin-film transistor disposed over said substrate layer, at least one of said layers comprising a nano-crystaline zinc-oxide or other metal-oxide channel layer; at least some of said layers further comprising gate layers; and at least one of said layers further comprising a passivation layer selected from any of HfLaO or other material selected to prevent ambient moisture from disrupting nano-crystals in said nano-crystalline zinc-oxide channel layer.

2. The apparatus of claim 1, wherein said nano-crystalline zinc-oxide or other metal-oxide channel layer is further selected to be substantially free from HOZnOH compounds that disrupt nano-crystals in said nano-crystalline zinc-oxide layers.

3. The apparatus of claim 1, wherein said gate layers further comprises a high dielectric constant gate oxide stack comprising HfO.sub.2, TiO.sub.2, and SiO.sub.2 or other high-dielectric constant material layers.

4. The apparatus of claim 1, wherein said gate layers further comprise a metal-gate, said metal gate comprising a metal gate layer, layers comprising a high dielectric constant gate, and a layer comprising source/drain electrodes.

5. The apparatus of claim 4, wherein said high dielectric constant gate comprises a high dielectric constant gate oxide stack comprising HfO.sub.2, TiO.sub.2, and SiO.sub.2 layers.

6. The apparatus of claim 4, wherein said metal gate layer comprises a TaN gate metal, and said source drain electrodes comprise aluminum source/drain electrodes.

7. The apparatus of claim 1, wherein said apparatus further comprises a smoothing layer disposed over said flexible substrate layer, and wherein said at least one multi-layer thin film transistor is disposed over said smoothing layer.

8. The apparatus of claim 7, wherein said smoothing layer comprises a SiO.sub.2 layer.

9. The apparatus of claim 1, wherein said apparatus is transparent; and said substrate layer is an optically clear material.

10. The apparatus of claim 1, wherein said flexible substrate layer comprises a flexible polyethylene naphthalate substrate.

11. A substantially transparent apparatus comprising: An optically clear flexible substrate layer; at least one multi-layer thin-film transistor disposed over said flexible substrate layer, at least one of said layers comprising a nano-crystalline zinc-oxide channel layer; at least some of said layers further comprising gate layers, said gate layers comprising a metal gate layer, layers comprising a high dielectric constant gate, and a layer comprising source/drain electrodes; and at least one of said layers further comprising a HfLaO passivation layer.

12. The apparatus of claim 11, wherein said nano-crystalline zinc-oxide channel layer is further selected to be substantially free from HOZnOH compounds that disrupt nano-crystals in said nano-crystalline zinc-oxide layers.

13. The apparatus of claim 11, wherein said gate layers further comprises a high dielectric constant gate oxide stack comprising HfO.sub.2, TiO.sub.2, and SiO.sub.2 layers.

14. The apparatus of claim 11, wherein said metal gate layer comprises a TaN or other gate metal, and said source drain electrodes comprise aluminum source/drain electrodes.

15. The apparatus of claim 11, wherein said apparatus further comprises a smoothing layer disposed over said flexible substrate layer, and wherein said at least one multi-layer thin film transistor is disposed over said smoothing layer.

16. The apparatus of claim 15, wherein said smoothing layer comprises a SiO.sub.2 layer.

17. The apparatus of claim 11, wherein said flexible substrate layer comprises a flexible polyethylene naphthalate or other organic substrate.

18. A method of improving high field-effect mobility characteristics of a thin-film transistor, said method comprising: forming a multi-layer thin-film transistor by depositing at least one nano-crystalline zinc-oxide thin film transistor channel layer over a support comprising a substrate layer; and depositing at least one passivation layer over said support so that said nano-crystalline zinc-oxide channel layer is disposed between said support and said at least one passivation layer.

19. The method of claim 18, wherein said at least one passivation layer comprises HfLaO.

20. The method of claim 18, wherein said method further comprises preventing ambient moisture from disrupting nano-crystals in said nano-crystalline zinc-oxide channel layer; and wherein said at least one passivation layer comprises a material selected to prevent ambient moisture from disrupting nano-crystals in said nano-crystalline zinc-oxide channel layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG. 1 shows a photograph of a bendable electronic device fabricated from TFTs on a flexible PEN substrate.

[0024] FIG. 2 shows the I.sub.DS-V.sub.DS and characteristics of ZnO/high-/TaN TFT on flexible PEN without (a) and with (b) HfLaO passivation. FIG. 2 also shows the I.sub.DS-V.sub.GS characteristics of ZnO/high-/TaN TFT on flexible PEN without and with HfLaO passivation (c).

[0025] FIG. 3 shows the .sub.FE-V.sub.GS characteristics of ZnO/high-/TaN TFT on flexible PEN both without and with HfLaO passivation.

[0026] FIG. 4 shows: (a) SIMS depth profile of various layers of ZnO on HfO.sub.2/TiO.sub.2/SiO.sub.2 stacked gate dielectrics, (b) a cross-sectional transmission electron microscope (TEM) photograph showing some of the various layers, and (c) XRD spectra of the same ZnO/high-/TaN structure on a flexible PEN substrate.

[0027] FIG. 5 shows the XPS spectra of a ZnO/high-/TaN layered structure on flexible PEN substrate (a) without and (b) with HfLaO passivation. Here the passivated HfLaO passivation layer was removed for the XPS measurement.

[0028] FIG. 6 shows a schematic of the ZnO/high-/TaN energy bands and the nano-crystalline-ZnO band structures on flexible PEN without (left) and with (right) a HfLaO-passivation layer.

DETAILED DESCRIPTION OF THE INVENTION

[0029] As previously discussed, the invention may be viewed as a solution to the problem, Why do ZnO based TFT have generally unimpressive performance?, or How to produce ZnO based TFT with substantially improved performance?

[0030] As will be described in more detail shortly, in one embodiment, the invention may be an apparatus (e.g. an electronic apparatus) comprising: a flexible (e.g. PEN) or a rigid (e.g. glass) substrate layer, with at least one multi-layer thin-film transistor disposed over this substrate layer. At least one of these layers will comprise a nano-crystalline zinc-oxide metal-oxide channel layer. In some embodiments, other types of metal oxide channel layers may also be used. At least some of these layers will further comprise gate layers. In a particularly favored embodiment, at least one of these layers will further comprise an HfLaO passivation layer selected to prevent ambient moisture from disrupting nano-crystals in the nano-crystalline zinc-oxide channel layer. Alternatively other types of materials (which can include other types of LaO materials) selected to prevent ambient moisture from disrupting nano-crystals in the nano-crystalline zinc-oxide channel layer may also be used.

[0031] In some embodiments, which are particularly useful for display devices, the substrate layer may be an optically clear material, and the apparatus may be transparent. If a flexible substrate layer is desired (for example to produce a flexible device, such as a flexible display device), the flexible substrate layer can comprise a flexible polyethylene naphthalate substrate.

[0032] FIG. 1 shows a photo of the flexible TFT devices fabricated on a flexible PEN substrate.

[0033] In some embodiments, the gate layers can further comprise a high dielectric constant gate oxide stack comprising HfO.sub.2, TiO.sub.2, and SiO.sub.2 or other high-dielectric constant material layers. Alternatively or additionally, the gate layers can further comprise a metal-gate, such as a metal gate layer (such as a tantalum nitride gate material), layers comprising a high dielectric constant gate (which itself can be a high dielectric constant gate oxide stack comprising HfO.sub.2, TiO.sub.2, and SiO.sub.2 layers), and a layer comprising source/drain electrodes such as aluminum source/drain electrodes.

[0034] In some embodiments, the apparatus will further comprise a smoothing layer disposed over this flexible substrate layer. Here at least one multi-layer thin film transistor is typically disposed over this smoothing layer.

[0035] As will be discussed in more detail, an important aspect of the invention is that the nano-crystalline zinc-oxide (or other crystallized metal-oxide) channel layer be further selected or treated so as to be substantially free from HOZnOH (e.g. Zn(OH).sub.2) compounds that disrupt nano-crystals in these nano-crystalline zinc-oxide (or other crystallized metal-oxide) layers. As will be discussed, one good way to accomplish this is to use the passivation techniques disclosed herein to help prevent formation of such Zn(OH.sub.2) compounds.

[0036] Alternatively, the invention may also comprise a method of improving the high field-effect mobility characteristics of a thin-film transistor. This method may comprise forming a multi-layer thin-film transistor by depositing at least one nano-crystalline zinc-oxide thin film transistor channel layer over a support comprising a substrate layer. In a preferred embodiment, the method will also comprise depositing at least one passivation layer, such as an HfLaO passivation layer, over this support so that the nano-crystalline zinc-oxide channel layer is disposed between the support and this at least one passivation layer.

[0037] For example, the method can further comprise preventing ambient moisture from disrupting nano-crystals in the nano-crystalline zinc-oxide channel layer. This can be done by using (e.g. applying to the device) at least one passivation layer comprising a material (e.g. HfLaO, LaO) and/or other material selected to prevent ambient moisture from disrupting nano-crystals in the nano-crystalline zinc-oxide channel layer.

[0038] A high capacitance density of 0.35 F/cm.sup.2 was measured that lead to an equivalent-oxide-thickness (EOT) of 9.9 nm. A still low leakage current of 1.410.sup.5 A/cm.sup.2 was measured at 1.5 V, even when the devices were processed at room temperature. These results show the merits of the high- dielectrics, especially the higher TiO.sub.2 dielectric. The TiO.sub.2 has a higher value for low voltage operation. To improve the interface, extra SiO.sub.2 dielectric was inserted between ZnO and TiO2. To improve the leakage current via the low conduction band offset (E.sub.C) of TiO.sub.2, stacked TiO.sub.2/HfO.sub.2 was applied.

[0039] In general, high dielectric constant gate oxide materials can include HfO.sub.2, ZrO.sub.2, Al.sub.2O.sub.3, La.sub.2O.sub.3 and their mixed ternary or quaternary compounds. A preferred high dielectric constant typically ranges from about 20 to 100.

[0040] FIG. 2(a), FIG. 2(b) and FIG. 2(c) show the transistor's drain-source current versus drain-source voltage (I.sub.DSV.sub.DS), and I.sub.DS versus gate-source voltage (I.sub.DSV.sub.GS) characteristics of ZnO/high-/metal-gate TFTs both with and without HfLaO passivation. The ZnO TFTs without passivation show reasonable performance of I.sub.ON/I.sub.OFF of 210.sup.5, SS of 112 mV/dec, and a V.sub.T of 0.78 V. Here the gate leakage current is lower than I.sub.OFF due to the thick stacked gate dielectric.

[0041] After HfLaO passivation, the ZnO TFTs show more than an order of magnitude higher I.sub.ON and 4 times lower I.sub.OFF, with a large I.sub.ON/I.sub.OFF of 710.sup.6, a small SS of 103 mV/dec, and a low V.sub.T of 0.13 V. This good device performance was achieved at a low VD of 2V. This low voltage is crucial because it lowers the switching power by orders of magnitude relative to prior art TFT devices. Additionally, the steep SS means that the transistors can be turned on faster for lower voltage and power operation

[0042] The .sub.EF-V.sub.GS characteristics, obtained from the measured I.sub.DS-V.sub.GS characteristics, are shown in FIG. 3. For control non-passivated devices, a relatively low peak .sub.FE of 43 cm.sup.2/Vs is obtained for room-temperature-processed ZnO TFT.

[0043] By contrast, after HfLaO passivation, the invention's improved TFT devices produced a remarkably high mobility .sub.FE value of 345 cm.sup.2/Vs. This is the highest mobility value for TFT on flexible substrate that has been observed to date, and is even higher than the reported mobility values for IGZO and ZnON TFTs fabricated on rigid substrates.

[0044] Note that the much improved mobility .sub.FE for HfLaO-passivated devices are due to the higher I.sub.ON and the lower I.sub.OFF values.

[0045] It is important to notice that the .sub.FE value increases monotonically with increasing gate length:

[00001]$\begin{array}{cc}{}_{\mathrm{FE}}{}_0.Math.\frac{L}{L+{}_0.Math.{\mathrm{WC}}_{\mathrm{oX}}.Math.R_{\mathrm{SD}}\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)}& \left(1\right)\end{array}$

[0046] Here R.sub.SD is the source/drain series resistance, L is the gate length, .sub.FE is the apparent field-effect mobility and .sub.0 is the true field effect mobility. At long gate lengths, the value of .sub.FE approaches that of .sub.0; thus, for better performance, a relatively long gate length (48 m gate length) was used.

[0047] How can HfLaO passivation produce such an unexpectedly large improvement in mobility? To better understand this effect, the material and structure of the various devices were analyzed in more detail. These results are shown in FIGS. 4 and 5.

[0048] FIG. 4(a) shows a secondary ion mass spectrometry (SIMS) depth profile of a ZnO channel, HfO2, TiO.sub.2, and thin SiO.sub.2 gate dielectric stack, showing that all layers can be recognized. The device structure layers of Al contact, ZnO channel, high-K gate dielectric stack, and TaN (tantalum nitride) metal-gate were also observable from the cross-sectional transmission electron microscopy (TEM) image shown in FIG. 4(b).

[0049] The results show that the ZnO active layer forms a columnar nano-crystalline structure with an average crystal structure size of 10-20 nm. The formed crystalline nature of this structure is further revealed in the X-ray diffraction (XRD) spectra shown in FIG. 4(c). Even though the ZnO in this active layer was deposited by sputtering at room temperature (and thus might be expected to have a more amorphous X-ray diffraction structure), highly oriented phases of XRD peaks, indicating a nano-crystalline structure, were measured.

[0050] Note that although we use the term nano-crystalline to refer to ZnO and other nano-crystalline metal oxides, the alternative term polycrystalline metal-oxide may also be used. Often a preferred nano-crystalline or poly-crystalline grain size for such materials is between 1 nm to 300 nm

[0051] The full-width at half-maximum (FWHM) X-ray diffraction patterns revealed by the XRD spectra are comparable with the data of ZnO published in literature (e.g. Chen, R. et al. Self-aligned top-gate InGaZnO thin film transistors using SiO.sub.2/A.sub.12O.sub.3 stack gate dielectric. Thin Solid Films 548, 572 (2013); Im, S., Jin, B. J. & Yi, S. Ultraviolet emission and microstructural evolution in pulsed-laser-deposited ZnO films. J. Appl. Phys. 87, 9 (2000). By contrast, IGZO layers, under XRD, exhibit an amorphous structure.

[0052] FIG. 5(a) and FIG. 5(b) compare the XPS spectra obtained from TFT devices respectively produced without (5a) and with (5b) HfLaO passivation. The atomic composition of the nano-crystalline structure is identified to be Zn.sup.2+O.sup.2, as measured from the XPS spectra. Note that a significant amount of OH bonding signal obtained from the non-passivated device (5a), which was much higher than the amount of OH bonding signal obtained from the HfLaO passivated device (5b).

[0053] Even though dry process steps were used to fabricate the devices, the OH bonding in nano-crystalline ZnO appears to have originated by the device's absorption of small amounts of residual moisture from the dry ambient air used in the manufacturing process.

[0054] The chemical reaction of ZnO and H.sub.2O is expressed as:

ZnO+H.sub.2O.fwdarw.Zn(OH).sub.2(2)

[0055] Water (H.sub.2O) molecules are relatively small, and in addition to reacting with surface ZnO, can also penetrate into the depths of the thin (20-nm) ZnO layer and react with ZnO nanocrystal grain boundaries through this layer. These grain boundaries have a high defect density, and thus are highly reactive with H.sub.2O.

[0056] Once Zn(OH).sub.2 is formed, it further damages the ZnO bonded nano-crystals, and creates dangling bonds. These dangling bonds also form charged states in the ZnO bandgap.

[0057] Changes in the XPS OH signal, and related charge defects, are also supported from the high positive charge density (Q.sub.p) of 210.sup.12 cm.sup.2. This was obtained from the V.sub.T shift (V.sub.T) between the HfLaO-passivated and non-passivated ZnO devices shown in FIG. 3(b); and from the formula Q.sub.p=C.sub.GV.sub.T

[0058] Such positive charge and dangling bond effects have been seen before for other materials. For example, these positive charges and dangling bonds are also found in the interim SiO.sub.x region between SiO.sub.2 layers and the Silicon (Si) body/support/substrate.

[0059] On the other hand, in the HfLaO passivated device shown in FIG. 5b, the XPS spectra OH bonding signal is much lowered, relative to the non-passivated device shown in FIG. 5a. However high- gate dielectrics, such as La.sub.2O.sub.3, can also absorb moisture, which in turn can also reduce amount of Zn(OH).sub.2 formation.

[0060] In terms of the solid state physics of the situation, we believe that the high-density positive Q.sub.p further causes the Fermi-level to come closer to the valance band. As shown in the schematic diagrams of FIG. 6, the positive charge in the surface and the raised surface potential can also increase the ZnO depletion region, and lower the n-type ZnO conduction.

[0061] FIG. 6 shows that because the invention's improved HfLaO proper passivation blocks the reaction between H.sub.2O and ZnO, the OH bonding related charges in HfLaO/ZnO are much reduced. This in turn reduces the potential barriers at both surface and grain boundaries, which in succession leads to much higher mobility, because the nano-crystalline form of ZnO has overlapped s-orbitals for conduction.

[0062] More specifically, FIG. 6 is inferred from the measured Id-Vg results; the non-passivated device showed a positive Vt shift, which is related to positive charge in the ZnO because both passivated and non-passivated devices were made at the same time. The positive charges raised the Fermi-level to deplete the ZnO, and create potential barriers at the nano-crystalline or poly-crystalline grain boundaries, which in turn leads to lower mobility. In FIG. 6, the various parallelograms can be viewed as representing these nano-crystalline or polycrystalline grains.

[0063] In a MOSFET type device, the electron wave-function typically distributes over about 20 nm. Therefore the high-density Q.sub.p will also increase electron scattering rates, and decrease mobility. However, the passivation does not affect the gate equivalent-oxide-thickness (EOT), because the EOT of a TFT only counts the dielectric next to the gate.

[0064] The improved passivation techniques disclosed herein can really be viewed as teaching proper passivation for this type of system. Proper passivation blocks the reaction between H.sub.2O and ZnO. As a result, the amount of OH bonding in HfLaO/ZnO materials is much reduced. This lowers the Q.sub.p and the potential barriers at the ZnO grain boundaries. The net result of the invention's improved passivation techniques is a much higher mobility. From a physics perspective, this is because the nano-crystalline form of ZnO has overlapped s-orbitals that improve conduction

[0065] Table 1 compares the device performance of various materials deposited on both flexible and rigid substrates. Here the prior art values with ZnO, MoS.sub.2 on flexible substrates was taken from Li, H. U. et al. ZnO thin film transistors for more than just displays. IEDM Tech. Dig. 523 (2015); and Petrone, N., Cui, X., Hone, J., Chari, T. & Shepard, K. Flexible 2D FETs using hBN dielectrics. IEDM Tech. Dig. 534 (2015) is shown.

[0066] The prior art values obtained with IGZO and ZnON TFTs on rigid glass substrates was taken from Kim, S. I. et al. High performance oxide thin film transistors with double active layers. IEDM Tech. Dig. 73 (2008); and Kim, T. S. et al. High performance gallium-zinc oxynitride thin film transistors for next-generation display applications. IEDM Tech. Dig. 660 (2013); are also shown for comparison.

[0067] The values obtained with the invention's HfLaO-passivated ZnO TFTs are shown in the last row.

TABLE-US-00001 TABLE 1 Operating Channel Channel layer Gate Insulator SS .sub.EF Voltage Materials thickness (nm) Materials (V/decade) (cm.sup.2/V .Math. s) I.sub.ON/I.sub.OFF (V) Flexible ZnO-Li-H.U. 10 Al2O3 ~32 ~10.sup.8 8 Flexible MoS2- ~2.6 hBN ~40 >10.sup.4 80 Petrone N. Rigid ITO/IGZO- 5/70 SiO.sub.2 ~0.25 104 >10.sup.7 15 Kim S.I Rigid ZnON-Kim T.S. 50 SiN.sub.x/SiO.sub.2 0.8 ~115 >10.sup.6 20 Flexible (This Work) 20 HfO.sub.2/TiO.sub.2/SiO.sub.2 0.103 345 7 10.sup.6 2

[0068] As is shown in Table 1 (last row), the invention's mobility (.sub.EF) value of 345, obtained for the invention's HfLaO-passivated ZnO TFT, is substantially higher than the IGZO and ZnON TFTs on rigid substrates. The invention also produces a record for the highest mobility obtained to date for flexible substrate TFTs.

[0069] Without wishing to be bound by any theory, we believe that this high mobility is possible because poly-crystalline materials typically have better material qualities and higher mobility than corresponding amorphous materials. Indeed the mobility improvement can be as large as 100 times higher for poly-Si TFT, as opposed to amorphous-Si TFTs. In addition to very high mobility, the HfLaO passivated ZnO TFT has many other excellent properties, such as an excellent SS, large I.sub.ON/I.sub.OFF and low V.sub.D. This in turn enables improved devices that use less DC and AC power.

[0070] The invention thus enables improved nano-crystalline ZnO devices, such as TFT devices, that are both simple and inexpensive to manufacture. An important aspect is the invention's techniques for using improved (or proper) passivation to reduce the problem of OH bonding, thus reducing the problem of related charge traps and grain boundary potential barriers. Applications for this invention include improved next generation displays, and also more exotic technologies such as high-speed 3D integrated circuits, such as 3D brain-mimicking chips.

[0071] Methods

[0072] Bottom-gate ZnO/high-/metal-gate TFTs were made on a flexible polyethylene naphthalate (PEN) substrate. In addition to low cost, such PEN substrates have other good properties, such as a low linear thermal expansion coefficient, surface smoothness, and optical clarity.

[0073] To produce the TFT devices discussed here, a 300-nm smoothing SiO.sub.2 layer was first deposited on the PEN substrate. Then various layers such as 60-nm TaN gate metal, tri-layer gate dielectrics of 50-nm HfO.sub.2, 40-nm TiO.sub.2, a 4-nm-SiO.sub.2, and a 20-nm ZnO active layer were deposited using a physical vapor deposition (PVD) process. Then the Al source/drain (S/D) electrodes were formed. Finally, the device was passivated by depositing a 20 nm thick HfLaO dielectric with an opened S/D probing window for more convenient analysis.

[0074] Note that in FIG. 4b, which was designed to allow the ZnO layer to be more easily analyzed, the PEN and 300-nm SiO.sub.2 layers are not shown, and the order of the layers is TaN, SiO.sub.2, TiO.sub.2, HFO.sub.2, and ZnO. The passivation layer is also not shown. [0075] The TaN gate electrode was deposited by sputtering the TaN layer using a power of 800 W, Ar/N.sub.2 of 100/10 sccm, and a pressure of 310.sup.3 torr. [0076] The gate dielectric stacks were deposited by electron-gun evaporation at 5 KV, and the deposition rates were 0.24/0.2/0.1 /sec, respectively. [0077] The ZnO channel was deposited by sputtering at a power of 300 W, Ar/O.sub.2 of 20/5 sccm, and 1 /sec deposition rate. [0078] The Al source-drain was deposited by thermal evaporation deposition. [0079] The HfLaO passivation layer (not shown) was deposited by electron-gun evaporation at a deposition rate of 0.15 /sec. Before deposition, the chambers were pumped down to 310.sup.6 torr.

[0080] We have found that the deposition rates used here was important in order to obtain good quality results. No post-deposition annealing was used. The gate size of the fabricated TFT produced in this study was 48-m505-m.

[0081] To investigate the device's mobility and other material properties, X-ray diffraction (XRD), secondary ion mass spectrometry (SIMS), cross-sectional transmission electron microscopy (TEM), and X-ray photoelectron spectroscopy (XPS) analysis was done.

[0082] Due to the thin 20 nm HfLaO passivation layer, in the XPS measurement, a very low etching rate of 0.2 /sec was used.