Organic light emitting diode display having thin film transistor substrate using oxide semiconductor

Abstract

A method for manufacturing an organic light emitting diode (OLED) display can include forming a gate electrode on a substrate, forming a semiconductor layer by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material, forming an etch stopper on a central portion of the semiconductor layer, conducting a plasma treatment using the etch stopper as a mask to conductorize portions of the semiconductor layer exposed by the etch stopper for defining a channel area, a source area and a drain area, and forming a source electrode contacting portions of the conductorized source area and a drain electrode contacting portions of the conductorized drain area.

Claims

1. A method for manufacturing an organic light emitting diode (OLED) display, the method comprising: forming a gate electrode on a substrate; forming a semiconductor layer having a source area, a drain area and a channel area between the source area and the drain area by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material; forming an etch stopper on the semiconductor layer and the gate insulation layer to expose a portion of the source area and a portion of the drain area of the semiconductor layer; conducting a plasma treatment using the etch stopper as a mask to conductorize the portion of the source area and the portion of the drain area of the semiconductor layer exposed by the etch stopper for defining the channel area, the source area and the drain area; and forming a source electrode contacting the portion of the conductorized source area and a drain electrode contacting the portion of the conductorized drain area, wherein the forming the source electrode and the drain electrode includes: depositing a first metal layer and a second metal layer sequentially on the etch stopper; patterning the second metal layer with an wet etching method; and patterning the first metal layer with a dry etching method using the patterned second metal layer as a mask, wherein the source electrode contacts a surface of the portion of the source area that is apart from the channel area with a first predetermined distance, wherein the drain electrode contacts a surface of the portion of the drain area that is apart from the channel area with a second predetermined distance, and wherein the etch stopper includes a first portion disposed on a portion of the gate insulation layer and a portion of the source area at a position in which the first portion overlaps the gate electrode, a second portion disposed on the channel area at a position in which the second portion overlaps the gate electrode, and a third portion disposed on another portion of the gate insulation layer and a portion of the drain area at a position in which the third portion overlaps the gate electrode.

2. The method according to claim 1, wherein the step of forming the etch stopper includes: depositing an insulating layer on the semiconductor layer; and forming a source area hole exposing the source area and a drain area hole exposing the drain area by patterning the insulating layer using a mask.

3. The method according to claim 1, wherein the first metal layer and the second metal layer of the source and drain electrodes have a same shape and size, respectively.

4. The method according to claim 1, wherein the step of conducting the plasma treatment includes reducing an oxygen content in the exposed portions of the semiconductor layer.

5. The method according to claim 1, wherein the step of conducting the plasma treatment includes aligning a first end of the etch stopper with a boundary between the channel area and the source area and a second end of the etch stopper with a boundary between the channel area and the drain area.

6. The method according to claim 1, wherein the conductorized source and drain areas extend from a top surface of the semiconductor layer to a bottom surface of the semiconductor layer.

7. The method according to claim 1, wherein the source electrode is disposed on the first portion of the etch stopper and the conductorized source area exposed between the first portion of the etch stopper and the second portion of the etch stopper.

8. The method according to claim 7, wherein the drain electrode is disposed on the third portion of the etch stopper and the conductorized drain area exposed between the second portion of the etch stopper and the third portion of the etch stopper.

9. The method according to claim 1, wherein the gate electrode overlaps with the source area and the drain area and extends past outer edges of the source area and the drain area.

10. The method according to claim 1, wherein the first metal layer is thinner than the second metal layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

(2) In the drawings:

(3) FIG. 1 is a diagram illustrating the structure of the organic light emitting diode according to the related art.

(4) FIG. 2 is an exemplary circuit diagram illustrating the structure of one pixel in the active matrix organic light emitting diode display (or AMOLED) according to the related art.

(5) FIG. 3 is a plane view illustrating the structure of one pixel in the AMOLED according to the related art.

(6) FIG. 4 is a cross-sectional view along the cutting line I-I for illustrating the structure of the AMOLED according to the related art.

(7) FIG. 5 is a plane view illustrating the structure of an organic light emitting diode display according to the first embodiment of the present disclosure.

(8) FIG. 6 is a cross-sectional view along the cutting line of II-IP in FIG. 5 for illustrating the structure of an organic light emitting diode display according to the first embodiment of the present disclosure.

(9) FIG. 7 is an enlarged cross-sectional view illustrating the area showing the structure of the driving thin film transistor in FIG. 6 according to the first embodiment of the present disclosure.

(10) FIGS. 8A to 8F are cross-sectional views illustrating a method for manufacturing a thin film transistor substrate according to the first embodiment of the present disclosure.

(11) FIG. 9 is a cross-sectional view illustrating the structure of an organic light emitting diode display according to the second embodiment of the present disclosure.

(12) FIG. 10 is a cross-sectional view along the cutting line of III-III in FIG. 9 for illustrating the structure of an organic light emitting diode display according to the second embodiment of the present disclosure.

(13) FIGS. 11A to 11F are cross-sectional views illustrating a method for manufacturing a thin film transistor substrate for the organic light emitting diode display according to the second embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(14) Referring to attached figures, we will explain preferred embodiments of the present disclosure. Like reference numerals designate like elements throughout the detailed description. However, the present disclosure is not restricted by these embodiments but can be applied to various changes or modifications without changing the technical spirit. In the following embodiments, the names of the elements are selected by considering the easiness for explanation so that they may be different from actual names.

(15) Hereinafter, referring to FIGS. 5 and 6, we will explain about an organic light emitting diode display according to the first embodiment of the present disclosure. FIG. 5 is a plane view illustrating the structure of an organic light emitting diode display according to the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view along the cutting line of II-IP in FIG. 5 for illustrating the structure of an organic light emitting diode display according to the first embodiment of the present disclosure.

(16) Referring to FIGS. 5 and 6, an organic light emitting diode display according to the first embodiment of the present disclosure has gate electrodes SG and DG of the switching thin film transistor ST and the driving thin film transistor DT, respectively, formed on a substrate SUB. On the gate electrodes SG and DG the gate insulator GI is deposited. The semiconductor layers SA and DA are formed on some portions of the gate insulator GI overlapping with the gate electrodes SG and DG. On the semiconductor layers SA and DA, the source electrodes SS and DS and the drain electrodes SD and DD are facing each other respectively with certain distance. The drain electrode SD of the switching thin film transistor ST is connected to the gate electrode DG of the driving thin film transistor DT via the contact hole penetrating the gate insulator GI. The passivation layer PAS is deposited on the substrate SUB having the switching thin film transistor ST and the driving thin film transistor DT.

(17) Especially, when the semiconductor layer SEM is made of oxide semiconductor materials, in order to ensure the stability of the elements, an etch stopper ES may be included for protecting the upper surface of the semiconductor layer SEM from the etchant. In detail, when patterning the source electrodes SS and DS and the drain electrodes SD and DD are formed by a photo-lithography method using an etchant, at the gap area between the source electrode and the drain electrode, the semiconductor layer SEM may be back-etched by the etchant. By forming the etch stopper ES on the upper surface of the channel area of the semiconductor layer SEM, the etch stopper ES can prevent the upper surface of the semiconductor layer SEM at this gap from being etched by the etchant.

(18) In the first embodiment of the present disclosure, the etch stopper ES is formed as covering the whole surface of the substrate SUB having the semiconductor layer SEM is deposited. Further, the etch stopper ES has the open holes for defining the channel areas SA and DA of the semiconductor layer SEM, and the source area SSA and DSA and the drain area SDA and DDA continuously disposed at the right side and the left side of the channel area, respectively. In other words, the exposed area of the semiconductor layer SEM by the open holes of the etch stopper ES may be defined as the source areas SSA and DSA and the drain areas SDA and DDA. The middle portions of the semiconductor layer SEM covered by the etch stopper ES between the source areas SSA and DSA and the drain areas SDA and DDA are defined as the channel areas SA and DA.

(19) Further, in the first embodiment of the present disclosure, the source electrodes SS and DS are connected to some portions of the source areas SSA and DSA, respectively. Therefore, the source electrodes SS and DS are not overlapped with the channel areas SA and DA. Also, the drain electrodes SD and DD are connected to some portions of the drain areas SDA and DDA, respectively.

(20) Color filters CF may be formed at the area where the anode electrode ANO may be formed as a layer. It is preferable that the color filter CF has as large an area as possible. For example, the color filter CF may be overlapped with some portions of the data line DL, the driving current line VDD and the scan line SL. The upper surface of the substrate having these thin film transistors ST and DT and the color filter CF is not in even and/or smooth conditions, but in uneven and/or rugged conditions having different levels. To ensure that the organic light emitting diode display has good luminescent quality over the whole display area, the organic light emitting layer OLE should be formed on an even or smooth surface. So, to make the upper surface in planar and even conditions, the over coat layer OC is deposited on the whole surface of the substrate SUB.

(21) Then, on the over coat layer OC, the anode electrode ANO of the organic light emitting diode OLED is formed. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the contact hole penetrating the over coat layer OC and the passivation layer PAS.

(22) On the substrate SUB having the anode electrode ANO, a bank BANK is formed over the area having the switching thin film transistor ST, the driving thin film transistor DT and the various lines DL, SL and VDD, for defining the light emitting area. The exposed portion of the anode electrode ANO by the bank BANK may be the light emitting area. On the anode electrode ANO exposed from the bank BANK, the organic light emitting layer OLE is formed. On the organic light emitting layer OLE, the cathode electrode ACT is formed.

(23) In the case that the organic light emitting layer OLE includes an organic material emitting white light, each pixel can represent its own color using the color filter CF disposed under the anode electrode ANO. The organic light emitting diode display having the structure shown in FIG. 6 may be the bottom emission type display.

(24) One of the main features of the present disclosure is on the structure of the thin film transistor including an oxide semiconductor material. Hereinafter, referring to FIG. 7, the structure of the thin film transistor in the organic light emitting diode display is described in more detail. FIG. 7 is an enlarged cross-sectional view illustrating the area showing the structure of the driving thin film transistor in FIG. 6 according to the first embodiment of the present disclosure.

(25) Referring to FIG. 7, a gate electrode DG of the driving thin film transistor DT is formed on a substrate SUB. On the gate electrode DG a gate insulating layer GI is deposited. A semiconductor layer SEM is formed on the gate insulating layer GI as being overlapped with the gate electrode DG. On the whole surface of the substrate SUB having the semiconductor layer SEM, an etch stopper ES is deposited.

(26) The etch stopper ES is patterned to expose the source area DSA and the drain area DDA of the semiconductor layer SEM. The exposed source area DSA and the drain area DDA may be conductorized (or metalized) by plasma treatment. As a result, the portions of the semiconductor layer SEM between the source area DSA and the drain area DDA may be defined as the channel area DA.

(27) On the etch stopper ES, a source electrode DS and a drain electrode DD are formed. Especially, the source electrode DS is connected to the source area DSA exposed through the open hole of the etch stopper ES, especially, to some portions of the source area DSA apart from the channel area DA with a predetermined distance. In addition, the drain electrode DD is connected to the drain area DDA exposed through the open hole of the etch stopper ES, especially, to some portions of the drain area DDA apart from the channel area DA with a predetermined distance.

(28) In accordance with one embodiment, the source electrode DS and the drain electrode DD may be made of a double-layered metal layer. For example, a first metal layer M1 may be disposed at the lower layer, and a second metal layer M2 may be disposed at the upper layer. The first metal layer M1 may be easily patterned by the wet etching method, but the second metal layer may be easily patterned by the dry etching method. Further, the data line DL extended from the source electrode DS may have the same structure. Likewise, the drain electrode SD of the switching thin film transistor ST connected to the gate electrode DG of the driving thin film transistor DT may have the same structure.

(29) Under this structure, the channel area DA and the source-drain areas DSA and DDA can be defined by the shape (or profile) of the etch stopper ES. Therefore, the channel area DA has no portion overlapped with the source-drain electrodes DS and DD. As the result, the length of the channel area DA is decided by the pattern of the etch stopper ES, so that it is not required to consider any overlapping margin when designing the thin film transistor. It is possible to accurately design and form the thin film transistor to have a short length of channel by use of the pattern of the etch stopper ES.

(30) Hereinafter, referring to FIGS. 8A to 8F, a method for manufacturing the thin film transistor is described. FIGS. 8A to 8F are cross-sectional views illustrating a method for manufacturing a thin film transistor substrate according to the first embodiment of the present disclosure.

(31) As shown in FIG. 8A, on a transparent substrate SUB, a gate metal material is deposited and patterned in a first mask process to form the gate elements. The gate elements include a gate electrode DG (of the driving thin film transistor DT) and a scan line SL connecting the gate electrode DG. A gate insulating layer GI is deposited on the whole surface of the substrate SUB having the gate elements.

(32) Depositing an oxide semiconductor material on the gate insulating layer GI and patterning in the second mask process, a semiconductor layer SEM is formed. The oxide semiconductor material includes the metal oxide material such as indium-gallium-zinc oxide (or IGZO). The semiconductor layer SEM is formed as overlapping with the gate electrode DG as shown in FIG. 8B.

(33) Depositing an insulating material on the whole surface of the substrate SUB having the semiconductor layer SEM, an etch stopper ES is formed. Patterning the etch stopper ES in the third mask process, a source area hole SH and a drain area hole DH are formed, as shown in FIG. 8C.

(34) After forming the source area hole SH and the drain area hole DH, patterning the etch stopper ES and the gate insulating layer GI in the fourth mask process, a gate contact hole GH exposing some portions of the gate electrode DG is formed. As the manufacturing process explained in the first embodiment is for forming an organic light emitting diode display, the switching thin film transistor ST is connected to the driving thin film transistor DT. Therefore, the gate contact hole GH is required. However, in the method for manufacturing a liquid crystal display in which the gate contact hole is not necessary, this fourth mask process may be omitted.

(35) Using the patterned etch stopper ES as a mask, a plasma treatment is conducted on the whole surface of the substrate SUB. Then, some portions of the semiconductor layer SEM exposed by the source area hole SH and the drain area hole DH penetrating the etch stopper ES are conductorized (or metalized).

(36) The oxide semiconductor material has the characteristics in which the conductivity may be changed according to the content amount of the oxygen therein. The metal oxide semiconductor material such as indium-gallium-zinc oxide used in the semiconductor layer SEM in this application may have the semiconductor characteristics by controlling the content of the oxygen. Here, when reducing the oxygen content, the conductive characteristics may be increased so that the indium-gallium-zinc oxide may be conductorized. There are various methods for reducing the oxygen content during forming the semiconductor layer SEM. In order to reduce the oxygen content within a selected area, the plasma treatment is used. By conducting the plasma treatment on selected portions of the semiconductor layer SEM, the oxygen amount in the selected portions of the semiconductor layer can be removed so that those portions can be conductorized. In the plasma treatment, the helium (He) gas, the hydrogen (H2) gas or the argon (Ar) gas may be used.

(37) The conductorized areas of the semiconductor layer SEM may be defined as the source area DSA and the drain area DDA. At the same time, the portions of the semiconductor layer SEM covered by the etch stopper ES at the area between the source area hole SH and the drain area hole DH is defined as the channel area DA, as shown in FIG. 8D.

(38) On the whole surface of the substrate SUB having the channel area DA and the source-drain area DSA and DDA, a source-drain metal is deposited. In detail, the first metal layer M1 and the second metal layer M2 are sequentially deposited. The first metal layer M1 may include a metal material or a conductive material such as the molybdenum (Mo), the titanium (Ti), the molybdenum-titanium alloy (MoTi) or the indium thin oxide (ITO). The first metal layer M1 may be deposited with the thickness of 1,000 or less. The second metal layer M2 may include a low resistance material such as the copper (Cu). In another example, the second metal layer M2 may include a metal material or a conductive material such as the copper (Cu) alloy, the molybdenum (Mo), the titanium (Ti), the molybdenum-titanium alloy (MoTi) or the indium thin oxide (ITO). The second metal layer M2 may be deposited with the thickness of 6,000 or less. It is preferable that the second metal layer M2 is thicker than the first metal layer M1. However, depending on the cases, the second metal layer M2 may be thinner than the first metal layer M1. In the fifth mask process, the second metal layer M2 is etched by the wet etching process, as the source-drain pattern, as shown in FIG. 8E.

(39) Using the second metal layer M2 patterned in the source-drain shape as a mask, the first metal layer M1 is patterned by the dry etching process. As the result, the source-drain elements are completed. The source-drain elements include the source electrode DS and the drain electrode DD of the driving thin film transistor DT, the source electrode SS and the drain electrode SD of the switching thin film transistor ST, the data line DL and the driving current line VDD.

(40) Especially, the source electrode DS contacts some portions of the source area DSA exposed through the source area hole SH formed at the etch stopper ES. In detail, the source electrode DS contacts some area of the source area DSA with a predetermined distance from the channel area DA to outside. Therefore, other portions of the source area DSA between the source electrode DS and the channel area DA are exposed. In addition, the drain electrode DD also contacts some area of the drain area DDA with a predetermined distance from the channel area DA to the outside. Then, other portions of the drain area DDA between the drain electrode DD and the channel area DA are also exposed, as shown in FIG. 8F.

(41) In the case that the source-drain electrode DS and DD are formed as being overlapped with the etch stopper ES covering the channel area DA, the portions of the semiconductor layer SEM corresponding to the space between the source electrode DS and the drain electrode DD may be defined as the channel area. However, in the first embodiment of the present disclosure, the source-drain electrodes DS and DD are not overlapped with the channel area DA, so that the channel area DA may be exactly and/or precisely defined by the shape or pattern of the etch stopper ES.

(42) As described above, when the source electrode DS and the drain electrode DD contact some portions of the source area DSA and the drain area DDA, respectively, and the other portions of the source area DSA and the drain area DDA are exposed, the exposed portions of the source area DSA and the drain area DDA may be damaged when patterning the source-drain elements. To prevent this damage, in the present disclosure, the source-drain elements include two metal layers. For example, in the wet etching process, the second metal layer M2 of the source-drain element is patterned in a fast takt time. After that, the first metal layer M1 thinner than the second metal layer M2 is patterned in the dry etching process using the patterned second metal layer M2 as a mask. The dry etching process requires longer takt time than the wet etching process, but it can control the etching thickness more precisely. Therefore, by combining the wet etching process and the dry etching process properly, it is possible to form the source-drain element without any damages on the exposed other portions of the source area DSA and the drain area DDA.

(43) Hereinafter, referring to FIGS. 9 and 10, a second embodiment of the present disclosure is described. FIG. 9 is a cross-sectional view illustrating the structure of an organic light emitting diode display according to the second embodiment of the present disclosure. FIG. 10 is a cross-sectional view along the cutting line of III-III in FIG. 9 for illustrating the structure of an organic light emitting diode display according to the second embodiment of the present disclosure.

(44) The basic structure of the organic light emitting diode display according to the second embodiment of the present disclosure is very similar with the first embodiment. Therefore, the explanation about the same structure would be omitted and we will mainly explain on the differences.

(45) In the second embodiment, the channel areas SA and DA and the etch stopper ES is defined and/or formed using the shape of the gate electrodes SG and DG. That is, the channel area of the thin film transistor is defined by the pattern of the gate electrode. In detail, the gate electrode is formed by the designed channel area in the thin film transistor, the etch stopper is formed by the back exposure method using the gate electrode as a mask, and the channel area and the source-drain areas are defined using the etch stopper.

(46) Referring to FIGS. 9 and 10, the organic light emitting diode display according the second embodiment includes a gate electrode SG of the switching thin film transistor ST and a gate electrode DG of the driving thin film transistor DT formed on a substrate SUB. On the gate electrodes SG and DQ a gate insulating layer GI is deposited. On the gate insulating layer GI, a semiconductor layer SEM is formed in which the semiconductor layer SEM includes the channel areas SA and DA having the same shape with the gate electrodes SG and DG, and the source-drain areas SSA-SDA and DSA-DDA extended at both sides of the channel areas SA and DA, respectively.

(47) On the channel areas SA and DA, the etch stopper ES having the same shape with the gate electrodes SG and DG and the channel areas SA and DA is formed. The source-drain areas SSA-SDA and DSA-DDA extended from both sides of the channel areas SA and DA contact the source-drain electrodes SS-SD and DS-DD, respectively. Especially, the source electrodes SS and DS contact some portions of the source areas SSA and DSA, respectively. In detail, the source electrodes SS and DS contact some portions of the source areas SSA and DSA which are apart from the channel areas SA and DA with a predetermined distance to the outside. The drain electrodes SD and DD contact some portions of the drain areas SDA and DDA which are apart from the channel areas SA and DA with a predetermined distance to the outside.

(48) In the second embodiment, the etch stopper ES and the channel areas SA and DA are formed using the shape and/or the profile of the gate electrodes SG and DG. In the first embodiment, the etch stopper ES is deposited on the whole surface of the substrate except the source-drain areas SSA-SDA and DSA-DDA. However, in the second embodiment, the etch stopper ES exists on the channel areas SA and DA only.

(49) Hereinafter, referring to FIGS. 11A to 11F, a method for manufacturing the thin film transistor substrate according to the second embodiment of the present disclosure is described. FIGS. 11A to 11F are cross-sectional views illustrating a method for manufacturing a thin film transistor substrate for the organic light emitting diode display according to the second embodiment of the present disclosure.

(50) As shown in FIG. 11A, on a transparent substrate SUB, a gate metal material is deposited and patterned in a first mask process to form the gate elements. The gate elements include a gate electrode DG (of the driving thin film transistor DT) and a scan line SL connecting the gate electrode DG. It is preferable that the shape of the gate electrode DG is designed as having the same size and shape with those of the channel area DA to be formed later. A gate insulating layer GI is deposited on the whole surface of the substrate SUB having the gate elements.

(51) Depositing an oxide semiconductor material on the gate insulating layer GI and patterning in the second mask process, a semiconductor layer SEM is formed. The oxide semiconductor material includes the metal oxide material such as the indium-gallium-zinc oxide (or IGZO). The semiconductor layer SEM is formed as being larger than the gate electrode as shown in FIG. 11B.

(52) By depositing an insulating material on the whole surface of the substrate SUB having the semiconductor layer SEM, an etch stopper ES is formed. The etch stopper ES is patterned in the third mask process. No any additional photo mask, the etch stopper ES is patterned with the back exposure method using the gate electrode DG as a mask, as shown in FIG. 11C.

(53) After forming the etch stopper ES, by patterning the gate insulating layer GI in the fourth mask process, a gate contact hole GH exposing some portions of the gate electrode DG is formed. Similar to the manufacturing process explained in the first embodiment for forming an organic light emitting diode display, the switching thin film transistor ST is connected to the driving thin film transistor DT. Therefore, the gate contact hole GH is required. However, in the method for manufacturing a liquid crystal display in which the gate contact hole is not necessary, this fourth mask process may be omitted.

(54) By using the patterned etch stopper ES as a mask, a plasma treatment is conducted on the whole surface of the substrate SUB. Then, some portions of the semiconductor layer SEM exposed by the etch stopper ES are conductorized (or metalized). The conductorized areas of the semiconductor layer SEM may be defined as the source area DSA and the drain area DDA. At the same time, the portions of the semiconductor layer SEM covered by the etch stopper ES at the area between the source area DSA and the drain area DDA is defined as the channel area DA, as shown in FIG. 11D.

(55) On the whole surface of the substrate SUB having the channel area DA and the source-drain area DSA and DDA, a source-drain metal is deposited. In detail, the first metal layer M1 and the second metal layer M2 are sequentially deposited. The first metal layer M1 may include a metal material or a conductive material such as the molybdenum (Mo), the titanium (Ti), the molybdenum-titanium alloy (MoTi) or the indium thin oxide (ITO). The first metal layer M1 may be deposited with the thickness of 1,000 or less. The second metal layer M2 may include a low resistance material such as the copper (Cu). In another example, the second metal layer M2 may include a metal material or a conductive material such as the copper (Cu) alloy, the molybdenum (Mo), the titanium (Ti), the molybdenum-titanium alloy (MoTi) or the indium thin oxide (ITO). The second metal layer M2 may be deposited with the thickness of 6,000 or less. It is preferable that the second metal layer M2 is thicker than the first metal layer M1. However, depending on the cases, the second metal layer M2 may be thinner than the first metal layer M1. In the fifth mask process, the second metal layer M2 is etched by the wet etching process, as the source-drain pattern, as shown in FIG. 11E.

(56) By using the second metal layer M2 patterned in the source-drain shape as a mask, the first metal layer M1 is patterned by the dry etching process. As a result, the source-drain elements are completed. The source-drain elements include the source electrode DS and the drain electrode DD of the driving thin film transistor DT, the source electrode SS and the drain electrode SD of the switching thin film transistor ST, the data line DL and the driving current line VDD.

(57) Especially, the source electrode DS contacts some portions of the source area DSA exposed at the one outside direction of the etch stopper ES. In detail, the source electrode DS contacts some area of the source area DSA with a predetermined distance from the channel area DA to outside. Therefore, other portions of the source area DSA between the source electrode DS and the channel area DA are exposed. Further, the drain electrode DD also contacts some area of the drain area DDA exposed at the other outside direction of the etch stopper ES, with a predetermined distance from the channel area DA to the outside. Then, other portions of the drain area DDA between the drain electrode DD and the channel area DA are also exposed, as shown in FIG. 11F.

(58) In the case that the source-drain electrode DS and DD are formed as being overlapped with the etch stopper ES covering the channel area DA, the portions of the semiconductor layer SEM corresponding to the space between the source electrode DS and the drain electrode DD may be defined as the channel area. However, in the second embodiment of the present disclosure, the source-drain electrodes DS and DD are not overlapped with the channel area DA, so that the channel area DA may be exactly and/or precisely defined by the shape or pattern of the etch stopper ES.

(59) Especially, in the second embodiment, the thin film transistor has the self-aligned structure in which the source-drain electrodes DS and DD are not overlapped with the gate electrode DG. Therefore, the parasitic capacitances formed between the gate electrode and the source electrode and/or between the gate electrode and the drain electrode can be minimized or eliminated. Consequently, while the thin film transistor has a bottom gate structure, it has the merit of a top gate structure in which the gate electrode DG and the source-drain electrodes DS and DD are self aligned.

(60) While the embodiment of the present invention has been described in detail with reference to the drawings, it will be understood by those skilled in the art that the invention can be implemented in other specific forms without changing the technical spirit or essential features of the invention. Therefore, it should be noted that the forgoing embodiments are merely illustrative in all aspects and are not to be construed as limiting the invention. The scope of the invention is defined by the appended claims rather than the detailed description of the invention. All changes or modifications or their equivalents made within the meanings and scope of the claims should be construed as falling within the scope of the invention.