POWER SEMICONDUCTOR DEVICE

Abstract

A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein C.sub.gd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating C.sub.gd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

Claims

1. A power semiconductor device, comprising: a P-type substrate, an N-type well region located over the P-type substrate, a P-type body region located on a left side surface of the N-type well region, wherein a first N+ contact region and a first P+ contact region are adjacent and both located on a surface of the P-type body region, an another first N+ contact region is located on a right side surface of the N-type well region, a gate oxide layer is located over the P-type body region and the N-type well region, a polysilicon gate is located over the gate oxide layer, a first oxide layer is located on a surface of the N-type well region, the first N+ contact region and the first P+ contact region are shorted through a source metal, a drain metal is connected to the first N+ contact region on the right side surface of the N-type well region, and a first-type doped region is located on the surface of the N-type well region and below the gate oxide layer.

2. The power semiconductor device according to claim 1, wherein a polysilicon field plate is located over the gate oxide layer between the P-type body region and the first oxide layer; the polysilicon field plate is shorted with the first N+ contact region and the first P+ contact region through the source metal.

3. The power semiconductor device according to claim 1, wherein a right boundary of the P-type body region is flush with a right boundary of the polysilicon gate or exceeds the right boundary of the polysilicon gate.

4. The power semiconductor device according to claim 1, wherein the source metal is directly connected with the gate oxide layer.

5. The power semiconductor device according to claim 1, wherein the first-type doped region is formed jointly by multiple implantations.

6. The power semiconductor device according to claim 1, wherein the first-type doped region is formed by multiple ion implantations with different energies and doses.

7. The power semiconductor device according to claim 1, wherein the first-type doped region comprises a separated first-type doped region formed by two implantations, and a second-type doped region is implanted in a middle of the separated first-type doped region.

8. The power semiconductor device according to claim 7, wherein another first-type doped region is implanted over the first-type doped region formed by the two implantations and the second-type doped region.

9. The power semiconductor device according to claim 6, wherein a P-type well region is implanted on a right side of the first-type doped region, and the first P+ contact region is implanted inside the P-type well region; the first N+ contact region and the first P+ contact region located within the P-type body region are shorted with the first P+ contact region located in the P-type well region through the source metal.

10. The power semiconductor device according to claim 1, wherein a polysilicon field plate is located over the gate oxide layer; the polysilicon field plate is shorted with the first N+ contact region and the first P+ contact region through the source metal.

11. The power semiconductor device according to claim 6, wherein a first buried layer is added inside the P-type body region and below the first N+ contact region and the first P+ contact region.

12. The power semiconductor device according to claim 6, wherein a first polysilicon field plate is provided over the gate oxide layer between the P-type body region and the first oxide layer, and a second polysilicon field plate is provided over the first oxide layer, the first polysilicon field plate and the first polysilicon field plate are shorted with the first N+ contact region and the first P+ contact region through the source metal.

13. The power semiconductor device according to claim 6, wherein a first type drift region inject is provided on a right side of the first-type doped region and below the first oxide layer.

14. The power semiconductor device according to claim 1, wherein the P-type substrate is a bulk silicon substrate or an SOI substrate.

15. The power semiconductor device according to claim 2, wherein a right boundary of the P-type body region is flush with a right boundary of the polysilicon gate or exceeds the right boundary of the polysilicon gate.

16. The power semiconductor device according to claim 2, wherein the first-type doped region is formed jointly by multiple implantations.

17. The power semiconductor device according to claim 8, wherein a P-type well region is implanted on a right side of the first-type doped region, and the first P+ contact region is implanted inside the P-type well region; the first N+ contact region and the first P+ contact region located within the P-type body region are shorted with the first P+ contact region located in the P-type well region through the source metal.

18. The power semiconductor device according to claim 2, wherein the P-type substrate is a bulk silicon substrate or an SOI substrate.

19. The power semiconductor device according to claim 3, wherein the P-type substrate is a bulk silicon substrate or an SOI substrate.

20. The power semiconductor device according to claim 4, wherein the P-type substrate is a bulk silicon substrate or an SOI substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1A is a traditional LDMOS longitudinal cross-sectional view structure.

[0023] FIG. 1B is the capacitance composition diagram of the box portion in FIG. 1A.

[0024] FIG. 2 is a longitudinal cross-sectional view of Embodiment 1 of an integratable semiconductor device provided by the present invention;

[0025] FIG. 3 is a longitudinal cross-sectional view of Embodiment 2 of an integratable semiconductor device provided by the present invention;

[0026] FIG. 4 is a longitudinal cross-sectional view of Embodiment 3 of an integratable semiconductor device provided by the present invention;

[0027] FIG. 5 is a longitudinal cross-sectional view of Embodiment 4 of an integratable semiconductor device provided by the present invention;

[0028] FIG. 6 is a longitudinal cross-sectional view of Embodiment 5 of an integratable semiconductor device provided by the present invention;

[0029] FIG. 7 is a longitudinal cross-sectional view of Embodiment 6 of an integratable semiconductor device provided by the present invention;

[0030] FIG. 8 is a longitudinal cross-sectional view of Embodiment 7 of an integratable semiconductor device provided by the present invention;

[0031] FIG. 9 is a longitudinal cross-sectional view of Embodiment 8 of an integratable semiconductor device provided by the present invention;

[0032] FIG. 10 is a longitudinal cross-sectional view of Embodiment 9 of an integratable semiconductor device provided by the present invention;

[0033] FIG. 11 is a longitudinal cross-sectional view of Embodiment 10 of an integratable semiconductor device provided by the present invention;

[0034] FIG. 12 is a longitudinal cross-sectional view of Embodiment 11 of an integratable semiconductor device provided by the present invention;

[0035] FIG. 13 is a longitudinal cross-sectional view of Embodiment 12 of an integratable semiconductor device provided by the present invention;

[0036] Wherein 1 is a first N+ contact region, 2 is a first P+ contact region, 3 is a p-type body region, 4 is a N-type well region, 5 is a first-type doped region, 6 is a second-type doped region, and 7 is a p-type well region, 8 is a first-type buried layer, 9 is a first-type drift region implantation, 10 is a p-type substrate, 11 is a source metal, 12 is a drain metal, 13 is a first oxide layer, and 14 is a polysilicon gate, 15 is a polysilicon field plate, and 16 is a gate oxide layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Through specific examples of the present invention below, technicians of the field can easily understand other advantages and efficacies of the present invention revealed by the specification. The present invention can also be implemented or applied through other different ways, and the details of the specification can also be modified or changed based on different views and applications without deviating from the spirit of the present invention.

Embodiment 1

[0038] A power semiconductor device provided in this embodiment is shown in FIG. 2:

[0039] Comprising a p-type substrate 10, an N-type well region 4 located over the p-type substrate 10, a p-type body region 3 located on the left side surface of the N-type well region 4, the first N+ contact region 1 and the first P+ contact region 2 are adjacent and both located on the surface of the p-type body area 3, the other first N+ contact region 1 is located on the right side surface of the N-type well region 4, the right side of the gate oxide layer 16 is tangent or not in contact with the left side of the first oxide layer 13, and polysilicon gate 14 is located over the gate oxide layer 16, first oxide layer 13 is located on the surface of the N-type well region 4, the first N+ contact region 1, the first P+ contact region 2 is shorted through source metal 11, drain metal 12 is connected to the first N+ contact region 1 located on the right side surface of the N-type well region 4, and the first-type doped region 5 is located on the surface of the N-type well region 4 and below the gate oxide layer 16. The right boundary of the P-type body region 3 is flush with the right boundary of the polysilicon gate 14. The substrate is a bulk silicon substrate or an SOI substrate.

[0040] The source metal 11 is directly connected to the gate oxide layer 16.

[0041] The advantage of this embodiment is that the robustness of the device against hot carrier effect can be further improved.

Embodiment 2

[0042] As shown in FIG. 3, the difference between this embodiment and embodiment 1 lies in that:

[0043] Polysilicon field plate 15 is located over the gate oxide layer 16 between the p-type body region 3 and the first oxide layer 13; the polysilicon field plate 15 is shorted with the first N+ contact region 1 and the first P+ contact region 2 through the source metal 11.

[0044] The advantage of this embodiment lies in the low difficulty in process realization and better compatibility with traditional processes.

Embodiment 3

[0045] As shown in FIG. 4, the difference between this embodiment and embodiment 2 lies in that: the right boundary of the P-type body region 3 exceeds the right boundary of the polysilicon gate 14.

[0046] In this case, the device can still be an enhanced device and can be turned on smoothly, the advantage of this embodiment is that the input capacitance of the device can be further reduced and the switching frequency can be increased.

Embodiment 4

[0047] As shown in FIG. 5, the difference between this embodiment and embodiment 2 lies in that: the first type doped region 5 is formed jointly by multiple implantations. The advantage of this embodiment is that the adverse effect of the polysilicon field plate 15 on the on-resistance of the device can be further reduced.

Embodiment 5

[0048] As shown in FIG. 6, the difference between this embodiment and embodiment 2 lies in that the first-type doped region 5 is formed by multiple ion implantations with different energies and doses. The advantage of this embodiment is that the adverse effect of the polysilicon field plate 15 on the on-resistance of the device can be further reduced

Embodiment 6

[0049] As shown in FIG. 7, the difference between this embodiment and embodiment 2 lies in that the first-type doped region 5 comprises a separated first-type doped regions 5 formed by two implantations, and a second-type doped region 6 is implanted in the middle of the separated first-type doped regions 5. The advantage of this embodiment is that the adverse effect of the polysilicon field plate 15 on the on-resistance of the device can be further reduced.

Embodiment 7

[0050] As shown in FIG. 8, the difference between this embodiment and embodiment 6 lies in that: implanting another first-type doped region 5 over the first-type doped region 5 formed by two implantations and the second-type doped region 6. The advantage of this embodiment is that the current path can be further optimized and the adverse effect of the polysilicon field plate 15 on the on-resistance of the device can be further reduced.

Embodiment 8

[0051] As shown in FIG. 9, the difference between this embodiment and embodiment 1 lies in that the first-type doped region 5 is formed by multiple ion implantations with different energies and doses. A p-type well region 7 is implanted on the right side of the first type doped region 5, and a first P+ contact region 2 is implanted inside the p-type well region 7; the first N+ contact region 1 and the first P+ contact region 2 located within the p-type body region 3 are shorted with the first P+ contact region 2 located within the p-type well region 7 through the source metal 11.

[0052] The advantage of this embodiment is that the C.sub.gd of the device can be further reduced, and the latch-up resistance of the device can be enhanced.

Embodiment 9

[0053] As shown in FIG. 10, the difference between this embodiment and embodiment 5 lies in that: the polysilicon field plate 15 is located over the gate oxide layer 13; the polysilicon field plate 15 is shorted with the first N+ contact region 1 and the first P+ contact region 2 through the source metal 11.

[0054] The advantage of this embodiment is that the adverse effect of the polysilicon field plate 15 on the on-resistance of the device can be further reduced.

Embodiment 10

[0055] As shown in FIG. 11, the difference between this embodiment and embodiment 5 lies in that: a first buried layer (8) is added inside the p-type body region 3 and below the first N+ contact region 1 and the first P+ contact region 2. The advantage of this embodiment is that it can increase the latch-up resistance of the device.

Embodiment 11

[0056] As shown in FIG. 12, the difference between this embodiment and Embodiment 5 lies in that: a polysilicon field plate 15 is provided over the first oxide layer 13; the two polysilicon field plates 15 are shorted with the first N+ contact region 1 and the first P+ contact region 2 through the source metal 11.

[0057] The advantage of this embodiment is that the robustness of the device against hot carrier effect can be further increased.

Embodiment 12

[0058] As shown in FIG. 13, the difference between this embodiment and embodiment 5 lies in that: a first type drift region implantation 9 is provided on the right side of the first type doped region 5 and below the first oxide layer 13.

[0059] The advantage of this embodiment is that it can further reduce the on-resistance of the device and can increase the robustness of the device against hot carrier effect.

[0060] The above embodiments illustrate only the principles and its efficacies of the present invention, and are not intended to limit the present invention. Modifications and variations can be made to the above-illustrated embodiments without departing from the spirit and scope of the present invention by anyone familiar with the art. Therefore, all equivalent modifications or changes made by those with known to persons of ordinary skill in the technical field without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.