METHOD FOR MANUFACTURING SILICON WAFER AND SILICON WAFER

Abstract

A clean silicon wafer, having a DZ layer free of micro-defects formed in a device active region on the surface of the thermally-processed silicon wafer, an IG layer having a high gettering capability formed in a bulk layer, and little heavy metal contamination on the wafer surface is manufactured. A method for manufacturing a silicon wafer for performing the rapid thermal process for a silicon wafer in a furnace, the method performs the rapid thermal process with a thermal budget of 53% or more and 65% or less, in terms of a thermal budget with temperature and time, when a condition where a thermal process at a highest temperature of 1350? C. is maintained for a predetermined longest holding time is taken as 100% of the thermal budget.

Claims

1. A method for manufacturing a silicon wafer, for performing a rapid thermal process on a silicon wafer in a chamber, the method comprising: in terms of a thermal budget with temperature and time, when a condition where a thermal process at a highest temperature of 1350? C. is maintained for a predetermined longest holding time is taken as 100% of the thermal budget, performing the rapid thermal process with a thermal budget of 53% or more and 65% or less.

2. The method for manufacturing a silicon wafer according to claim 1, wherein an oxygen concentration of the wafer is controlled to be 0.6?10.sup.18 atoms/cm.sup.3 or more and 1.0?10.sup.18 atoms/cm.sup.3 or less (ASTM '79) for the silicon wafer to be used in the rapid thermal process.

3. The method for manufacturing a silicon wafer according to claim 1, wherein, in the thermal process where the highest temperature of 1350? C. is maintained for the predetermined longest time, the predetermined longest holding time is 20 s.

4. A silicon wafer having the number of LSTDs on a surface layer of 0.3 numbers/cm.sup.2 or less, and having a BMD density of a bulk layer is 5?10.sup.10 cm.sup.?3 or more.

5. The silicon wafer according to claim 4, wherein an oxygen concentration of the wafer is 0.6?10.sup.18 atoms/cm.sup.3 or more and 1.0?10.sup.18 atoms/cm.sup.3 or less (ASTM '79).

Description

BRIEF DESCRIPTION OF DRAWINGS

[0020] FIG. 1 is a cross-sectional view illustrating an embodiment of a rapid thermal process device (RTP device) which is applied to a method for manufacturing a silicon wafer according to the present invention.

[0021] FIG. 2 is a graph illustrating an example of a thermal history of a silicon wafer to be applied in the rapid thermal process device (RTP device) in FIG. 1.

[0022] FIG. 3 is a graph illustrating the thermal history under condition No. 1 of an example.

[0023] FIG. 4 is a graph illustrating the thermal history under condition No. 2 of the example.

[0024] FIG. 5 is a graph illustrating the thermal history under condition No. 3 of the example.

[0025] FIG. 6 is a graph illustrating the thermal history under condition No. 4 of the example.

[0026] FIG. 7 is a graph illustrating the thermal history under condition No. 5 of the example.

[0027] FIG. 8 is a graph illustrating the thermal history under condition No. 6 of the example.

[0028] FIG. 9 is a graph illustrating the thermal history under condition No. 7 of the example.

[0029] FIG. 10 is a graph illustrating the thermal history under condition No. 8 of the example.

[0030] FIG. 11 is a graph illustrating the thermal history under condition No. 9 of the example.

[0031] FIG. 12 is a graph illustrating the thermal history under condition No. 10 of the example.

[0032] FIG. 13 is a graph illustrating the thermal history under condition No. 11 of the example.

[0033] FIG. 14 is a graph illustrating the thermal history under condition No. 12 of the example.

[0034] FIG. 15 is a graph illustrating the results of Experiment 1 and Experiment 2 of the example.

[0035] FIG. 16 is a graph illustrating the results of Experiment 3 of the example.

[0036] FIG. 17 is a graph illustrating the results of Experiment 4 and Experiment 5 of the example.

DESCRIPTION OF EMBODIMENTS

[0037] Hereinbelow, preferred embodiments of the present invention will be described based on the drawings. FIG. 1 is a cross-sectional view illustrating an embodiment of a rapid thermal process device (RTP device) which is applied to a method for manufacturing a silicon wafer according to the present invention.

[0038] As illustrated in FIG. 1, an RTP device 1 includes a chamber (reaction tube) 20 provided with an atmospheric gas inlet 20a and an atmospheric gas outlet 20b, a plurality of lamps 30 arranged at a distance from each other in an upper portion of the chamber 20, and a substrate support unit 40 that supports a silicon wafer W in a reaction space 25 in the chamber 20. In addition, a rotation means (not shown) that rotates the silicon wafer W at a predetermined speed around the central axis is provided.

[0039] The substrate support unit 40 includes a ring 10 that supports the outer periphery of the silicon wafer W and a stage 40a that supports the ring 10. The chamber 20 is made of quartz, for example. Each of the lamps 30 is a halogen lamp, for example. The stage 40a is made of quartz, for example. The RTP device 1 can uniformly heat and process the entire silicon wafer W with a temperature gradient of temperature rise and drop of 10 to 300? C./s, and a detailed thermal budget will be described below.

[0040] In the RTP device 1 according to the present embodiment, an average temperature for multiple points is measured (for example, 9 points) in the substrate plane in the substrate radial direction of the backside of the silicon wafer W with a plurality of radiation thermometers embedded in the stage 40a of the substrate support unit 40, and the temperature in the reaction space 25 is controlled by controlling the plurality of halogen lamps 30 (individual ON-OFF control of each of the lamps, control of emission intensity of light to be emitted, and the like) based on the measured temperature.

[0041] Next, a method for manufacturing a silicon wafer according to an embodiment will be described using the RTP device 1 in FIG. 1.

[0042] First, the silicon wafer W is placed and fixed on the ring 10. The ring 10 is fixed to the upper portion of the stage 40a which is installed in the reaction space 25 under an oxidizing atmosphere such that the upper surface of the silicon wafer W is substantially parallel to the upper portion thereof.

[0043] Process gas is introduced from the atmospheric gas inlet 20a, and the gas in the reaction space 25 is exhausted from the atmospheric gas outlet 20b, to form a predetermined airflow over the silicon wafer W.

[0044] Subsequently, the halogen lamps 30 arranged at equal spaces are individually controlled based on the feedback from the plurality of radiation thermometers embedded in the stage 40a, that is, based on the temperature of the backside of the silicon wafer W. Then, the silicon wafer W is heat-processed by rapidly heating the inside of the reaction space 25, while controlling the temperature of the silicon wafer W.

[0045] Here, in the RTP device 1 according to the present embodiment, a state where the thermal process at 1350? C., which is the highest heating temperature, is maintained for 20 s (longest time), for example, is taken as the thermal budget (total quantity of thermal process) of 100%, a rapid thermal process is performed with a thermal budget of 53% or more and 65% or less, for example.

[0046] For example, as illustrated in the graph of FIG. 2, the wafer surface temperature is raised to 1300? C. in 10 s after the start of heating.

[0047] Subsequently, the wafer surface temperature is raised to 1350? C. in 27 to 32 s after the start of heating, and this state is maintained for 0 to 6 s.

[0048] Thereafter, the inside of the furnace is rapidly cooled to complete the rapid thermal process.

[0049] In addition, the silicon wafer used in the rapid thermal process is prepared to have the oxygen concentration of the substrate of 0.6?10.sup.18 atoms/cm.sup.3 or more and 1.0?10.sup.18 atoms/cm.sup.3 or less (ASTM '79).

[0050] In such a rapid thermal process, by raising the heating temperature to 1350? C., COP on the wafer surface can be eliminated, and a DZ layer can be formed. In addition, the concentration of vacancies to be introduced is increased, which makes it possible to obtain a high BMD density enough for the bulk layer to have a sufficiently high gettering capability. In a case where the heating temperature does not reach 1350? C. (the thermal budget is insufficient), void defects remain on the wafer surface layer, and the BMD density of the bulk layer decreases, leading to the lowering of the gettering capability.

[0051] In addition, by not maintaining the heating time at 1350? C. long, which is the highest heating temperature, the FeB concentration measured with the surface photovoltage (SPV) method can be lowered (less than 1?10.sup.9 cm.sup.?3), and the silicon wafer can be kept clean. If the heating time at 1350? C. is too long and the thermal budget is too large, Fe contamination (heavy metal contamination) becomes pronounced, and the heat load on the RTP device 1 increases, which is not preferable because there might be a risk of lamp breakage or the like.

[0052] As described above, according to the embodiment of the present invention, when a case where the heating time at 1350? C., which is the highest heating temperature, for example, is 20 s, is taken as a thermal budget (total quantity of thermal process) of 100% in the rapid thermal process with the RTP device 1, the silicon wafer is subjected to the thermal process with a thermal budget of 53% or more and 65% or less.

[0053] As a result, the thermal process can be completed without damaging the RTP device, and the method allows the manufacturing of a clean silicon wafer, having a DZ layer free of micro-defects formed in a device active region on the surface of the thermally-processed silicon wafer, an IG layer having a high gettering capability formed in a bulk layer, and little heavy metal contamination on the wafer surface.

[0054] In the above embodiment, the highest temperature of 1350? C. is maintained for several seconds, and the preferred ratio of the thermal budget is adjusted. However, the present invention is not limited to this mode, and the ratio of the thermal budget may be adjusted to 53% or more and 65% or less by gradually lowering the temperature without maintaining the highest temperature of 1350? C., for example.

[0055] Further, in the above embodiment, the holding time at the highest temperature is set to 20 s in the rapid thermal process, but the present invention is not limited thereto, and a time longer than 20 s may be set as the highest-temperature holding time.

EXAMPLES

[0056] The method for manufacturing a silicon wafer and the silicon wafer according to the present invention will be further described based on examples. In the present example, the following experiments were performed based on the above embodiment.

Experiment 1

[0057] In Experiment 1, the number of laser scattering tomography defects (LSTD) (micro-defects such as COP detected by laser light scattering) was measured by changing the conditions of the rapid thermal process for the silicon wafer. The silicon wafer used in the rapid thermal process has an oxygen concentration of the substrate of approximately 1.0?10.sup.18 atoms/cm.sup.3 (ASTM '79).

[0058] In condition No. 1, the thermal history as illustrated in FIG. 3 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 20 s. This condition was set to be the thermal budget of 100%.

[0059] In condition No. 2, the thermal history as illustrated in FIG. 4 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 15 s. The thermal budget under this condition was 92.9%.

[0060] In condition No. 3, the thermal history as illustrated in FIG. 5 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 13 s. The thermal budget under this condition was 85.1%.

[0061] In condition No. 4, the thermal history as illustrated in FIG. 6 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 10 s. The thermal budget under this condition was 75.2%.

[0062] In condition No. 5, the thermal history as illustrated in FIG. 7 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 8 s. The thermal budget under this condition was 65.4%.

[0063] In condition No. 6, the thermal history as illustrated in FIG. 8 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 2 s. The thermal budget under this condition was 59.4%.

[0064] In condition No. 7, the thermal history as illustrated in FIG. 9 was employed, the highest temperature was 1350? C., and the highest-temperature holding time was 0.1 s. The thermal budget under this condition was 52.8%.

[0065] In condition No. 8, the thermal history as illustrated in FIG. 10 was employed, the highest temperature was 1340? C., and the highest-temperature holding time was 0.1 s. The thermal budget under this condition was 42.3%.

[0066] In condition No. 9, the thermal history as illustrated in FIG. 11 was employed, the highest temperature was 1330? C., and the highest-temperature holding time was 0.1 s. The thermal budget under this condition was 31.7%.

[0067] In condition No. 10, the thermal history as illustrated in FIG. 12 was employed, the highest temperature was 1320? C., and the highest-temperature holding time was 0.1 s. The thermal budget under this condition was 21.1%.

[0068] In condition No. 11, the thermal history as illustrated in FIG. 13 was employed, the highest temperature was 1310? C., and the highest-temperature holding time was 0.1 s. The thermal budget under this condition was 10.5%.

[0069] In condition No. 12, the thermal history as illustrated in FIG. 14 was employed, the highest temperature was 1300? C., and the highest-temperature holding time was 22 s. The thermal budget under this condition was 0%.

[0070] The graph in FIG. 15 illustrates the results under conditions No. 1 to No. 12. In the graph in FIG. 15, the vertical axis (left-hand side) represents the predicted number of LSTDs (numbers/cm.sup.2), and the horizontal axis represents the condition number.

[0071] As illustrated in this graph, the number of LSTDs has increased with decreasing thermal budget from conditions No. 1 to No. 12. In and after condition No. 8, the number of LSTDs exceeds 0.3 numbers/cm.sup.2, showing worse values. Therefore, it is found that conditions No. 1 to No. 7 are favorable as the thermal process conditions for eliminating the COPS on the wafer surface layer.

Experiment 2

[0072] In Experiment 2, the BMD density of the bulk layer was measured under the same conditions of the rapid thermal process as in Experiment 1.

[0073] The graph in FIG. 15 illustrates the results under conditions No. 1 to No. 12. In the graph in FIG. 15, the vertical axis (right-hand side) represents the BMD density (cm.sup.?3) of the bulk layer, and the horizontal axis represents the condition number.

[0074] As illustrated in this graph, under conditions No. 1 to No. 7, the BMD density of the bulk layer is substantially constant, and a sufficiently high value (5?1010 cm.sup.?3 or more) is obtained.

[0075] However, in and after condition No. 8, the BMD density of the bulk layer has decreased with decreasing thermal budget. The reason for this is that the concentration of vacancies introduced in the rapid thermal process decreases with decreasing thermal budget.

[0076] Therefore, it is found that conditions No. 1 to No. 7 are favorable as the thermal process conditions for the bulk layer to have a sufficiently high gettering capability.

Experiment 3

[0077] In Experiment 3, the FeB concentration of the thermally-processed silicon wafer was measured by the SPV method under the same conditions of the rapid thermal process as in Experiment 1.

[0078] The graph in FIG. 16 illustrates the results under conditions No. 1 to No. 12. In the graph in FIG. 16, the vertical axis represents the FeB concentration (cm.sup.?3), and the horizontal axis represents the condition number.

[0079] As illustrated in this graph, the FeB concentration gradually decreases from conditions No. 1 to No. 8, and in and after condition No. 8, the FeB concentration is equal to or less than the measurement lower limit value. Let the preferable FeB concentration be 1?10.sup.9 cm.sup.?3, the concentration less than this value is obtained under conditions No. 5 to No. 12.

[0080] Therefore, it is found that conditions No. 5 to No. 12 are preferable to process cleanly of the silicon wafers.

[0081] From the results of Experiments 1 to 3 described above, it is found that in a case where the oxygen concentration of the substrate is approximately 1.0?10.sup.18 atoms/cm.sup.3 (ASTM '79), the thermal process conditions under which the COP on the wafer surface layer can be eliminated, the gettering capability of the bulk layer is sufficient, and the silicon wafer can be cleanly processed are conditions No. 5 (thermal budget 65%) to No. 7 (thermal budget 53%).

[0082] In addition, in the range of conditions No. 5 to No. 7, the highest-temperature holding time is not too long, a sufficient thermal budget can be secured, and adverse effects on the RTP device can be suppressed.

Experiment 4

[0083] In Experiment 4, similarly to Experiment 1, the number of micro-defects such as COP detected by laser light scattering (LSTD) was measured by changing the conditions of the rapid thermal process for the silicon wafer.

[0084] In Experiment 4, only the oxygen concentration of the silicon wafer substrate used in the rapid thermal process is different from that in Experiment 1, and the value thereof is approximately 0.6?10.sup.18 atoms/cm.sup.3 (ASTM '79).

[0085] The graph in FIG. 17 illustrates the results under conditions No. 1 to No. 12. In the graph in FIG. 17, the vertical axis (left-hand side) represents the predicted number of LSTDs (numbers/cm.sup.2), and the horizontal axis represents condition numbers.

[0086] As illustrated in this graph, the number of LSTDs is 0.3 numbers/cm.sup.2 or less which is the target value under conditions No. 1 to No. 12.

Experiment 5

[0087] In Experiment 5, the BMD density of the bulk layer was measured under the same conditions of the rapid thermal process as in Experiment 4.

[0088] The graph in FIG. 17 illustrates the results under conditions No. 1 to No. 12. In the graph in FIG. 17, the vertical axis (right-hand side) represents the BMD density (cm.sup.?3) of the bulk layer, and the horizontal axis represents the condition numbers.

[0089] As illustrated in this graph, under conditions No. 1 to No. 7, the BMD density of the bulk layer is substantially constant, and a sufficiently high value (5?10.sup.10 cm.sup.?3 or more) is obtained.

[0090] However, in and after condition No. 8, the BMD density of the bulk layer decreases with decreasing thermal budget.

[0091] Therefore, it is found that conditions No. 1 to No. 7 are favorable as the thermal process conditions for the sufficient gettering capability of the bulk layer.

[0092] From the results of Experiments 4 and 5 described above, even when the oxygen concentration of the substrate is approximately 0.6?10.sup.18 atoms/cm.sup.3 (ASTM '79), it is confirmed that under conditions No. 1 to No. 7, the number of LSTDs in the wafer surface layer can be suppressed and the gettering performance of the bulk layer is sufficient. Therefore, the oxygen concentration of the substrate is desirably 0.6?10.sup.18 atoms/cm.sup.3 or more and 1.0?10.sup.18 atoms/cm.sup.3 or less (ASTM '79).

INDUSTRIAL APPLICABILITY

[0093] As described above, the method for manufacturing a silicon wafer according to the present invention is useful for a silicon wafer requiring high quality and is particularly suitable for rapid thermal processing (RTP) of silicon wafers.

REFERENCE SIGNS LIST

[0094] 1 RTP device [0095] 20 chamber (furnace) [0096] 25 reaction space [0097] 30 halogen lamp (lamp) [0098] 40 substrate support unit [0099] 40a stage [0100] W silicon wafer