Method of Manufacturing and Passivating a Die

Abstract

In an embodiment, a method for manufacturing and passivating a die includes providing the die having an active frontside including a protrusion, the protrusion configured for electrically contacting the die, covering a portion of the protrusion by a passivation tape before applying a passivation layer, applying the passivation layer on all sides of the die including the frontside and its protrusion in one single process, except on the portion covered by the passivation tape and detaching the passivation tape from the covered portion of the protrusion after applying the passivation layer to expose the portion of the protrusion which forms an electrical contact area.

Claims

1.-21. (canceled)

22. A method for manufacturing and passivating a die, the method comprising: providing the die comprising an active frontside having a protrusion, the protrusion configured for electrically contacting the die; covering a portion of the protrusion by a passivation tape before applying a passivation layer; applying the passivation layer on all sides of the die including the frontside and its protrusion in one single process, except on the portion covered by the passivation tape; and detaching the passivation tape from the covered portion of the protrusion after applying the passivation layer to expose the portion of the protrusion which forms an electrical contact area.

23. The method of claim 22, wherein the passivation tape comprises a first base layer having a first adhesive layer thereon.

24. The method of claim 22, wherein the die comprises a semiconductor material.

25. The method of claim 22, wherein the passivation layer is deposited by atomic layer deposition.

26. A wafer level packaging method comprising: providing a wafer comprising an active frontside with several protrusions, which are configured for electrically contacting a die, and a passive backside; singulating the wafer into single dies, each with at least one protrusion; covering a portion of each protrusion by a passivation tape before applying a passivation layer; applying the passivation layer on all sides, including the frontside, the backside and all lateral sides of the singulated dies in one single process, except on the portions covered by the passivation tape; and detaching the passivation tape from the covered portions of the protrusions after applying the passivation layer to expose the portions of the protrusions which form electrical contact areas.

27. The method of claim 26, wherein the passivation tape comprises a first base layer having a first adhesive layer thereon.

28. The method of claim 26, wherein the wafer comprises a semiconductor material.

29. The method of claim 26, wherein the passivation layer is deposited by atomic layer deposition. 3o. (New) The method of claim 26 wherein singulating comprises: partially dicing the wafer into the dies, each with at least one protrusion, from the frontside; laminating a grinding tape to the frontside of the wafer, the grinding tape comprising a second base layer having a second adhesive layer thereon; singulating the dies by grinding the wafer from the backside; and releasing the grinding tape from the singulated dies.

31. The method of claim 3o, wherein the second adhesive layer on the grinding tape is thicker than a first adhesive layer on the passivation tape.

32. The method of claim 3o, wherein a distance between two adjacent dies while applying the passivation layer is kept equal to a width of a dicing street formed by partially dicing.

33. The method of claim 30, further comprising applying a protective layer on the frontside of the wafer before partially dicing.

34. The method of claim 30, wherein the backside is covered with a dicing tape while partially dicing the wafer into the dies from the frontside.

35. The method of claim 34, further comprising detaching tapes by physical methods comprising at least one of UV-exposure or heating.

36. The method of claim 26, wherein the protrusion is a solder bump on the die, and wherein the solder bump is partially covered by the passivation layer while applying the passivation layer.

37. The method of claim 26, wherein the protrusion is a thick film metallization on the die, and wherein the thick film metallization is partially covered by the passivation layer while applying the passivation layer.

38. A die comprising: a passivation layer covering all sides and edges of the die except an electrical contact area on a protrusion, wherein the passivation layer is uniform, continuous and homogeneous on every side.

39. The die of claim 38, wherein the die comprises a MEMS arranged on a semiconductor die.

40. The die of claim 38, wherein a frontside of the die comprises a protective layer and the passivation layer all around the die, wherein the passivation layer is arranged on the protective layer, and wherein materials of the two layers are different from each other.

41. The die of claim 38, wherein the passivation layer is electrically insulating.

42. The die of claim 38, wherein the passivation layer comprises one or more of Al.sub.2O.sub.3, AlN or TiO.sub.2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In the following, the invention will be explained in more detail with reference to accompanied drawings. The drawings show:

[0063] FIG. 1: The frontside of a wafer with an active surface and the backside of the wafer with a passive surface;

[0064] FIG. 2A: a cross-sectional view of a single die with a solder bump for electrical interconnection, before applying a passivation layer;

[0065] FIG. 2B: a cross-sectional view of a single die with a thick film metallization for electrical interconnection, before applying a passivation layer;

[0066] FIG. 3: a top view onto the wafer attached to a dicing tape held by a frame at the backside, after partial-cut dicing;

[0067] FIG. 4: a cross-sectional view of the wafer attached to the dicing tape with the backside, after partial-cut dicing;

[0068] FIG. 5: a cross-sectional view of the wafer attached to a grinding tape with the frontside, before backside grinding;

[0069] FIG. 6: a cross-sectional view of the single dies of the wafer attached to a grinding tape with the frontside, after backside grinding;

[0070] FIG. 7: a cross-sectional view of the single dies attached to a passivation tape with the upper surface of the thick film metallization, before applying the passivation layer;

[0071] FIG. 8: a cross-sectional view of the single dies attached to a passivation tape with the upper surface of the thick film metallization, after applying the passivation layer;

[0072] FIG. 9A: a cross-sectional view of a single die with a solder bump for electrical interconnection, after applying the passivation layer; and

[0073] FIG. 9B: a cross-sectional view of a single die with a thick film metallization for electrical interconnection after applying the passivation layer.

[0074] Similar or apparently identical elements in the figures are marked with the same reference signs. The figures and the proportions in the figures are not scalable.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0075] FIG. 1 shows an embodiment of a wafer 100 which is a semiconductor consisting of Si and has a circular shape which can have any size. The semiconductor wafer 100 comprises an array of semiconductor dies 101. The die borders 102 are indicated by virtual lines. Circuit layers or other electric device structures are applied on the frontside 103 of the wafer or are integrated within the die near the frontside. Thus the frontside 103 is designated as active surface.

[0076] Bond pads 104 are formed on the active surface connected to device structures. Said bond pads serve as electrical contact points between the wafer and any connected circuitry. Protrusions for electrical interconnections are applied on said bond pads.

[0077] The backside 105 of the wafer shown at the bottom part of the figure is free of circuitry. Thus the backside of the wafer may be designated as passive surface. The passive surface 106 may comprise the material of the wafer.

[0078] FIGS. 2a and 2b show sectional views of one single die 101 of the wafer 100. On the semiconductor substrate a protective layer 201 and an interlayer 202 are applied. The protective layer 201 may consist of SiO.sub.2 or Si.sub.3N.sub.4. The protective layer 201 may be deposited by a conventional method like sputtering or CVD. The dielectric protective layer 201 defines the size and position of the electrical contact point between the semiconductor and an applied protrusion on the frontside of the wafer (e.g. solder bump, thick film metallization), which is electrically conductive. For that process an etching process is used in the present embodiment to form an opening exposing at its bottom a bond pad 104 through the protective layer 201. Into the opening an under-bump metallization (UBM) 203 is applied. Thereon a conductive solder bump 204 is formed. The solder bump 204 may be deposited by screen printing, ball bumping or a jetting process.

[0079] Alternatively, the opening may be filled with a thick film metallization 205 deposited by a conventional sputtering and subsequent electroplating process. Both the solder bump 204 and the thick film metallization 205 enable electrical interconnection between the semiconductor die 101 and the electrical device realized by device structures in or on the die and an external circuitry like a printed circuit board (PCB).

[0080] In step a) of an exemplary method a semiconductor wafer as shown in FIG. 1 is provided. A frame 301 is used for holding a tape 303 as shown in figure 3. The tape 303 is formed of a material such as polyethylene or a similarly resilient material. Adhesion of the tape 303 may be supported by applying pressure, vacuum and/or heat. The adhesive layer of the tape 303 may comprise an UV releasable adhesive or any other adhesive that allows a later release of the tape 303. Hence, the tape 303 adheres to the backside 105 of the wafer 100 without forming a permanent bond.

[0081] When the tape 303 is attached to the backside 105 of the wafer 100, the wafer 100 is diced into single dies Dolby sawing dicing streets 302 from the frontside 103. The single dies 101 are only partially divided by the dicing step i), as shown in figure 4. The dicing streets 302 are only partial-cut. On the backside 105 of the wafer a continuous layer 401 of wafer material remains.

[0082] In a third step ii) illustrated in figure 5 a grinding tape 501 is laminated on the frontside of the wafer 100. The grinding tape 501 may also be held by a frame 301. The tape 501 consists of a base layer 501A and an adhesive layer 501B. The thickness of the adhesive layer 501B depends on the thickness of the solder bump 204, thick film metallization 205 or any other protrusion for electrical interconnection. The layer should be executed in such a way that the adhesive layer 501B covers the whole frontside 103 of the wafer 100 comprising the protective layer 201, the protrusions and the later electrical contact areas.

[0083] Next, the adhesive layer of the tape 303 on the backside 105 is detached from the wafer 100. The releasing can be executed by mechanical pressure, heating, UV exposure or a different method depending on the adhesive's properties.

[0084] In step iii) the wafer 100 is divided into singulated dies 101 by grinding since the continuous layer on the backside 401 is ground until it is completely removed as shown in FIG. 6. Thus, the ground backside 601 and lateral sides 602 that have already been exposed by the dicing streets 302 of the dies 101 are completely exposed and accessible from the back side and thus are ready for applying the passivation.

[0085] The described dicing before grinding (DBG) process allows better control of the dicing process, minimum backside chipping and minimum risk of die damage. The grinding tape 501 protects the active surface on the frontside 103 from damage during backside-grinding.

[0086] Once the wafer 100 is ground and the dies 101 are singulated, a specific delamination and lamination process is required to delaminate the grinding tape 501 (step iv) and to laminate a passivation tape 701 (step c) on the frontside 103 of the dies 101, as shown in figure 7. The releasing of the grinding tape 501 can be executed by heating, UV exposure or a different method depending on the adhesive's properties. The passivation tape 701 may be held by a frame 301 and consists of a base layer 701A and an adhesive layer 701B. This passivation tape 701 covers only the later electrical contact areas which shall not be passivated in the following steps. Therefore the adhesive layer 701B of the passivation tape 701 is thinner than the adhesive layer 501B of the grinding tape 501. As an example, the thickness of the adhesive layer 701B of the passivation tape 701 is about 8 μm to 10 μm compared to 20 μm to 60 μm of the adhesive layer 501B of the grinding tape 501.

[0087] After the later electrical contact areas are covered by the tape 701, a passivation layer 801 is deposited by ALD as illustrated in FIG. 8 (step d). By the ALD process all six sides of each die, the frontside 103, the backside 105 and the four lateral sides 602, are passivated at the same time.

[0088] In contrast to other methods, in the described method no expansion of the tapes 501 or 701 in order to enlarge the distance between the lateral sides 602 of the dies 101 is required. Here, such a step is superfluous since passivation by an ALD process allows the deposition of single passivation layers in nanometer scale. By repeatedly applying such mono-layers, layer thicknessness up to μm scale can be achieved. Therefore, neither the small distances between facing lateral sides 602, which are equal to the width of the dicing streets 302, nor the small gaps between the frontside 103 of the die and the tape 701 do hinder uniform deposition of passivation.

[0089] Furthermore, an ALD process has the main advantages of being capable of depositing layers in a low temperature regime with a high uniformity and quality and being capable of covering high aspect ratio topographies with minimum variation of less than 1 nm. Only the ALD process allows a thin-film deposition of passivation layers based on metal nitrides or metal oxides like alumina since the required temperature in a CVD process would be higher than the decomposition temperature of most polymers. In contrast to CVD, ALD can be performed at low temperatures, i.e. around room temperature. CVD for passivation processes is performed at elevated temperatures above 150° C.

[0090] When the deposition of the passivation layer 801 is completed, the passivation tape 701 is detached from the dies 101 (step e). The releasing can be forced by heating, UV exposure or a different method depending on the adhesive's properties. A usual fatigue strength of the first adhesive layer 701B of the passivation tape 701 is about 6 to 8 N/mm.sup.2. When releasing the tape 701 from the dies 101, the passivation layer 801 that is also deposited to the bottom surface of the tape 701 delaminates at the upper edge between the protrusion and the tape 701, since the edge is a weak point of said layer.

[0091] For example, the passivation layer 801 delaminates at the upper edge of a thick film metallization 205 and the tape 701 or at the edge between a solder bump 204 and the tape 701. The exact borderline of the passivation layer 801 can be defined by the thickness of the adhesive layer 701B of the tape 701. A thick adhesive layer 701B covers a large area of the solder bump 204 or of the thick film metallization 205. Thus, on a large area of the solder bump 204 or of the thick film metallization 205 no passivation layer can be deposited. The borderline runs close to the surface of the die.

[0092] On the other hand, a thin adhesive layer 701B covers a comparatively smaller portion of the solder bump 204 or of the thick film metallization 205. Thus, the passivation layer 801 can be deposited on a larger portion of the solder bump 204 or of the thick film metallization 205. In such a way, the size of an electric contact area not covered by the passivation layer 801 can be defined. Hence, this size can be defined exactly.

[0093] The resulting dies 901 and 902 with passivation layer 801 are shown in figure 9A and 9B, wherein the protrusion is a solder bump 204 in FIG. 9A (die 901) or a thick film metallization 205 in FIG. 9B (die 902). The passivation layer 801 is laminated on all sides of the die 101 and ends at the upper edges 903A or 903B of the protrusions 204 or 205. The area not covered by the passivation layer 801 defines the electrical contact area 904.

[0094] The passivation layer 801 may consist of a dielectric material such as alumina (Al.sub.2O.sub.3 ), which allows high electrical insulation. Other possible materials are AlN or a mixture of Al.sub.2O.sub.3 and TiO.sub.2. The exact composition of the passivation layer material depends on external influences, the required material qualities such as electrical resistance, thermal conductivity and temperature resistance and on material costs.

[0095] The passivation layer 801 protects the semiconductor die 101 against external influences such as moisture, chemical contamination or mechanical damages in the following process steps.

[0096] In one embodiment not shown in the figures the semiconductor die may be used for forming a micro-electro-mechanical system (MEMS) device for a variety of applications such as sensing, protection, power electronics, etc.

[0097] In another embodiment not shown in the figures the die may comprise a mineral material. The mineral material may comprise a ceramic. The electric device of the die may be embodied as capacitor, varistor or thermistor.

[0098] In another embodiment not shown in the figures the wafer may comprise a mineral material. The wafer may be divisible in singulated dies. The mineral material may comprise a ceramic. The electric devices of the dies may be embodied as capacitor, varistor or thermistor.

[0099] Although the invention has been illustrated and described in detail by means of the preferred embodiment examples, the present invention is not restricted by the disclosed examples and other variations may be derived by the skilled person without exceeding the scope of protection of the invention.