METHOD OF GROWING NANOSTRUCTURES

Abstract

A method for making one or more nanostructures is disclosed. The method includes depositing a catalyst layer on the substrate; depositing an insulator layer on the catalyst layer; providing a continuous patterned conducting helplayer on the insulator layer; creating via holes through the insulator layer from the conducting helplayer to the catalyst layer; growing the one or more nanostructures on the catalyst layer through the via holes; and selectively removing the conducting helplayer after growing the one or more nanostructure.

Claims

1. A method for making one or more nanostructures on a substrate, the method comprising: depositing a catalyst layer on the substrate; depositing an insulator layer on the catalyst layer; providing a continuous patterned conducting helplayer on the insulator layer; creating via holes through the insulator layer from the conducting helplayer to the catalyst layer; growing the one or more nanostructures on the catalyst layer through the via holes; and selectively removing the conducting helplayer after growing the one or more nanostructures.

2. The method according to claim 1, wherein the conducting helplayer is selectively removed after growing the one or more nanostructures.

3. The method according to claim 1, wherein said step of providing said continuous patterned conducting helplayer comprises the steps of: depositing a continuous conducting helplayer on said insulator layer; and patterning said conducting helplayer.

4. The method according to claim 1, wherein said via holes are created by selectively etching the insulating layer.

5. The method according to claim 1, wherein said conducting helplayer is completely removed.

6. The method according to claim 1, further comprising the step of: etching one of the materials below the conducting helplayer using an etchant with relative selectivity, such that the catalyst and nanostructure layers are working as a mask for further processing.

7. The method according to claim 1, wherein said substrate is conducting.

8. The method according to claim 7, wherein said substrate comprises a metal underlayer at an upper surface thereof, said catalyst layer being deposited on the metal underlayer.

9. A method of making a nanostructure device, comprising the steps of: providing a substrate having an upper surface; depositing a catalyst layer on the upper surface of said substrate; depositing a helplayer on said catalyst layer; selectively removing said helplayer to expose said catalyst layer at at least one intended position for nanostructure growth; growing at least one nanostructure from said catalyst layer at said at least one intended position; and removing said helplayer around said at least one nanostructure.

10. The method according to claim 9, further comprising the step of: removing said helplayer around said at least one nanostructure.

11. The method according to claim 10, wherein said step of removing comprises etching said helplayer using said at least one nanostructure as a mask.

12. The method according to claim 9, further comprising the step of: depositing an additional layer between the helplayer and the catalyst layer.

13. The method according to claim 9, further comprising the step of: patterning said catalyst layer to define said at least one intended position for nanostructure growth.

14. The method according to claim 9, further comprising the step of: depositing a metal layer on top of the grown nanostructures.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIGS. 1A-1E illustrate example configurations for growing nanostructures on substrates.

[0036] FIG. 2 is an SEM (scanning electron microscope) image showing a spark-damaged chip surface.

[0037] FIGS. 3A-3E illustrate an example process for manufacturing the nanostructures in accordance with the technology disclosed in this specification.

[0038] FIGS. 4A-4B and 5A-5B show alternative embodiments of the technology disclosed in this specification.

[0039] FIG. 6 is a flow diagram of an example process for growing nanostructures on (partly) insulating surfaces.

[0040] FIGS. 7A-7B show an example optical waveguide structure manufactured using the technology disclosed in this specification.

[0041] FIGS. 8A-8C illustrate an example process for growing nanostructures through an insulating layer.

[0042] FIGS. 9A-9B are SEM images showing an exemplary device with a patterned metal underlayer, a continuous conducting helplayer and a patterned catalyst layer with grown nanofibers.

[0043] FIG. 10 is an SEM image showing the same exemplary device with the helplayer selectively removed.

[0044] FIGS. 11A-11B are SEM images of exemplary devices with copper as the underlayer, before and after the helplayer removal, respectively.

[0045] FIG. 12 is an SEM image of an exemplary device where microstructures/nanostructures are grown through via holes in an insulating layer.

LIST OF REFERENCE NUMERALS USED HEREIN

[0046] The following is a list of reference numerals found on the drawings of the application, with a description of each. [0047] 100conducting substrate [0048] 102catalyst layer, patterned to support growth of individual nanostructures [0049] 104catalyst layer, patterned to support growth of forests of nanostructures (multiple closely-spaced nanostructures) [0050] 106individual nanostructure [0051] 108forest of nanostructures (multiple closely-spaced nanostructures) [0052] 110insulating substrate [0053] 112continuous metal underlayer [0054] 114patterned metal underlayer on top of an insulator [0055] 116patterned metal underlayer having a top surface that is at the same level as the top surface of the insulating substrate (flat chip after polish) [0056] 118via (vertical interconnect) [0057] 120continuous conducting helplayer [0058] 122residuals of catalyst layer (after self-aligned etching) [0059] 124residuals of conducting helplayer (after self-aligned etching) [0060] 126optional layer [0061] 128substrate for waveguide [0062] 130waveguide material [0063] 132remaining vertical sidewalls of the conducting helplayer [0064] 134patterned conducting helplayer [0065] 136via hole through an insulator [0066] 200Depositing a conducting helplayer [0067] 210Depositing optional additional layers [0068] 220Depositing and patterning a catalyst layer [0069] 230Growing nanostructures [0070] 240Selective and self-aligned removal of helplayer

[0071] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0072] The technology described herein relates to plasma processing, for example, growth of nanostructures (i.e., structures having at least one dimension in the order of nanometers). In some implementations, the technology also applies to processing of structures with feature sizes other than in the nanometer range, for example in the micrometer or millimeter size range.

[0073] Substrate is a designation of any layer or layers on which other layers can be deposited for the growth of nanostructures. Substrates can include semiconductors containing devices or metal layers or insulators. Semiconductors can include doped or undoped silicon, silicon carbide, II-VI or III-V materials (GaAs, InP, InGaAs etc) or semiconducting polymers. A substrate can also be transparent, conducting or insulating materials such as glass or indium-tin-oxide (ITO). A substrate can also include polymer layers or printed circuit boards (PCBs). A substrate does not need to be flat and can contain corrugated structures.

[0074] Metal underlayer can include any metal already present on the top surface of a substrate structure before the helplayer is deposited onto the substrate structure, including exposed metal islands (e.g., interconnects or vias) and/or continuous conducting layers that are disposed between the substrate and an exposed insulator layer on top. A metal underlayer can comprise any metal and/or metal alloy or combinations of different metals from the periodic table, such as Cu, Ti, W, Mo, Pt, Al, Au, Pd, Pt, Ni, Fe, etc. A metal underlayer can also comprise one or more conducting alloys such as TiN, WN, AlN. The metal underlayer can also comprise one or more conducting polymers. The metal underlayer can also comprise any combination of the above conducting materials.

[0075] Catalyst is a metal, alloy or material stack for promoting a chemical reaction. One example catalyst is silicon covered by nickel. The catalyst layer might also include a barrier layer, for example a tungsten layer deposited between a gold layer and the Si/Ni layer on top. A catalyst can be a pure metal such as Ni, Fe, Pt, Pd, or a metal alloy such as NiFe, NiCr, NiAlFe, etc.

[0076] Insulator can be any electrically insulating material such as silicon dioxide, silicon nitride or high-k materials such as HfO, ZrO, etc., aluminum oxide, sintered composites, polymers, resists (for example SU8), different forms of polyamide, ITO, so called low-k materials, or interlayer dielectrics (ILD).

[0077] Deposited means any one or more of evaporated, plated, sputtered, or deposited by chemical vapour deposition (CVD) such as thermal or plasma-enhanced CVD, by molecular beam epitaxy (MBE), by pulsed laser deposition (PLD), or by spin-coating.

[0078] Nanostructure is a structure that has at least one dimension in the order of nanometers. Nanostructures can include nanofibers, nanotubes or nanowires of carbon, GaAs, ZnO, InP, GaN, InGaN, InGaAs, Si, or other materials.

[0079] FIG. 3A shows a partly processed substrate such as a silicon chip. The technology described in this specification is applied to the insulating substrate 110 in order to grow nanostructures on the metal islands formed by interconnects 116 and vias 118 (patterned metal underlayer) embedded in the substrate. The vias 118 and interconnects 116 (patterned metal underlayers) can be manufactured according to standard wafer processing methods, for example, the so-called Damascene process, including etching trenches and depositing metals in the trenches. Chemical mechanical polishing (CMP) can be used to achieve a flat top surface of the substrate and interconnects.

[0080] To manufacture the structures shown in FIG. 3E, a number of steps are performed as shown in FIG. 6. First, a continuous conducting helplayer 120 is deposited (step 200) on the substrate 110 and the patterned metal underlayer 116 and 118 embedded in the substrate 110 to obtain the structure in FIG. 3B. Any electrically conducting material can be used as a helplayer 120. Examples of the conducting materials include any electrically conducting element from the periodic table of elements such as W, Mo etc., conducting alloys such as titanium nitride, semiconductors such as doped silicon, or conducting polymers. The material for the helplayer should be different from the material of the patterned metal underlayer unless a buffer layer separating the metal underlayer and the helplayer is first deposited. In the described example, a tungsten layer was employed as the continuous conducting helplayer 120.

[0081] The thickness of the conducting helplayer can be from about 1 nm to 100 m, and preferably between about 1 nm and 100 nm. In one embodiment, a 50 nm layer of tungsten is used. In some embodiments, only one helplayer is used. However, the technology described herein is not limited to have only a helplayer with a single layer of material, the helplayer can also include multiple layers to improve lift-off, adhesion, etch selectivity or act as an etch stop layer, a seed layer for electroplating or a protection layer. Furthermore, layers for thermal management, for example layers with high or low thermal conductivity such as Peltier materials, can be included.

[0082] The technology described herein can be utilized with a number of different materials as the helplayer. It is important to select helplayer materials and etching parameters so that the nanostructures can be used as a self-aligned mask layer during the etching of the helplayer. The choice of the helplayer material can depend on the material lying beneath the helplayer. The helplayer can also be a catalyst, as the selective removal process can also be used to remove any unwanted catalyst residuals between the grown nanostructures.

[0083] The patterned catalyst layers 102 and/or 104 define where the nanostructures are to be grown. The catalyst can be nickel, iron, platinum, palladium, nickel-silicide, cobalt, molybdenum or alloys thereof, or can be combined with other materials (e.g., silicon). The catalyst can be optional, as the technology described herein can also be applied in a catalyst-free growth process for nanostructures. A patterned catalyst layer including a small catalyst dot 102 will give rise to an individual nanostructure, and a patterned catalyst layer including a large catalyst area 104 will give rise to a forest of nanostructures.

[0084] In order to pattern the catalyst layer (step 220 in FIG. 6), standard etch-back or lift-off processing with resist can be used. UV-light or an electron-beam can be used to pattern the resist layer. Other means can also be used to pattern the resist (or the catalyst directly), such as nanoimprint lithography or laser writing. The catalyst layer can also be patterned with methods that do not use a resist, for example, self-assembled chemical methods. An array of catalyst particles can be formed on the surface using Langmuir-Blodgett films, spinning on a solution with catalyst (nano-) particles onto the wafer or depositing a continuous catalyst film which is transformed to catalyst particles during annealing at elevated temperatures. Several of these techniques can be utilized to grow the catalyst layer on non-flat surfaces and to control the growth site density (number of growth sites per unit area).

[0085] During growth of the nanostructures, the conducting helplayer can be electrically grounded or connected to the potential of the substrate holder, or to some other suitable grounding potential. The nanostructures 106 and/or 108 can be grown in a plasma (step 230 in FIG. 6), typically a DC-plasma. The plasma gases used for nanostructure growth can be any carbon carrying precursor such as acetylene, carbon monoxide, methane, or higher order hydrocarbon, together with other gases such as ammonia, hydrogen, argon, or nitrogen. The growth temperature is preferably less than 800 C. A pressure ranging from about 0.1 to 250 Torr and preferably between about 0.1 to 100 Torr can be used. The plasma current can range from about 10 mA to 100 A, and preferably about 10 mA to 1 A.

[0086] In some implementations, RF-plasma or thermal CVD can be used to grow the nanostructures, and the technology described herein has applications especially for RF-plasmas with a DC-bias. In some implementations, the technology described herein also has application for nanostructures grown in gas-phase (without plasma) and in liquid phase.

[0087] In some implementations according to the technology described herein, after the growth step(s), the conductive helplayer is selectively removed by etching (step 240 in FIG. 6). The etching method and etch gases (for the case of dry etch) or etchants (for the case of wet etch) are chosen depending on the materials of the nanostructures and the conducting helplayer. For example, a helplayer comprising tungsten located under carbon nanofibers can be preferably removed by plasma dry etching using a fluorine-containing plasma. An advantage of this combination is the relative selectivity to the nanostructures and the catalyst particles.

[0088] Other etching methods, such as other anisotropic etch methods, wet (isotropic) etching, pyrolysis, electrochemical etching or photochemical etching, can be used. By using an etch-stop layer, or varying the etch time, a sufficiently strong etching can be carried out. It can be advantageous to choose an etchant or etch gas that has a relative selectivity between the conducting helplayer and the metal underlayer.

[0089] After the removal of the conducting helplayer 120 on specific locations using this self-aligned selective removal process, the final structure will consist of residuals of the conducting helplayer 122 below the residuals of the catalyst layer 124 and nanostructures 106 and/or 108 (see FIG. 3E).

[0090] With the method described herein, it is possible to manufacture individual nanostructures 106 or forests of nanostructures 108 on isolated metal islands 116 or directly on the insulating substrate 110 as indicated in FIG. 3E.

[0091] It is also possible to form the nanostructures if the metal underlayer is not at the same level as the rest of the substrate. FIG. 4A illustrates isolated metal islands 114 deposited on top of an insulating substrate 110. The continuous conducting helplayer 120 is deposited over and covering the substrate surface (step 200), and then a patterned catalyst layer 102 and/or 104 is deposited (step 220) on the continuous conducting helplayer. After the growth of nanostructures (step 230) and the self-aligned selective removal (step 240) of the helplayer, the structure will appear as indicated in FIG. 4B.

[0092] In FIGS. 5A and 5B, a final structure formed by an alternative method is shown. First, the continuous conducting helplayer 120 is deposited throughout the top surface of the substrate (step 200), and then some optional patterned layer 126, for example to permit electrical conduction in the direction perpendicular to the nanostructures, is deposited (step 210) on the helplayer 120. Finally the patterned catalyst 102 and/or 104 is deposited (step 220) on the optional layer or the helplayer. After the growth process (step 230), the helplayer is selectively removed as described in a previous section (step 240). As with other methods described herein, no lithography is necessary after the nanostructure growth. Isolated islands (optional patterned layer 126) with nanostructures 106 and/or 108 on top, and residuals of the helplayer 124 below, are thus manufactured by the method illustrated by FIGS. 5A and 5B.

[0093] In another embodiment, FIGS. 8A-8C illustrate the method of growing nanostructures through via holes created in an insulating material layer deposited on top of catalyst layer. First the catalyst layer 102 and/or 104 is deposited on a conducting substrate 100. The substrate in this case can however be an insulating substrate as well. An insulating layer 110 is then deposited on the substrate and the catalyst layer. A patterned conducting helplayer 134 is then deposited on top of the insulating layer 110. In some implementations, a continuous conducting helplayer can be deposited on top of the insulating layer first and then patterned by various suitable methods. Holes are then created by selectively etching the insulating layer 110 to create via holes 136 to the catalyst layer. Growth of nanostructures is then carried out to form nanostructures 106 and/or 108 on the catalyst layer 102 and/or 104. The patterned conducting helplayer 134 is then selectively removed (step 240 of FIG. 6), i.e., completely removed in this case.

[0094] If required, one of the materials below the conducting helplayer can be etched using an etchant with suitable relative selectivity. For example silicon oxide can be etched using wet or dry etching. Thus the catalyst and nanostructure layers are working as a mask for further processing.

Exemplary Applications

[0095] An important application for the technology described in this specification is for making interconnects and/or thermal elevators in integrated circuits, which, for example, can be used in computing devices. The nanostructures are used to carry heat and electricity inside the integrated circuit chip or to/from the integrate circuit chip. The growth methods and devices used are compatible with current processing standards which involve patterning metals by polishing, and are also compatible with the metals involved. Also, 3-dimensional stacking of integrated circuits (several device layers) can utilize the nanostructures made with the methods described herein as interconnects. For example, a method is described in FIGS. 8A-8C to utilize the present invention to create via hole interconnect structures. FIG. 12 shows an SEM micrograph of a device where carbon nanostructures are grown through via holes in an oxide insulator as an exemplary device manufactured using the technology and methods described herein. In FIG. 12, the bright flat area is the insulating area and in the rest of the area, vertically grown nanostructures are visible.

[0096] Another application is the elimination of parasitic growth. When growing nanostructures on a chip that is only partially covered by a metal underlayer (i.e., by a patterned metal underlayer), there is sometimes a parasitic growth outside the catalyst particles. This can be avoided by using the continuous metal helplayer as described herein.

[0097] The technology described herein can also be used to protect the metal underlayer and other exposed materials from the plasma during the growth of nanostructures. This is particularly important when growing nanostructures on a metal underlayer that is not compatible with the gases used for the nanostructure growth. One example is nanostructure growth on a copper surface using acetylene-containing plasma, as copper and acetylene will react with each other. As the conducting helplayer can act as a diffusion barrier for oxygen or other materials of choice from reaching the metal underlayer, unwanted oxidation/chemical reaction/diffusion can be prevented. For example, an aluminum underlayer (if present) can be protected against oxidation by the helplayer. Furthermore, contaminants (for example metal ions) can also be reduced in the nanostructures produced using the method disclosed herein.

[0098] The technology described herein can also be used for protecting any sensitive electrical devices in the substrate from the high voltage arcs in the plasma during the nanostructure growth. If, after all, there are any arcs in the plasma, the resulting damage will be significantly reduced as all connectors on the substrate surface are shorted together and grounded by the conducting helplayer. This electrostatic discharge (ESD) protection is also important for handling a wafer in the laboratory or for shipping the partly finished wafer to another laboratory.

[0099] The methods described herein can also be used to manufacture thermal bumps on an insulating surface by means of self-aligned removal of the helplayer by plasma etching so that no metal is left except in areas just underneath the nanostructures.

[0100] The technology described herein can also be used to manufacture electrical conducting polymeric films and coatings while making the films optically partially transparent, transparent, or non-transparent. Applications can be, for example, making products such as electrode layers in displays, touch screens, electrostatic dissipation (ESD), and shielding etc.

[0101] Furthermore, the mechanical properties of the nanostructures created as described herein can be utilized to give mechanical stability to insulators, for example. It is then an advantage that no continuous metal underlayer is required, as the conducting helplayer is selectively removed by plasma etching (except just below the nanostructures) in a self-aligned process.

[0102] Thermal interface materials (TIMs), an example of anisotropic conducting films, can be manufactured using the technology described herein. In this case, a layer of nanostructures is embedded in a rubber of polymer designed to help increasing thermal conductivity. The polymer is first spun onto the nanofibers after the helplayer removal, and is then lifted off (with the nanostructures embedded therein). As there is no continuous metal film (since it has been selectively removed) below the polymer film, there is no risk of short-circuiting the different parallel nanostructures in the polymer film.

[0103] The conducting helplayer can also supply all nanostructures with the current necessary for electroplating, electrolessplating, or galvanic plating, if this is the next processing step to deposit a metal such as Au, Cu, Al, Ni, etc.

[0104] Another application is to make chemical probes directly onto partly insulating substrates. This can for example be done directly on a standard silicon integrated circuit.

[0105] The technology described herein can be used to manufacture source, drain and gate metal contact points for a transistor, such as CMOS, Bi-CMOS, Bi-polar, or HEMT etc. Variations of such configuration can be envisaged for particular transistor layouts. Applications also include devices with liquid crystals.

[0106] Some applications take advantage of the property that the helplayer can be removed in one-direction-only, if desired. Using anisotropic etch on an appropriately designed substrate structure will leave the helplayer on the vertical surfaces but remove it from the horizontal surfaces. As shown in FIGS. 7A and 7B, a waveguide material 130 is deposited on a suitable substrate 128. The substrate 128 and the waveguide material 130 are covered by a helplayer 120 on the top surface as well as the side walls. By anisotropic etching, the helplayer on the top surface is selectively removed, leaving the side walls intact. As a result, a structure with individual nanofibers 106 grown on an otherwise transparent top surface and metallized sidewalls 132 is created. This structure is useful as an optical absorber for connecting the absorbed light into a waveguide 130 (which consists of the structure with helplayer coated side walls).

[0107] The technology described herein also provides a way to rework processing methods. This means that processed wafers can be reworked in case of processing problems/failure simply by removing the nanostructures by chemical mechanical polishing (CMP) to remove the nanostructures and start over the process.

[0108] The present technology is applicable for attaching technologies such as ball grid arrays (BGA), flip chip (FC) modules, CSP, WLP, FCOB, TCB etc., IC types, RFID tags, CMOS, BiCMOS, GaAS, HEMT, AlGAAs, MMIC, MCM, LCD, displays, mobile handset, ASIC chips, memory devices, MCU, and integrated passive components etc.

Exemplary Devices

[0109] In order to demonstrate the principle, a patterned gold (under-)layer (with a titanium adhesion-promotion layer below) was formed on an otherwise insulating oxide surface (using standard lithographic techniques). It is not desirable to put the catalyst directly on the patterned metal underlayer, as that would give rise to large plasma-induced damages during the growth. Instead, a tungsten helplayer (50 nm) was sputtered all over the chip surface. Then the patterned catalyst layer (Si 10 nm and Ni 10 nm) was formed (aligned with the patterned metal underlayer) by a standard lift off process. After growth, the structures appear as shown in FIGS. 9A and 9B. In this example, the growth temperature was about 700 C., and the plasma was generated in a mixture of C.sub.2H.sub.2 and NH.sub.3 gases (20 and 100 sccm, respectively) at a pressure of about 4 Torr. The plasma current was set to 20 mA and the growth time was about 60 minutes. In this particular example, the catalyst was patterned such that a film (forest) of nanofibers resulted after the growth process, but individual vertically aligned nanofibers will result if the catalyst regions are made smaller.

[0110] The conducting helplayer was then removed by plasma etching in a fluorine-containing plasma (pressure 10 mTorr, gas flow 20 sccm CF.sub.4), and using endpoint detection in a plasma etch CVD processing chamber.

[0111] The viability of the method can be shown by the SEM pictures taken before the processing (FIGS. 9A and 9B) and after the processing (FIG. 10). The fibers essentially look the same, despite the fact that the helplayer has been removed. Hence a self-aligned selective removal of the helplayer has been achieved, leaving only parts of the helplayer directly below the fibers remaining on the substrate. The complete removal of the helplayer from the rest of the areas was verified by electrical measurements. Minimal parasitic growth is seen outside the isolated metal island. A similar exemplary device with aluminum as the underlayer is shown in FIG. 11A, and with copper as the underlayer in FIG. 11B, respectively.

[0112] Thus the goal of growing nanofibers on a patterned metal underlayer (on an otherwise insulating chip surface) has been achieved without plasma-induced chip damage.

[0113] FIG. 12 shows an SEM micrograph of an exemplary device where carbon nanostructures are grown through via holes in an oxide insulator as an exemplary device manufactured using the technology and methods described herein. In FIG. 12, the bright flat area is the insulating area and in the rest of the area, vertically grown nanostructures are visible. Thus the goal of growing nanofibers through via holes in an insulating layer is achieved.

[0114] The contents of all patents and other references cited to herein are hereby incorporated by reference in their entirety for all purposes.

[0115] While the instant specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombinations. Moreover, although features may be described herein as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.