THIN-FILM CAPACITOR
20180102220 ยท 2018-04-12
Assignee
Inventors
- Hiroshi Takasaki (Tokyo, JP)
- Masahiro Hiraoka (Tokyo, JP)
- Hitoshi Saita (Tokyo, JP)
- Kenichi Yoshida (Tokyo, JP)
Cpc classification
H01G4/40
ELECTRICITY
H01G4/1254
ELECTRICITY
H01G7/06
ELECTRICITY
H01G4/232
ELECTRICITY
H01L28/91
ELECTRICITY
H01G4/33
ELECTRICITY
International classification
H01G4/33
ELECTRICITY
H01G4/40
ELECTRICITY
H01G7/06
ELECTRICITY
Abstract
A thin-film capacitor includes a capacitor section in which electrode layers and dielectric layers are alternately stacked and which includes a hole portion that extends to the electrode layer. In a cross-section which is perpendicular to a stacking surface of the capacitor section and which passes through the hole portion, a side surface of the hole portion extends along a reference line extending in a direction intersecting the stacking surface, the dielectric layer extends up to the reference line toward the hole portion, and a gap is formed between the side surface of the pair electrode layer and the reference line.
Claims
1. A thin-film capacitor comprising: a capacitor section in which electrode layers and dielectric layers are alternately stacked such that at least one dielectric layer is interposed in a stacking direction between a pair of electrode layers, the capacitor section including a hole portion that extends from an uppermost surface of the capacitor section to a lower electrode layer in the stacking direction of the pair of electrode layers, wherein, in a cross-section which is perpendicular to a stacking surface of the capacitor section and which passes through the hole portion, a side surface of the hole portion extends along a reference line extending in a direction intersecting the stacking surface, the at least one dielectric layer extends up to the reference line toward the hole portion, and a gap is formed between the side surface on the hole portion side of at least one of the pair of electrode layers and the reference line.
2. The thin-film capacitor according to claim 1, wherein an area of the gap in the cross-section is equal to or greater than 0.0025 m.sup.2 and equal to or less than 2.5 m.sup.2.
3. The thin-film capacitor according to claim 1, wherein the side surface on the hole portion side of the least one of the pair of electrode layers has a convex shape or a concave shape with respect to the gap.
4. The thin-film capacitor according to claim 1, further comprising a protective layer that is formed of an insulating material and that is disposed in the hole portion along the reference line in the cross-section, wherein the protective layer is not present in the gap.
5. The thin-film capacitor according to claim 1, further comprising a protective layer that is formed of an insulating material and that is disposed in the hole portion along the reference line in the cross-section, wherein the protective layer is present also in the gap.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0012]
[0013]
[0014]
[0015]
DETAILED DESCRIPTION
[0016] Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings. In the drawings, the same elements will be referenced by the same reference signs as much as possible. Dimension ratios in elements and between elements in the drawings are arbitrarily set for the purpose of easy understanding of the drawings.
First Embodiment
[0017] A thin-film capacitor according to a first embodiment of the invention will be described below.
[0018] The capacitor section 10 is formed by alternately stacking electrode layers and dielectric layers. That is, a lower electrode layer 1, a dielectric layer 2, an internal electrode layer 3, a dielectric layer 4, an internal electrode layer 5, a dielectric layer 6, and an upper electrode layer 7 are stacked in this order to constitute the capacitor section 10. The dielectric layer 2 is interposed in the stacking direction between the lower electrode layer 1 and the internal electrode layer 3 to constitute a capacitor. Similarly, the dielectric layer 4 is interposed in the stacking direction between the internal electrode layers 3 and 5 to constitute a capacitor, and the dielectric layer 6 is interposed in the stacking direction between the internal electrode layer 5 and the upper electrode layer 7 to constitute a capacitor.
[0019]
[0020] The lower electrode layer 1, the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 are formed of a conductive material and are formed of, for example, a metal material such as Ni, Pt, Pd, Cu, Cr, Ti, W, Al, or alloy of two or more thereof. Thicknesses of the lower electrode layer 1, the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 in the stacking direction of the capacitor section 10 can be set to be, for example, equal to or greater than 50 nm and equal to or less than 1000 nm.
[0021] The dielectric layers 2, 4, and 6 are formed of a (ferroelectric) dielectric material having a perovskite structure such as BaTiO.sub.3 (barium titanate), (Ba.sub.1-XSr.sub.X)TiO.sub.3 (barium strontium titanate), (Ba.sub.1-XCa.sub.X)TiO.sub.3, PbTiO.sub.3, or Pb(Zr.sub.XTi.sub.1-X)O.sub.3, a complex perovskite relaxer type ferroelectric material such as Pb(Mg.sub.1/.sub.3Nb.sub.2/3)O.sub.3, a bismuth-layered compound such as Bi.sub.4Ti.sub.3O.sub.12 or SrBi.sub.2Ta.sub.2O.sub.9, a tungsten-bronze type ferroelectric material such as (Sr.sub.1-XBa.sub.X)Nb.sub.2O.sub.6 or PbNb.sub.2O.sub.6, or the like. Here, in the perovskite structure, the complex perovskite relaxer type ferroelectric material, the bismuth-layered compound, and the tungsten-bronze type ferroelectric material, a ratio of A site and B site is normally an integer ratio, but may be intentionally deviated from the integer ratio for the purpose of improvement in characteristics. In order to control characteristics of the dielectric layers 2, 4, and 6, additives may be appropriately added as a secondary component to the dielectric layers 2, 4, and 6. Thicknesses of the dielectric layers 2, 4, and 6 in the stacking direction of the capacitor section 10 can be set to be, for example, equal to or greater than 50 nm and equal to or less than 1000 nm.
[0022] The detailed configuration of the capacitor section 10 will be described below with reference to
[0023] The hole portion 11 extends from an uppermost surface of the capacitor section 10 (a surface 7S of the upper electrode layer 7 in this embodiment) to the internal electrode layer 5 in the stacking direction of the capacitor section 10. The hole portion 12 extends from the surface 7S of the upper electrode layer 7 to the internal electrode layer 3 in the stacking direction of the capacitor section 10. The hole portions 13 and 14 extend from the surface 7S of the upper electrode layer 7 to the lower electrode layer 1 in the stacking direction of the capacitor section 10.
[0024] The hole portions 11, 12, 13, and 14 have, for example, an inverted truncated cone shape or a cylindrical shape of which a center axis is parallel to the stacking direction of the capacitor section 10. When the hole portions 11, 12, 13, and 14 have such a shape,
[0025] As illustrated in
[0026] In the cross-section, the reference lines S1, S2, S3, S4, S5, and S6 have a substantially straight line shape. Angles S1, S2, S3, S4, S5, and S6 formed by the reference lines S1, S2, S3, S4, S5, and S6 and the stacking surface P are 90 degrees or acute angles and can be set to be, for example, equal to or greater than 15 degrees and equal to or less than 90 degrees. All the angles S1, S2, S3, S4, S5, and S6 may be the same angle or some or all thereof may be different angles.
[0027] It is preferable that the angles S1, S2, S3, S4, S5, and S6 be substantially 90 degrees. This is because an opposite area of each layer of the capacitor section 10 can be kept large and capacitance of the capacitor section 10 becomes large.
[0028] As illustrated in
[0029] Paying attention to the hole portion 11, since the upper electrode layer 7 extends to short of the reference line S2 and the reference line S3 in the direction of the stacking surface P toward the hole portion 11, gaps G7 are formed between two side surfaces 7e on the hole portion 11 side of the upper electrode layer 7 and the reference lines S2 and S3. Paying attention to the hole portion 12, since the internal electrode layer 5 and the upper electrode layer 7 extend to short of the reference line S4 and the reference line S5 in the direction of the stacking surface P toward the hole portion 12, gaps G5 are formed between two side surfaces 5e on the hole portion 12 side of the internal electrode layer 5 and the reference lines S4 and S5, and gaps G7 are formed between two side surfaces 7e on. the hole portion 12 side of the upper electrode layer 7 and the reference lines S4 and S5.
[0030] Paying attention to the hole portion 13 and the hole portion 14, since the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 extend to short of the reference line S1 and the reference line S6 in the direction of the stacking surface P toward the hole portion 13 and the hole portion 14, gaps G3 are formed between two side surfaces 3e on the hole portion 13 side and the hole portion 14 side of the internal electrode layer 3 and the reference lines S1 and S6, gaps G5 are formed between two side surfaces 5e on the hole portion 13 side and the hole portion 14 side of the internal electrode layer 5 and the reference lines S1 and S6, and gaps G7 are formed between two side surfaces 7e on the hole portion 13 side and the hole portion 14 side of the upper electrode layer 7 and the reference lines S1 and S6.
[0031] In this embodiment, in the cross-section illustrated in
[0032] Such maximum distances may be substantially the same distances or some or all thereof may be different distances. It is preferable that the maximum recessed quantity of the side surface 7e of the upper electrode layer 7 be greater than the maximum recessed quantities of the side surfaces 5e and 3e of the internal electrode layer 5 and the internal electrode layer 3. This is because, since a current generation part which can be easily formed in a dielectric material due to electrostriction is separated from an end of the dielectric layer which is structurally vulnerable due to the recession, an effect capable of further decreasing a probability of occurrence of short-circuiting of the electrode layers can be achieved and this effect is remarkable particularly on the upper electrode layer 7 side in which concentration or an electric field can be easily caused due to a tip effect in the capacitor section 10.
[0033] Other elements of the thin-film capacitor 100 will be described below with reference to
[0034] In the protective layer 21, the parts covering the areas of the capacitor section 10 adjacent to the side surfaces of the hole portions 11, 12, 13, and 14 extend along the reference lines S2, S3, S4, S5, and S6. The protective layer 21 is formed of an insulating material such as SiO.sub.2, may be formed of the same material as one of the dielectric layers 2, 4, and 6, or may be formed of another material. The thickness of the protective layer 21 may be set to be, for example, equal to or greater than 0.05 m and equal to or less than 5 m.
[0035] The insulating layer 25 is formed to bury the capacitor section 10 and the protective layer 21. The insulating layer 25 is formed of an insulating material such as an epoxy resin, a polyimide resin, or a phenol resin. The top surface of the insulating layer 25 is substantially flat. In this embodiment, the protective layer 21 is not disposed in the gaps G3, G5, and G7.
[0036] On the insulating layer 25, the drawing electrodes 31 and 33 are disposed separated from each other in the direction of the stacking surface P. The drawing electrodes 31 and 33 are formed of a conductive material and are formed of, for example, a metal material such as Ni, Pt, Pd, Cu, Cr, Ti, W, Al, or alloy of two thereof.
[0037] The drawing electrode 31 is electrically connected to the lower electrode layer 1 and the internal electrode layer 5. Specifically, a part of the drawing electrode 31 is disposed in the hole portion 13 to extend in the stacking direction of the capacitor section 10, and the part comes in contact with the lower electrode layer 1 via a through-hole k1 disposed in the insulating layer 25 and a through-hole h1 disposed in the protective layer 21. Another part of the drawing electrode 31 is disposed in the hole portion 11 to extend in the stacking direction of the capacitor section 10, and the part comes in contact with the internal electrode layer 5 via a through-hole k5 disposed in the insulating layer 25 and a through-hole h5 disposed in the protective layer 21.
[0038] The drawing electrode 33 is electrically connected to the internal electrode layer 3 and the upper electrode layer 7. Specifically, a part of the drawing electrode 33 is disposed in the hole portion 12 to extend in the stacking direction of the capacitor section 10, and the part comes in contact with the internal electrode layer 3 via a through-hole k3 disposed in the insulating layer 25 and a through-hole h3 disposed in the protective layer 21. Another part of the drawing electrode 33 is disposed on the upper electrode layer 7 to extend in the stacking direction of the capacitor section 10, and the part comes in contact with the upper electrode layer 7 via a through-hole k7 disposed in the insulating layer 25 and a through-hole h7 disposed in the protective layer 21.
[0039] An example of a method of manufacturing the thin-film capacitor 100 according to this embodiment will be described below. In manufacturing the thin-film capacitor 100, for example, first, the dielectric layer 2, the internal electrode layer 3, the dielectric layer 4, the internal electrode layer 5, the dielectric layer 6, and a layer which will become the upper electrode layer 7 are stacked in this order on a metal foil which will become the lower electrode layer 1, for example, using a sputtering method to form a stacked body which will be the capacitor section 10 (a stacked body forming step). Instead of this step, the lower electrode layer 1, the dielectric layer 2, the internal electrode layer 3, the dielectric layer 4, the internal electrode layer 5, the dielectric layer 6, and a layer which will become the upper electrode layer 7 may be stacked in this order on a substrate, for example, using a sputtering method to form a stacked body which will be the capacitor section 10.
[0040] Then, the hole portion 11 is formed in the stacked body by covering an area other than the area of the surface of the stacked body corresponding to the hole portion 11 with a mask and then dry-etching the stacked body. Subsequently, through the same step, the hole portions 12, 13, and 14 are formed in the stacked body (a hole portion forming step). Subsequently, the protective layer 21 is formed substantially along the shape of the stacked body to cover the stacked body, for example, using a plasma CVD method (a protective layer forming step).
[0041] Then, a process of baking the stacked body (for example, at 875 C. for about one hour) is performed to crystallize the layers constituting the stacked body (a baking step). Accordingly, the capacitor section 10 is formed. At the time of sintering, the gaps G3, G5, and G7 are formed by reducing the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 more than the dielectric layers 2, 4, and 6.
[0042] By appropriately selecting conditions of the sintering process (such as a sintering temperature, a temperature rising rate, and a temperature falling rate) and types of the materials constituting the layers of the capacitor section 10, the sizes of the gaps G3, G5, and G7 and the shapes of the side surfaces 3e, 5e, and 7e of the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 can be controlled, In general, as the temperature rising rate in the sintering process becomes lower, the gaps G3, G5, and G7 can become larger.
[0043] After the baking process, the insulating layer 25 is formed to bury the capacitor section 10 and the protective layer 21, for example, using a spin coating method. (an insulating layer forming step). Then, the insulating layer 25 and the protective layer 21 are etched to form the through-holes k1, k3, k5, and k7, and the through-holes h1, h3, h5, and h7 (a through-hole forming step), for example, using a reactive ion etching method, the drawing electrode 31 and the drawing electrode 33 are formed, for example, using a plating method (a drawing electrode forming step), and the resultant structure is divided into individual elements by dicing if necessary, whereby the thin-film capacitor 100 is completed.
[0044] According to the thin-film capacitor 100 according to this embodiment, since the gaps G3, G5, and G7 are formed between the side surfaces 3e, 5e, and 7e on the hole portions 11, 12, 13, and 14 side of the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 and the reference lines S1, S2, S3, S4, S5, and S6 (see
[0045] In the thin-film capacitor 100 according to this embodiment, it is preferable that the areas of the gaps G3, G5, and G7 in the cross-section illustrated in
[0046] In the thin-film capacitor 100 according to this embodiment, since the side surfaces 3e, 5e, and 7e of the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 have a convex shape with respect to the corresponding hole portions 11, 12, 13, and 14 (see
[0047] The thin-film capacitor according to this embodiment further includes the protective layer 21 including parts that are disposed in the hole portions 11, 12, 13, and 14 along the reference lines S1, S2, S3, S4, S5, and S6 in the cross-section illustrated in
Second Embodiment
[0048] A thin-film capacitor according to a second embodiment of the invention will be described below.
[0049] A thin-film capacitor 200 according to this embodiment illustrated in
[0050] A method of manufacturing the thin-film capacitor 200 according to this embodiment is the same as the method of manufacturing the thin-film capacitor 100 according to the first embodiment, except that the protective layer forming step and the baking step are reversed in order. That is, the thin-film capacitor 200 according to this embodiment can be manufactured by performing the steps of the method of manufacturing the thin-film capacitor 100 according to the first embodiments in the order of the stacked body forming step, the hole portion forming step, the baking step, the protective layer forming step, the insulating layer forming step, and the drawing electrode forming step.
[0051] According to the thin-film capacitor 200 according to this embodiment, it is possible to prevent a pair of electrode layers interposing the dielectric layer therebetween in the stacking direction from short-circuiting for the same reason as in the thin-film capacitor 100 according to the first embodiment.
[0052] According to the thin-film capacitor 200 according to this embodiment, since the side surfaces of the dielectric layers 2, 4, and 6, the lower electrode layer 1, the internal electrode layers 3 and 5, and the upper electrode layer 7 adjacent to the hole portions 11, 12, 13, and 14 are protected by the protective layer 23, it is possible to further prevent a pair of electrode layers interposing the dielectric layer therebetween in the stacking direction from short-circuiting. Since the protective layer 23 is present in the gaps G3, G5, and G7, it is possible to prevent the end portions of the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 from being deformed due to insufficient support of the end portions in the gaps G3, G5, and G7.
[0053] The invention is not limited to the above-mentioned embodiments, and can be modified in various forms.
[0054] For example, in the thin-film capacitor 100 according to the first embodiment and the thin-film capacitor 200 according to the second embodiment, the side surfaces 3e, 5e, and 7e of the internal electrode layer 3, the internal electrode layer 5, and the upper electrode layer 7 have a convex shape with respect to the corresponding hole portions 11, 12, 13, and 14 (see
[0055]
[0056] The side surface 3e of the internal electrode layer 3 and the side surface 7e of the upper electrode layer 7 may similarly have various shapes as illustrated in
[0057] In the thin-film capacitor 100 according to the first embodiment and the thin-film capacitor 200 according to the second embodiment, the gaps G3, G5, and (17 are formed in the cross-section satisfying the conditions that the cross-section is perpendicular to the stacking surface of the capacitor section 10 and passes through the hole portions 11, 12, 13, and 14 (see
[0058] In the thin-film capacitor 100 according to the first embodiment and the thin-film capacitor 200 according to the second embodiment may not include the protective layer 21 arid the protective layer 23. In this case, the areas in which the protective layer 21 and the protective layer 23 are formed may be occupied by the insulating layer 25.
[0059] The protective layer 23 of the thin-film capacitor 200 according to the second embodiment is disposed in the gaps to occupy all the gaps G3, G5, and G7 (see