Insulated trench gates with multiple layers for improved performance of semiconductor devices

Abstract

Trenches having a gate oxide layer are formed in the surface of a silicon wafer for vertical gates. Conductive doped polysilicon is then deposited in the trenches to form a relatively thin layer of doped polysilicon along the sidewalls. Thus, there is a central cavity surrounded by polysilicon. Next, the cavity is filled in with a much higher conductivity material, such as aluminum, copper, a metal silicide, or other conductor to greatly reduce the overall resistivity of the trenched gates. The thin polysilicon forms an excellent barrier to protect the gate oxide from diffusion from the inner conductor atoms. The inner conductor and the polysilicon conduct the gate voltage in parallel to lower the resistance of the gates, which increases the switching speed of the device. In another embodiment, a metal silicide is used as the first layer, and a metal fills the cavity.

Claims

1. A semiconductor, insulated trench gate device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a trench formed in at least the first semiconductor layer, the trench having sidewalls; an oxide layer on the sidewalls; a first conductive material in the trench abutting the oxide layer, wherein the first conductive material extends above the trench, wherein the first conductive material comprises doped polysilicon; a conductive gate contact material directly contacting an exposed top of the first conductive material, the conductive gate contact material comprising a metal; oxide sidewall spacers along exposed sides of at least the conductive gate contact material, wherein a top of the conductive gate contact material is level with a top of the oxide sidewall spacers; and doped source regions, the source regions comprising a first portion and a second portion, the first portion abutting the trench and having a first depth below a top surface of the first semiconductor layer, the second portion being self-aligned with the oxide sidewall spacers and being spaced away from the trench, the second portion having a second depth, greater than the first depth, below the top surface of the first semiconductor layer, wherein the device forms an npnp layered structure.

2. The device of claim 1 wherein the trench is within a cellular array of trenches.

3. A semiconductor, insulated trench gate device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a trench formed in at least the first semiconductor layer, the trench having sidewalls; an oxide layer on the sidewalls; a first conductive material in the trench abutting the oxide layer, wherein the first conductive material extends above the trench, wherein the first conductive material comprises doped polysilicon; a conductive gate contact material directly contacting an exposed top of the first conductive material, the conductive gate contact material comprising a metal; oxide sidewall spacers along exposed sides of at least the conductive gate contact material, wherein a top of the conductive gate contact material is level with a top of the oxide sidewall spacers; and doped source regions, the source regions comprising a first portion and a second portion, the first portion abutting the trench and having a first depth below a top surface of the first semiconductor layer, the second portion being self-aligned with the oxide sidewall spacers and being spaced away from the trench, the second portion having a second depth, greater than the first depth, below the top surface of the first semiconductor layer, wherein the trench is within a cellular array of trenches.

4. The device of claim 3 wherein the device comprises a MOSFET.

5. The device of claim 3 wherein the device comprises an insulated-gate power device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is copied from Applicant's U.S. Pat. No. 8,878,238 and is a cross-section of a vertical switch having an insulated trench gates connected in parallel.

(2) FIG. 2 is a cross-section of an insulated trench gate, in accordance with one embodiment of the invention, in any vertical or lateral semiconductor device, such as the power device of FIG. 1, an IGBT, a MOSFET, a thyristor, etc., where the overall conductivity of the gate is lower compared to a doped polysilicon gate by using two different gate materials.

(3) FIG. 3 illustrates another embodiment of an insulated trench gate, where two different gate materials are used in the insulated trench gate.

(4) FIG. 4 illustrates another embodiment of an insulated trench gate, where two different gate materials are used in the insulated trench gate.

(5) FIG. 5 illustrates another embodiment of an insulated trench gate, where three different gate materials are used in the insulated trench gate.

(6) FIG. 6 illustrates another embodiment of an insulated trench gate, where the top of the insulated trench gate is a higher conductivity material.

(7) FIG. 7 illustrates another embodiment of an insulated trench gate, where the gate material extends above the trench, and the top and exposed sides of the gate material is contacted by a highly conductive material for a very low resistance contact to the gate material.

(8) FIG. 8 illustrates another embodiment of an insulated trench gate, where oxide sidewall spacers are used to self-align and control the shape of the source contact region.

(9) FIG. 9 illustrates the power device of FIG. 1 but includes any of the new gate structures described herein.

(10) Elements that are the same or equivalent in the various figures may be labeled with the same numeral.

DETAILED DESCRIPTION

(11) FIG. 2 is a cross-section of an insulated trench gate in a silicon wafer, in accordance with one embodiment of the invention, in any vertical or lateral semiconductor device, such as the power device of FIG. 1, an IGBT, a MOSFET, a thyristor, etc.

(12) An n-type drain layer 14 can also be the n drift layer 106 in FIG. 1 or any suitable layer in a vertical or lateral gate-controlled device. Above the drain layer 14 is a p layer 16 that forms a channel region abutting the insulated trench gate 18. Above the p-layer 16 are n+ source regions 20 that are connected to a metal source (or cathode) electrode 22. An oxide layer 24 insulates the gate 18 from the electrode 22. The anode electrode (not shown) may be on the bottom or top of the die.

(13) A trench 26 is etched through the various layers using a mask and RIE.

(14) The resulting wafer is then heated in an oxygen atmosphere to grow a thin gate oxide 28 on the walls of the trench 26.

(15) A CVD process is then conducted to deposit doped polysilicon 30 over the gate oxide 28. The Si atoms in the doped polysilicon 30 deposit on the gate oxide 28, and the polysilicon grows outward. After a thin layer of polysilicon is grown, the CVD process is stopped so that there is a middle cavity in the polysilicon 30.

(16) A metal silicide 32, such as WSi2, or other conductive silicide, is then deposited in the cavity, such as by CVD. The silicide 32 is more conductive than the doped polysilicon 30, but the polysilicon 30 provides a good barrier against diffusion of the metal atoms into the gate oxide 28. Diffusion of metal atoms into the gate oxide 28 would change the threshold voltage and possibly cause the gate oxide 28 to be conductive.

(17) Any excess gate material is etched away during an etching step for that particular material.

(18) The top of the resulting gate 18 is electrically connected to a metal gate pad outside of the cross-section. The electrical connection between any gate and the gate pad may be via the distributed polysilicon and silicide gate materials forming the array of gates. Thus, gates closest to the gate pad and gates farthest from the gate pad will both have a very low resistance path to the gate pad. Lowering the overall gate resistance is important for all regions of the array of gates to be at substantially the same voltage.

(19) In the example of FIG. 2, biasing the gate 18 sufficiently positive with respect to the source regions 20 (i.e., exceeding a threshold voltage), inverts the p-layer 16 abutting the trench 26 to cause a conductive channel to form between the source regions 20 and the drain layer 14, assuming the source electrode 22 is positively biased with respect to the drain. A metal drain electrode (not shown) is formed on the bottom or top surface of the die, which may use an n+substrate. It is also known to use a p+ substrate to form an npnp layered structure.

(20) The insulated trench gates may be part of a cellular structure, where each cell conducts substantially the same current, and the cells are connected in parallel.

(21) Accordingly, the overall conductivity of the insulated trench gate is lower compared to a doped polysilicon gate by using two different gate materials, which improves efficiency, lowers threshold voltages, lowers die temperature, and improves switching speed.

(22) FIG. 3 is similar to FIG. 2 but a metal 34 (e.g., Al or Cu) or a metal alloy fills the cavity in the doped polysilicon 30 to further reduce gate resistivity.

(23) In FIG. 4, a high conductivity metal silicide 32 is used as the first layer in the insulated trench. If the metal atoms in the silicide diffuse slowly enough, they will not significantly diffuse into the gate oxide 28. A metal 34 (e.g., Al or Cu) then fills the cavity in the silicide 32 to lower the resistance of the overall gate. The silicide 32 acts as a barrier to metal diffusion from the metal 34.

(24) In FIG. 5, three different materials are used in the insulated trench gate. A doped polysilicon 30 layer is deposited, followed by a metal silicide 32 layer, followed by metal 34 filling in the cavity. The polysilicon 30 and silicide 32 act as barrier layers for the metal atoms.

(25) FIG. 6 illustrates another embodiment of an insulated trench gate, where the top of the trenched gate 40 is formed of a higher conductivity material. In the example, the bottom part of the trench that forms the channel region is completely filled with doped polysilicon 30, and the top of the trench is filled with a higher conductivity material 42, such as metal silicide. This configuration lowers the connection resistance between the gate and the gate pad, yet the silicide does not affect the gate oxide 28 in the channel region (along the p-type layer 16). The trench may instead be filled with a combination of conductive materials, as described above.

(26) FIG. 7 illustrates another embodiment of an insulated trench gate, where the gate material, such as doped polysilicon 30 or any of the other gate materials discussed above, extends above the trench 46, and the top and exposed sides of the gate material is contacted by a highly conductive material, such as a metal silicide 48 or metal, for a very low resistance contact to the gate material. In a conventional insulated trench gate, there may be, at most, a direct connection to the top of the gate material in the trench, which is only a very small area. By also directly contacting the sides of the gate material extending above the trench, the contact area is greatly increased to reduce resistivity between the gate pad and the gate material. A dielectric 49 insulates the silicide 48, and a source electrode (not shown) contacts the tops of the n+ source regions 20.

(27) The gate material in FIG. 7 may comprise layers of different conductive materials, as described with respect to FIGS. 2-6, where the layers of different conductive materials extend above the trench and are electrically contacted by a contact material that directly contacts top and side surfaces of the exposed materials. The dashed outline 50 in the gate material of FIG. 7 represents the option of two different conductive materials in the trench.

(28) FIG. 8 illustrates another embodiment of an insulated trench gate. Prior to or after the trenches are formed, n-type source regions 52 are formed by masking and ion implantation adjacent to the insulated trench 53. Gate material 54, such as doped polysilicon, is deposited and etched to extend above the trench 53. A conductive material 55, such as a metal (e.g., Al or Cu, or alloys thereof), is formed over the top surface of the gate material 54. Oxide spacers 56 are then deposited and etched to form a mask for a deeper n-dopant implant with a higher concentration. Additional n-type dopants are then implanted and diffused. The oxide spacers 56 self-align the ion implantation to precisely control the shape of the n+ source contact region 60.

(29) A source electrode 62 then contacts the n+ source contact region 60.

(30) As with FIG. 7, the gate material in FIG. 8 may be any of the layered gate materials in FIGS. 2-7.

(31) FIG. 9 illustrates the power device of FIG. 1 but includes any of the new gate structures, labeled as gate 70 in FIG. 9, described herein.

(32) The concepts described above can be used to improve the performance of any insulated trench gate device, such as MOSFETs, IGTO devices, IGBTs, thyristors, etc.

(33) Various features disclosed may be combined to achieve a desired result.

(34) While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.