SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

Abstract

In this patent application, a new Metal Oxide Semiconductor MOS planar cell design concept is proposed. The inventive power semiconductor includes a planar cell forming a horizontal channel and a plurality of trenches, which are arranged orthogonally to the plane of the planar cells. A second p base layer is introduced which extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, a vertical channel is prevented from forming in the trench regions while allowing the horizontal channels to form. This is extremely important in order to avoid significant issues (i.e. shifts in Vth) encountered in prior art IGBT designs. The new cell concept adopts planar MOS channel and Trench technology in a single MOS cell structure. The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and processability (narrow mesa design rules, reliable planar process compatibility) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as Silicon Carbide SiC. Furthermore, the device is easy to manufacture, because the inventive design can be manufactured based on a self-aligned process with minimum number of masks, with the potential of additionally applying enhancement layers and/or reverse conducting type of structures.

Claims

1. A power semiconductor device comprising a first surface and a second surface separated in a first dimension, wherein an emitter electrode is operatively connected to the first surface and a collector electrode is operatively connected to the second surface, and wherein the power semiconductor device further comprises: a drift layer of a first conductivity type located between the first surface and the second surface; a first base layer of a second conductivity type located between the drift layer and the emitter electrode; a source region of the first conductivity type located within the first base layer and operatively connected to the emitter electrode, wherein a doping concentration of the source region is greater than a doping concentration of the drift layer; a second base layer of the second conductivity type located within the first base layer and under the source region, wherein a doping concentration of the second base layer region is greater than a doping concentration of the first base layer, wherein a first end of the second base layer is aligned with a first end of the source region in a second dimension and a second end of the second base layer extends beyond a second end of the source region in the second dimension, wherein at least part of the second end of the second base region is operatively connected to the emitter electrode via a contact opening; a first gate electrode located over the first base layer, the source region and the drift layer, wherein the first gate electrode is electrically insulated from the first base layer, the source region and the drift layer by a first insulating layer; a plurality of trench regions each comprising a second gate electrode and a second insulating layer, the second insulating layer electrically insulating the second gate electrode from the first base layer, the second base layer, the source region and the drift layer, wherein each trench region is located at least partially within the first base layer, and wherein a bottom of each trench region extends into the drift layer in the first dimension and a length of each trench region extends into the drift layer in the second dimension; wherein the second base layer is configured to prevent the formation of a first channel in the first dimension between the emitter electrode and the drift layer; and wherein the emitter electrode and the drift layer are separated in the second dimension by the first base layer and the source region, wherein the power semiconductor device is configured to form a second channel between the emitter electrode and the drift layer in the second dimension.

2. The power semiconductor device according to claim 1, wherein: the plurality of trench regions are shaped with respective stripes; the first base layer, the source region and the second base layer are shaped with respective stripes in orthogonal direction to the respective stripes of the trenches; and the respective stripes of the first base layers, source region and second base layer are divided into rectangles separated from each other by the respective stripes of the trenches.

3. The power semiconductor device according to claim 1, wherein: the first base layer, the source region and the second base layer are shaped with respective stripes; the plurality of trench regions are shaped with respective stripes in orthogonal direction to the respective stripes of the first base layer, the source region and the second base layer; and the respective stripes of the plurality of trench regions are divided into rectangles separated from each other by the respective stripes of the first base layer, the source region and the second base layer.

4. The power semiconductor device according to any preceding claim, wherein the first gate electrode and the second gate electrodes are electrically connected.

5. The power semiconductor device according to any preceding claim, wherein at least one of the second gate electrodes is electrically connected to the emitter electrode.

6. The power semiconductor device according to any preceding claim, wherein at least one of the second gate electrodes is electrically floating.

7. The power semiconductor device according to any preceding claim, further comprising at least one of: a buffer layer of the first conductivity type located between the drift layer and the second surface, wherein the a doping concentration of the buffer layer is greater than the doping concentration of the drift layer; and a collector layer of the second conductivity type located between the drift layer and the second surface.

8. The power semiconductor device according to claim 7, wherein the buffer layer is located between the drift layer and the collector layer.

9. The power semiconductor device according to claim 7 or 8, wherein the power semiconductor is a reverse conducting power semiconductor device and further comprises a shorted collector layer of the first conductivity type located between the buffer layer and the second surface.

10. The power semiconductor device according to any preceding claim, wherein an enhancement layer of the first conductivity type is located between and separates the drift layer and the first base layer.

11. The power semiconductor device according to any preceding claim, wherein a distance between adjacent trench regions of the plurality of trench regions in the third dimension is between about 5 μm and about 0.1 μm.

12. The power semiconductor device according to any preceding claim, wherein a distance between adjacent trench regions of the plurality of trench regions in the second dimension is between about 20 μm and about 1 μm.

13. The power semiconductor device according to any preceding claim, wherein the power semiconductor has a stripe layout design or cellular layout design.

14. A method for manufacturing a power semiconductor device, the method comprising: providing a lowly doped wafer of a first conductivity type having an emitter side and a collector side, wherein the lowly doped wafer forms a drift layer; applying a mask and etching a trench region on the emitter side of the lowly doped wafer; forming a first oxide layer on the emitter side of the lowly doped wafer; producing a structured gate electrode layer with at least one opening above the first oxide layer; using the structured gate electrode layer as a mask for implanting a first dopant of a second conductivity type into the lowly doped wafer, thereby forming a well; diffusing the first dopants into the lowly doped wafer; using the structured gate electrode layer as a mask for implanting second dopants of the first conductivity type into the lowly doped wafer; diffusing the second dopants to a lower depth than the first dopants, thereby forming a source contact; using the structured gate electrode layer as a mask for implanting third dopants of the second conductivity type into the lowly doped wafer to a depth higher than the second dopants; diffusing the third dopants into the substrate, wherein the third dopants are diffused to a lower depth than the first dopants; forming a second insulating layer above the emitter side of the lowly doped wafer; etching a contact opening through the second insulating layer and the second dopants; and filling the contact opening with a metal.

15. The method according to claim 14, wherein the first dopants are driven into a maximum depth between 1 μm and 5 μm, in particular between 1 and 3 μm and in particular between 1 and 2 μm, optionally wherein the first dopants Boron ions.

16. The method according to claim 14 or 15, wherein the second dopants are driven into a maximum depth between 0.5 μm and 1 μm, optionally wherein the second dopants are Phosphorous ions or Arsenic ions.

17. The method according to any one of claims 14 to 16, wherein the third dopants are driven into a maximum depth between 0.5 μm and 1.5 μm and completely cover a lower part of the second base layer, thereby preventing the formation of a vertical trench channel at the trench regions, optionally wherein the third dopants are Boron ions.

18. The method according to any one of claims 14 to 17, further comprising implanting fourth dopants into the emitter side of the lowly doped wafer, wherein the fourth dopants are driven into a maximum depth between 2 μm and 8 μm, in particular between 2 and 6 μm and in particular between 2 and 4 μm, optionally wherein the fourth dopants are Phosphorous ions.

19. The method according to any one of claims 14 to 18, wherein the first dopants are implanted with an energy of 20-100 keV and/and a dose of 5×10.sup.13/cm.sup.2 to 2×10.sup.14/cm.sup.2.

20. The method for manufacturing according to any one of claims 14 to 19, wherein the second dopants are implanted with an energy of 100-160 keV and/and a dose of 1×10.sup.15/cm.sup.2 to 1×10.sup.16/cm.sup.2.

21. The method according to any one of claims 14 to 20, wherein the third dopants are implanted to a higher depth than the second region with an energy of 100-160 keV and a dose of 1×10.sup.15/cm.sup.2 to 1×10.sup.16/cm.sup.2.

22. The method according to claim 18, wherein the fourth dopants are implanted with an energy of 20-100 keV and a dose of 5×10.sup.12/cm.sup.2 to 5×10.sup.13/cm.sup.2.

23. The method according to any one of claims 19 to 22, wherein the power semiconductor device is an insulated gated bipolar transistor (IGBT).

24. A semiconductor module package comprising one or more power semiconductor devices according to claims 1 to 13.

25. A converter comprising a plurality of power semiconductor devices according to any of the claims 1 to 13

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0106] The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which:

[0107] FIG. 1A-B: show the cross sections of Planar MOS IGBT structures (prior art).

[0108] FIG. 2A-B: show the cross sections of Trench MOS IGBT structures (prior art).

[0109] FIG. 3: show the cross section of Trench Planar MOS IGBT structure (prior art).

[0110] FIG. 4A-B: show an alternative cross-section of Trench Planar MOS IGBT structures, in particular structures with Gaussian p well profiles (prior art).

[0111] FIG. 5: show the cross sections of Planar Trench MOS IGBT structure (prior art).

[0112] FIG. 6: show three dimensional illustrations of the Trench Planar MOS IGBT structure with a planar channel orthogonal to the trench region (prior art).

[0113] FIG. 7: show the cross sections of FIG. 6 at cut B-B′ showing both planar and vertical MOS channels are formed (prior art).

[0114] FIG. 8: show three dimensional illustrations of the Trench MOS IGBT structure with a planar channel orthogonal to the trench region (prior art).

[0115] FIG. 9: show the cross sections of FIG. 8 at cut B-B′ (prior art).

[0116] FIG. 10: show a first example embodiment of a power semiconductor device according to the invention

[0117] FIG. 11: Top view of the first example embodiment of a punch-through IGBT according to the invention

[0118] FIG. 12: Top view of a second example embodiment of a punch-through IGBT according to the invention

[0119] FIG. 13: Cross section of FIG. 10 along A-A′ showing the planar MOS channel.

[0120] FIG. 14: Cross section of FIG. 10 along B-B′ showing that no vertical MOS channel is created.

[0121] FIG. 15: Cross section of FIG. 11 along C-C′ and D-D′.

[0122] FIG. 16: Cross section of FIG. 11 along E-E′ and F-F′.

[0123] FIG. 17: An example top view for a stripe design of first example embodiment of a punch-through IGBT according to the invention

[0124] FIGS. 18-28: show a cross section of the different steps of the method for manufacturing a semiconductor device according to the invention.

[0125] FIGS. 29-36: show a top view of the different steps of the method for manufacturing a semiconductor device according to the invention.

[0126] FIG. 37 shows a third example embodiment of a reverse conducting IGBT according to the invention.

[0127] FIG. 38 shows a fourth example embodiment of a punch through IGBT with n-enhancement layer according to the invention

[0128] The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0129] FIG. 10 shows a first exemplary embodiment of a power semiconductor device 1 in form of a punch through insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn). The layers are arranged between an emitter electrode 3 on an emitter side 31 and a collector electrode 2 on a collector side 21, which is arranged opposite of the emitter side 31. The IGBT comprises the following layers:

[0130] an (n−) doped drift layer 4, which is arranged between the emitter side 31 and the collector side 21,

[0131] a p doped first base layer 9, which is arranged between the drift layer 4 and the emitter electrode 3,

[0132] a p doped second base layer 8, which is arranged between the first base layer 9 and the emitter electrode 3, which second base layer 8 is in direct electrical contact to the emitter electrode 3, which second base layer 8 has a higher doping concentration than the first base layer 9, which second base layer 8 extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, preventing a vertical channel from forming in the trench regions while allowing the horizontal channels to form,

[0133] an n doped source region 7, which is arranged at the emitter side 31 embedded into the first base layer 9 and contacts the emitter electrode 3, which source region 7 has a higher doping concentration than the drift layer 4,

[0134] a first gate electrode 10, which is arranged on top of the emitter side 31 and the first gate electrode 10 is electrically insulated from the first base layer 9, the source region 7 and the drift layer 4 by a first insulating layer 12, an horizontal channel 15 is formable between the emitter electrode 31, the source region 7, the first base layer 9 and the drift layer 4,

[0135] a plurality of second gate electrodes 11, each of which is electrically insulated from the first base layer 9, the second base layer 8, the source region 7 and the drift layer 4 by a second insulating layer 12′ and which second gate electrode 11 is arranged orthogonally to the plane of the first base layer 9, the second base layer 8, and source region 7 and extends deeper into the drift layer 4 than the first base layer 9, a vertical channel is not formable between the emitter electrode 3, the source region 7, the second base layer 8, the first base layer 9 and the drift layer 4,

[0136] a collector layer 6 arranged between the buffer layer 5 and the collector electrode 2, which the collector layer 6 is in direct electrical contact to the collector electrode 2,

[0137] a buffer layer 5 arranged between the collector layer 6 and the drift region 4,

[0138] The trench regions can be better viewed in the top cell views shown in FIG. 11 and FIG. 12 for the two main embodiments of the inventive design with a discontinued trench and a continuous trench cutting through the planar cell. The inventive design consists of a basic planar MOS cell design with active trenches 11 (connected to gate electrode 10) occupying the regions between the planar cells in the Z dimension or in other words orthogonal to the X dimension (which represents also the longitudinal extension direction of the planar cells). It will be understood that the X, Y and Z dimensions generally correspond to the X, Y and Z dimensions as depicted in FIGS. 6 and 8. FIG. 13 to FIG. 15 show the cross sections of the inventive design along the cut lines shown in FIG. 11. The inventive design provides a lateral channel 15 in the planar regions 10 and lateral channel 15 a with improved vertical spreading in the trench region 11.

[0139] Specifically, the trench extends vertically to a depth approximately in a range from about 2 μm to about 7 μm. The trench width may range from about 3 μm to about 0.5 μm.

[0140] With respect to the Cartesian coordinate system shown in FIG. 16, the critical design aspects are the dimension W.sub.t or mesa between the orthogonal trenches, as well as the dimension W.sub.p representing the distance from the end of one trench to the adjacent trench along the planar channel. Improved carrier storage/reduced hole drainage is expected as the dimension W.sub.t and W.sub.p are reduced. The value of W.sub.t may be in a range from about 5 μm to below 0.1 μm, more preferably from 1 μm to 0.1 μm—which is achievable with the proposed design because no additional structures have to be lithographically defined in between the trenches, as in prior art. Also, improved carrier storage/reduced hole drainage is expected with reducing the planar cell dimensions, or by keeping the same pitch for the planar cell part, but reducing the distance W.sub.p by etching the adjacent trenches closer to each other in the X direction. More specifically, W.sub.p could extend approximately in a range from about 20 μm to about 1 μm, preferably from 5 μm to 1 μm, and more preferably from 2 μm to 1 μm.

[0141] The inventive method for manufacturing a planar MOS cell on an emitter side is shown in cross sections in the FIGS. 18 to 28 and top view in the FIGS. 29 to 36. The method comprises manufacturing steps as follows.

[0142] As shown in FIG. 18 (top view FIG. 29) the method is started with a lightly n doped substrate 4, which has an emitter side 31. As shown in FIG. 19 (top view FIG. 30), a trench region 11′ is produced by dry etching through a mask opening 111 into the substrate 4. A first oxide layer 12 and second oxide layer 12′ are produced completely covering the substrate 4 on the emitter side 31. As shown in FIG. 20 (top view FIG. 31) an electrically conductive layers 10 and 11 are produced on top of the first oxide layer 12 and second oxide layer 12′ respectively. The electrically conductive layers 10 and 11 cover the first oxide layer 12 and second oxide layer 12′ completely. According to FIG. 21 (top view FIG. 32) an opening 101 in form of a through hole is etched in the electrically conductive layer 10, resulting in a structured gate electrode layer 10, so that part of the first oxide layer 12 is now uncovered 10′.

[0143] Afterwards, the first dopants of p conductivity type are implanted into the substrate 4 (shown by arrows 90 in FIG. 22) (top view FIG. 33) using the structured gate electrode layer with its opening as a mask, resulting in a first implant region 9. Afterwards, the implanted first dopants are diffused into the substrate 4. The first dopants are preferably boron ions. The first dopants are preferably implanted with an energy of 20-100 keV and/or a dose of 5×10.sup.13/cm.sup.2 to 2×10.sup.14/cm.sup.2. The first dopants are driven into a maximum depth between 1 μm and 5 μm, in particular between 1 and 3 μm and in particular between 1 and 2 μm. As shown in FIG. 23, the first dopants are not only driven into the substrate 4 in a direction perpendicular to the surface, but they are spread out laterally.

[0144] Afterwards, the second dopants of highly doped n conductivity type are is implanted into the substrate 4 (shown by arrows 70 in FIG. 23) (top view FIG. 34) using the structured gate electrode layer with its opening as a mask, resulting in a second implant region 7. Afterwards, the implanted second dopants are diffused into the substrate 4. The second dopants are preferably Phosphorous or Arsenic preferably Arsenic ions. The second dopants are preferably implanted with an energy of 100-160 keV and/or a dose of 1×10.sup.15/cm.sup.2 to 1×10.sup.16/cm.sup.2. The second dopants are driven into a maximum depth between 0.5 μm and 1 μm. As shown in FIG. 24, the second dopants are mainly driven into the substrate 4 in a direction perpendicular to the surface, but they are only slightly spread out laterally to form the critical source region under the gate oxide.

[0145] Afterwards, the third dopants of highly doped p conductivity type are implanted into the substrate 4 (shown by arrows 80 in FIG. 24) (top view FIG. 35) using the structured gate electrode layer with its opening as a mask, resulting in a third implant region 8. Afterwards, the implanted third dopants are diffused into the substrate 4. The third dopants are preferably Boron ions. The third dopants are preferably implanted to a higher depth than the second region with an energy of 100-160 keV and/or a dose of 1×10.sup.15/cm.sup.2 to 1×10.sup.16/cm.sup.2. The third dopants are driven into a maximum depth between 0.5 μm and 1.5 μm. As shown in FIG. 25, the third dopants are mainly driven into the substrate 4 in a direction perpendicular to the surface, but they are only slightly spread out laterally to completely cover the lower part of the second region and ensure no vertical trench channel can be formed at the trench regions.

[0146] Afterwards, an insulating oxide layer 13 is produced to cover the first main side 31 completely as shown in FIG. 26. The insulating oxide layer thickness can range between 500 nm to 1500 nm. A contact opening 14 is then produced by dry etching fully through a mask opening 141 the insulating oxide layer 13 and the second dopants region 7 layer to reach the third dopants region 8 as shown in FIG. 27 (top view FIG. 36). The contact opening 14 is filled with metal to produce a direct electrical emitter contact 3 to the second dopants region 7 and third dopants region 8 as shown in FIG. 28.

[0147] The inventive design is especially suitable for reverse conducting structure by introducing n type dopants at the collector side to produce collector shorts 18 and an internal anti-parallel diode structure as shown in FIG. 37.

[0148] An enhancement layer or fourth dopants of lightly doped n conductivity type can be implanted and diffused before the first dopants implant as shown in FIG. 38. The fourth dopants of n conductivity type are implanted into the substrate 4 using the structured gate electrode layer with its opening as a mask, resulting in a fourth implant region 17. Afterwards, the implanted fourth dopants are diffused into the substrate 4. The fourth dopants are preferably Phosphorous ions. The fourth dopants are preferably implanted with an energy of 20-100 keV and/or a dose of 5×10.sup.12/cm.sup.2 to 5×10.sup.13/cm.sup.2. The fourth dopants are driven into a maximum depth between 2 μm and 8 μm, in particular between 2 and 6 μm and in particular between 2 and 4 μm. As shown in FIG. 38, the fourth dopants are not only driven into the substrate 4 in a direction perpendicular to the surface, but they are spread out laterally.

[0149] It is possible to apply the invention to a method for the manufacturing of semiconductor devices, in which the conductivity type of all layers is reversed, i.e. with a lightly p doped substrate etc.

REFERENCE LIST

[0150] 1: inventive planar MOS cell power semiconductor device [0151] 3: emitter metallization (electrode) [0152] 31: emitter side [0153] 2: collector metallization (electrode) [0154] 21: collector side [0155] 4: drift layer, substrate [0156] 5: buffer layer [0157] 6: collector layer [0158] 7: n source layer [0159] 8: p second base layer [0160] 9: p first base layer [0161] 10: planar gate electrode, electrically conductive layer [0162] 10′: uncovered gate electrode [0163] 11: trench gate electrode, electrically conductive layer [0164] 11′: trench region [0165] 12: insulating gate oxide gate electrode for planar gate [0166] 12′: insulating gate oxide gate electrode for trench gate [0167] 13: insulation layer for planar cell and trench cell [0168] 14: emitter contact opening [0169] 15: horizontal channel for planar gate [0170] 16: vertical channel for trench gate [0171] 17: enhancement layer [0172] 18: collector shorts [0173] 70: source implantation step [0174] 80: second base implantation step [0175] 90: first base implantation step [0176] 100: electrically conductive layer etch mask [0177] 110: electrically conductive layer etch mask opening [0178] 111: trench etch mask opening [0179] 140: contact etch mask [0180] 141: contact etch mask opening [0181] 200: planar MOS cell power semiconductor device (prior art) [0182] 300: trench MOS cell power semiconductor device (prior art) [0183] 400: trench planar MOS cell power semiconductor device (prior art) [0184] 401: trench planar MOS cell power semiconductor device (prior art) [0185] 500: trench planar MOS cell power semiconductor device (prior art) [0186] 600: trench planar MOS cell power semiconductor device (prior art) [0187] 700: trench planar MOS cell power semiconductor device (prior art) [0188] 800: planar MOS cell power semiconductor device (prior art)