METHOD OF PRODUCING A SEMICONDUCTOR BODY WITH A TRENCH, SEMICONDUCTOR BODY WITH AT LEAST ONE TRENCH AND SEMICONDUCTOR DEVICE

Abstract

A method is proposed of producing a semiconductor body with a trench. The semiconductor body comprises a substrate. The method comprising the step of etching the trench into the substrate using an etching mask. An oxide layer is formed at least on a sidewall of the trench by oxidation of the substrate. A passivation layer is formed on the oxide layer and the bottom of the trench. The passivation layer is removed from the bottom of the trench. Finally, a metallization layer is deposited into the trench.

Claims

1. A method of producing a semiconductor body with a trench, wherein the semiconductor body comprises a substrate, the method comprising: etching the trench into the substrate using an etching mask, forming an oxide layer at least on a sidewall of the trench by oxidation of the substrate, forming a passivation layer on the oxide layer and the bottom of the trench, removing the passivation layer from the bottom of the trench, and depositing a metallization layer into the trench.

2. The method according to claim 1, wherein the oxidation of the substrate involves: a wet-chemical oxidation process, and/or an oxidation induced by an atmospheric plasma.

3. The method according to claim 2, wherein the wet-chemical procedure involves an oxidizing agent which is applied into the trench via the etching mask.

4. The method according to claim 2, wherein the atmospheric plasma comprises an oxidizing species as process gas, such as ozone and/or oxygen.

5. The method according to claim 1, wherein the oxidation is performed at a temperature below the melting point of the substrate and/or other materials used for the semiconductor.

6. The method according to claim 1, wherein the oxidation is performed at a temperature below 800° C., and/or the oxidation is performed at a temperature from a range of 150° C. to 400° C.

7. The method according to claim 1, wherein the substrate comprises bulk silicon, and the oxide layer comprises SiO.sub.2, which is formed by the oxidation of bulk silicon.

8. The method according to claim 7, wherein the oxidation of bulk silicon is performed in an oxygen plasma such that a film SiO.sub.2 is grown on the sidewall at temperatures down to room temperature.

9. The method according to claim 8, wherein the oxygen plasma comprises a Helium and Oxygen mixture.

10. The method according to claim 1, wherein the steps of etching the trench, forming the oxide layer, forming and removing the passivation layer are repeated until the trench has a desired depth, and/or wherein further etching the trench into the substrate involves using the etching mask and the remaining passivation layer on the sidewall.

11. The method according to claim 1, wherein the metallization is electrically connected to electrodes such that the trench is operable as a through-substrate via.

12. A semiconductor body with at least one trench comprising a substrate, wherein the trench comprises: at least one sidewall, an oxide layer arranged at least on the sidewall of the trench and formed from an oxidation of the substrate, a passivation layer arranged on the oxide layer on the sidewall, and a metallization layer arranged in the trench.

13. The semiconductor body according to claim 12, wherein the oxide layer comprises an oxide from the bulk substrate, and the passivation layer comprises an oxide which has been applied onto the oxide layer so as to form an additional layer and/or the passivation layer comprises an oxide of the same substrate which has been applied onto the oxide layer so as to form the additional layer.

14. A semiconductor device comprising: at least one semiconductor body according to claim 11, at least one electrical component, and the at least one trench is operable as a through-substrate via and electrically connected to the at least one electrical component.

15. The semiconductor device according to claim 14, wherein the at least one electrical component comprises a photodiode structure, such as a pn-junction or pin-junction.

16. A method of producing a semiconductor body with a trench, wherein the semiconductor body comprises a substrate, the method comprising: etching the trench into the substrate using an etching mask, forming an oxide layer at least on a sidewall of the trench by oxidation of the substrate, forming a passivation layer on the oxide layer and the bottom of the trench, removing the passivation layer from the bottom of the trench, and depositing a metallization layer into the trench; wherein the steps of etching the trench, forming the oxide layer, forming and removing the passivation layer are repeated until the trench has a desired depth, and/or wherein further etching the trench into the substrate involves using the etching mask and the remaining passivation layer on the sidewall.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the following, the concept presented above is described in further detail with respect to drawings, in which examples of embodiments are presented. In the embodiments and Figures presented hereinafter, similar or identical elements may each be provided with the same reference numerals. The elements illustrated in the drawings and their size relationships among one another, however, should not be regarded as true to scale, rather individual elements, such as layers, components, and regions, may be exaggerated to enable better illustration or a better understanding.

[0034] FIG. 1 shows cross section through an example embodiment of a semiconductor body,

[0035] FIG. 2A shows an example process sequence of producing a semiconductor body with a trench,

[0036] FIG. 2B shows an example process sequence of producing a semiconductor body with a trench,

[0037] FIG. 2C shows a comparison of sidewall defects,

[0038] FIG. 3 shows a flowchart of an example Bosch process, and

[0039] FIG. 4 shows a schematic of defect formation on the silicon sidewall of a TSV structure during DRIE processing.

DETAILED DESCRIPTION

[0040] FIG. 1 shows cross section through an example embodiment of a semiconductor body. The semiconductor body 10 comprises an etching mask 38 which features a recess 25. The etching mask 38 may have several layers such as a hard-mask oxide layer 21, a nitride layer 22, a polysilicon layer 23 and a photoresist 24, for example. A trench 11 in the semiconductor body 10 extends perpendicular to a first main surface 17 of the semiconductor body 10. The trench 11 comprises a sidewall 14 and a bottom 15. The trench 11 extends from the first main surface 17 to the bottom 15 and is aligned orthogonally to the first main surface 17. The trench 11 has a depth T and a width D. In this case, the depth T corresponds to the distance between the bottom 15 and the first main surface 17. The first main surface 17 represents one of the boundaries of the substrate material 16.

[0041] The trench 11 may be produced by means of a deep etching process, during which two different gas compositions alternately act upon the semiconductor body 10. The deep etching process can be based on a process flow based on deep reactive-ion etching, DRIE, which is a highly anisotropic etch process used to create deep penetration, steep-sided holes and trenches in wafers/substrates, and allows for high aspect ratios. The first gas composition produces a polymer on the surface of the substrate, i.e. on a side wall 14 and bottom 15 of the trench 11. The second gas composition serves for etching the substrate material 16. The two gases can be C.sub.4F.sub.8 as the first gas and SF.sub.6 as the second gas, for example. The polymer on the bottom 15 is removed, e.g. by means of a sputtering process while the second gas composition is in the reactor chamber. Removal is affected by means of the physical stage of the deep etching process. The polymer on the side wall 14 is only slightly dissolved by the chemical stage of the process and therefore serves to protect the side wall 14 from being etched by the second gas composition.

[0042] The etching and deposition processes alternate cyclically. Since the first and second gas composition also act on the semiconductor body 10 alternately, scallops 51 to 54 are produced in the side wall 14 of the trench 11 as shown in FIG. 1. If the processing time for the first application of the second gas composition is chosen to be longer than the processing times for the other applications of the second gas composition in the subsequent cycles, it is possible to produce a first scallop 51, with dimensions parallel and perpendicular to the first main surface 17 that are greater than those of the other scallops 52 to 54. Consequently, an undercut 27 of the etching mask arrangement 38 is achieved by means of the first scallop 51. This means that the width B of the trench 11 can be increased relative to the width A of the recess 25 of the etching mask arrangement 38. A width B′ in the region of the first scallop 51 is greater than a width B″ in the region of the other scallops 52 to 54. The scallops 51 to 54 are generated because the gas composition and, thus, the effects of the different gas compositions on the semiconductor substrate change periodically.

[0043] An exemplary procedure could be summarized as follows:

[0044] Step 1: An etching gas composition is introduced into an etching reactor. The etching gas isotropically etches Silicon. The composition comprises SF.sub.6. The gas etches silicon at regions of the semiconductor body which are not covered by an etch mask. Since the gas performs an isotropic etching effect, a first cavity is generated, wherein the etch mask is underetched. Thus, a first scallop is created.

[0045] Step 2: A deposition gas composition is introduced in the etching reactor which generates a polymer layer on top of the surface including the cavity. The composition comprises C.sub.4F.sub.8.

[0046] Step 3: The etching gas composition is introduced again. A gas of the etching gas composition performs an anisotropic etching. Thus, this gas removes the polymer at the bottom of the cavity. The sidewalls of the cavity are still covered by the polymer.

[0047] Steps 1 and 3 can be repeated as required and until the trench 11 has a desired depth T. The etching gas composition again etches silicon isotropically in regions where no etch mask such as the polymer layer exists. The silicon at the bottom of the cavity is removed, the polymer etch mask is underetched and, thus, a second cavity below the first cavity with a second scallop is generated.

[0048] FIG. 2A shows an example process sequence of producing a semiconductor body with a trench. During a deep etching process, such as the DRIE process discussed above, defects can develop in the semiconductor body. In the worst case sharp tips emerge and extend from the sidewall 14. Often such tips cannot be sufficiently covered in additional process steps, e.g. by means of dielectric material applied to the sidewalls.

[0049] An example process sequence is depicted in FIG. 2A for easy reference. The drawing shows part of a sidewall inside a trench 11. In step a) a sidewall defect (often denoted pocketing) is created during the DRIE process. Creation of a pocket results in a thin sharp tip (needle-like) protruding from the sidewall 14. In a next step b) a passivation layer, e.g. an isolation oxide layer, is deposited onto the sidewall 14. The defect is also covered with the oxide layer. As a consequence the oxide-step develops as defect as well. In step c) the isolation oxide layer is etched anisotropically so as to remove oxide from the bottom 15 of the trench (not shown). This also increases oxide loss at the oxide step at the defect site. In order to render the trench 11 operable as an electronic interconnect, such as a TSV, a metallization layer, e.g. tungsten W, is deposited onto the sidewall 14.

[0050] Due to the high oxide loss during isolation etch, however, a distance between the semiconductor body (Si) and the metallization layer (W) is reduced compared to a region without a defect (indicated with the red arrow in the outtake of step d)). As discussed above the defect may decrease electrical performance of the trench when used as electrical interconnect and may reduce reliability against electrical breakdown. Typically a defect site or needle leads to local reduction of isolation thickness and potentially leading to a lowered breakdown voltage.

[0051] FIG. 2B shows an example process sequence of producing a semiconductor body with a trench. The process sequence discussed in FIG. 2A can be complemented with forming an oxide layer at least on a sidewall of the trench 11 by oxidation of the substrate. This step is different from the applying the passivation layer, such as the isolation oxide layer, discussed in FIG. 2A. In fact, forming the oxide layer involves oxidation of the substrate directly, i.e. the bulk substrate is oxidized as opposed to depositing oxidized substrate onto the semiconductor body, e.g. in a CVD process. This way the oxide layer is formed by converting the material of the semiconductor body into an oxide of said material, e.g. silicon, Si, into silicon dioxide, SiO.sub.2.

[0052] The process sequence in FIG. 2B comprises step a) wherein the deep etching or DRIE is executed. Eventually, a sidewall defect is created during the DRIE process. In step b1) the oxide layer is created by oxidation of the semiconductor material. This way Si is converted and a thin SiO.sub.2 layer is formed by oxidation of the bulk Si (converting Si to SiO.sub.2). The following step b2) corresponds to step b) in FIG. 2A. Thus, a passivation layer, e.g. an additional isolation oxide layer, is deposited onto the sidewall 14 covered with the oxide layer. The defect is also covered with two oxide layers. As a consequence the oxide-step develops a defect as well.

[0053] In step c) the isolation oxide layer is etched so as to remove oxide from the bottom 15 of the trench (not shown). This also increases oxide loss at the oxide step at the defect site. In order to render the trench 11 operable as an electronic interconnect, such as a TSV, a metallization layer, e.g. tungsten W, is deposited onto the sidewall 14. Due to the high oxide loss during isolation etch, however, a distance between the semiconductor body (Si) and the metallization layer (W) is reduced compared to a region without a defect (indicated with the red arrow in the outtake of step d)).

[0054] Creating the oxidation layer, i.e. converting a layer of the semiconductor body into a layer of its oxide, can be realized in several ways. One possibility involves a wet-chemical oxidation process. This procedure involves an oxidizing agent which is applied into the trench via the etching mask. Another possibility involves an oxidation induced by an atmospheric plasma.

[0055] The atmospheric plasma, also denoted cold plasma, non-thermal plasma, or non-equilibrium plasma, comprises an oxidizing species as process gas, such as ozone and/or oxygen. This type of oxidation is performed at a temperature below the melting point of the substrate. For example, the oxidation is performed at a temperature below 800° C., or, typically, at a temperature from a range of 150° C. to 400° C. Temperatures may, however, reach down to room temperature. The plasma is created and applied under ambient pressure, or close to that pressure.

[0056] The oxidation of bulk silicon is performed in an Oxygen plasma such that a film SiO.sub.2 is grown on the sidewall, for example. For example, an Oxygen plasma is used and comprises a Helium and Oxygen mixture, e.g. with a concentration of Oxygen equal or smaller than 5%.

[0057] Plasma-enhanced chemical vapor deposition, PECVD, can be used to apply the plasma and initiate oxidization. PECVD is a chemical vapor deposition process used to deposit thin films from a plasma to a solid state on a substrate. In general, there are known ways to create the oxide layer using PECVD. For example, Silicon dioxide can be deposited using a combination of silicon precursor gasses like dichlorosilane or silane and oxygen precursors, such as oxygen and nitrous oxide, typically at pressures from a few millitorr to a few torr. Plasma-deposited silicon nitride, formed from silane and ammonia or nitrogen, can also be used. Plasma nitrides always contain a large amount of hydrogen, which can be bonded to silicon (Si—H) or nitrogen (Si—NH). This hydrogen has an important influence on IR and UV absorption, stability, mechanical stress, and electrical conductivity. This can be used as a surface and bulk passivating layer. Silicon oxide can also be deposited from a tetraethoxysilane (TEOS) silicon precursor in an oxygen or oxygen-argon plasma. These films can be contaminated with significant carbon and hydrogen as silanol, and can be unstable in air. Pressures of a few torr and small electrode spacing, and/or dual frequency deposition, are helpful to achieve high deposition rates with good film stability. High-density plasma deposition of silicon dioxide from silane and oxygen/argon can be used to create a nearly hydrogen-free film with good conformity over complex surfaces, the latter resulting from intense ion bombardment and consequent sputtering of the deposited molecules from vertical onto horizontal surfaces.

[0058] FIG. 2C shows a comparison of sidewall defects. The left side of the drawing shows a sidewall defect treated without the additional oxidation layer, the right side of the drawing shows a sidewall defect treated with the additional oxidation layer. As indicated by the arrows with additional oxidation step a distance between the defect (such as Si tip/needle) and metallization layer such as tungsten, W) can be significantly increased. The oxide layer introduced by the oxidation step helps to increase the isolation layer thickness at the area of the sidewall defect by conversion of bulk Si into SiO.sub.2. With the adapted process sequence including the oxidation layer isolation deposition sequence an electrical interconnect structure, such as a TSV, can be manufactured with improved electrical performance and reduced susceptibility to sidewall defects produced during deep etching such as DRIE. The proposed process sequence provides a method of producing a semiconductor body with a trench, e.g. for electrical interconnect structures such as TSVs, with reduced leakage current, increased process robustness and increased breakdown voltage. Besides yield improvement the method enables creation of 3D integrated, low leakage devices. TSVs can be manufactures with superior leakage current performance compared to common solutions. SEM x-section of the semiconductor body have been found that the different oxide layer (Si-Oxide layers) can be distinguished.