Method for modifying the strain state of a block of a semiconducting material

Abstract

A method is provided for modifying a strain state of a block of a semiconducting material including steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making at least one recrystallization annealing of the lower region of the block.

Claims

1. A method for modifying a strain state of a block of a semiconducting material comprising steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, the stressing zone being a strained silicon nitride layer, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making at least one recrystallization annealing of the lower region of the block.

2. The method according to claim 1, wherein the block of the semiconducting material, the lower region of which is made amorphous in step a), is a block of strained semiconducting material.

3. The method according to claim 1, wherein the substrate is a semiconductor on insulator type substrate comprising a support layer, an insulating layer supported on the support layer, and a superficial semiconducting layer supported on the insulating layer, the block of the semiconducting material forming part of the superficial layer.

4. The method according to claim 3, wherein trenches are formed in the insulating layer on each side of the block of the semiconducting material.

5. The method according to claim 1, wherein the block of the semiconducting material is based on Si, and the at least one creep annealing in step c) is done at a temperature between 300 C. and 400 C.

6. A method for fabricating a microelectronic transistor device comprising implementation of the method according to claim 1.

7. The method according to claim 1, comprising forming the stressing zone in contact with the upper region of the block and not in contact with the lower region of the block.

8. The method according to claim 1, comprising forming the stressing zone in contact with an entire surface of the upper region of the block.

9. A method for modifying a strain state of a silicon-based block, comprising steps in the following order: a) making amorphous a lower region of the silicon-based block resting on a substrate, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the silicon-based block, the stressing zone being a strained layer made of an amorphous nitride material, then c) making a creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making a recrystallization annealing of the lower region of the silicon-based block.

10. The method according to claim 9, wherein the stressing zone is a strained silicon nitride layer.

11. The method according to claim 9, wherein the stressing zone comprises a strained layer made of a dielectric material.

12. A method for modifying a strain state of a block of a semiconducting material comprising steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, the stressing zone being a strained silicon nitride layer, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making at least one recrystallization annealing of the lower region of the block, the method further comprising forming the stressing zone made of a compressively strained silicon nitride to strain the block in tension.

13. A method for modifying a strain state of a block of a semiconducting material comprising steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, the stressing zone being a strained silicon nitride layer, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region comprising relaxing a stress of the lower region by at least 300 MPa, and then d) making at least one recrystallization annealing of the lower region of the block.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) This invention will be better understood after reading the description of example embodiments given purely for information and that is in no way limitative with reference to the appended drawings in which:

(2) FIGS. 1A-1D show an example method designed to reduce the strain state of a strained semiconducting block and in which at least one creep annealing of the semiconducting block is done according to the invention;

(3) FIG. 2 shows a variant of the method in which the semiconducting block is supported on an etched insulating zone;

(4) FIGS. 3A-3E show another example method according to the invention consisting of stressing a strained semiconducting block and in which at least one creep annealing of the semiconducting block is done according to the invention;

(5) FIGS. 4A-4E show a variant of the method according to the invention implemented on a bulk substrate;

(6) As is standard practice in representing semiconducting structures, the various sectional views are not drawn to scale. The different parts shown in the figures are not necessarily all at the same scale to make the figures more easily readable, the angles formed by the side faces of the different layers being used particularly to show the different strain states of these layers.

(7) Furthermore in the following description, terms that depend on the orientation of a structure such as lower and upper are applicable considering that the structure is oriented in the manner shown in the figures.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

(8) A first example of a method according to the invention that can modify the strain state of a semiconducting block will now be disclosed with reference to FIGS. 1A-1D.

(9) In this example, the initial material for this method is a strained semiconducting on insulator type substrate, for example of the sSOI (strained silicon on insulator) type. The substrate thus comprises a support layer 10 for example a semiconducting layer that may be based on Si and an insulating layer 11, for example based on silicon oxide located on and in contact with the support layer 10 and a so-called superficial semiconducting layer located on and in contact with said insulating layer 11 and that is strained, for example tensile strained (FIG. 1A). For example, the strained superficial semiconducting layer may be between 10 nm and 200 nm, and preferably between 15 nm and 40 nm thick.

(10) An ionic implantation (FIG. 1B) is then made of a semiconducting block 12 of the superficial layer that can have been obtained by etching this superficial layer.

(11) The implantation is made so as to make a lower region 12a of the semiconducting block 12 amorphous. The implantation profile is such that the upper region 12b maintains its crystalline structure. The upper region receives a dose less than the amorphization threshold that is usually of the order of 10% of atoms displaced in a crystal, namely about 3.6E.sup.21 atoms.cm.sup.3 in crystalline Si.

(12) In this particular example, the lower region 12a made amorphous is in contact with the insulating layer 12 of the substrate, while a crystalline germ is kept on the surface of the semiconducting block 12.

(13) The ionic implantation species is preferably a lightweight species. The amorphizing implantation may be made by means of an inert species for the implanted semiconducting material, for example Si atoms when the semiconducting material that is implanted is Si. In this case an inert species refers to a species that will not modify the conducting properties of the implanted semiconducting material.

(14) The amorphizing implantation conditions of the semiconducting block 12 may be defined using a simulation tool for example such as C-TRIM (CTRIM for Crystal Transport of Ions in Matter) type software using Monte Carlo algorithms. If a 30 nm thick region of an Si block 12 is implanted, the implantation energy may for example be between 15 keV and 30 keV, for example with an implantation dose of between 1.sup.E14 and 8.sup.E14 atoms/cm.sup.2.

(15) For an implantation of an Si block, a dose for example equal to approximately 4.sup.E14 with an energy for example of the order of 20 keV or a dose for example of the order of 3.sup.E14 with an energy for example of the order of 30 keV can be used to make a stack comprising an amorphous lower region of the order of 20 nm thick above which there is an upper crystalline region of the order of 10 nm thick.

(16) A creep annealing is then done (FIG. 1C).

(17) The creep annealing is done at a temperature and for a duration chosen to enable the lower amorphous region 12a to creep, while preventing recrystallization of this region.

(18) The temperature of this creep annealing is thus chosen to be lower than the recrystallization temperature of the semiconducting material of the semiconducting block 12, for example less than 500 C. when the semiconducting block 12 is based on Si.

(19) For example in the case of a block 12 based on another semiconducting material such as Si.sub.xGe.sub.1x or Ge, the creep temperature may be chosen as a function for example of recrystallization temperature data like those described in a document by O. Hellman, Materials Science and Engineering: R: Reports Volume 16, Issue 1, 1996.

(20) The thermal budget for the creep annealing is also designed to be sufficiently high to enable relaxation of the initially strained lower region 12b of the semiconducting block 12, and particularly a relaxation such that the lower region 12b of the semiconducting block 12 is affected by a stress variation of at least 300 MPa.

(21) For example, the document viscosity and elastic constants of amorphous Si and Ge by Witvrouw et al., Journal of Applied Physics 74,1993 gives conditions for the relaxation of Si.

(22) Based on the data in the previous document, a table can be determined providing results of stress measurements as a function of an annealing duration applied on an Si block after a creep annealing has been done on the Si block at a temperature chosen of the order of 350 C. A creep annealing lasting for the order of 1 hour may be done to relax this Si semiconducting block with an initial stress for example of the order of 1 GPa.

(23) TABLE-US-00001 t(s) Sigma (Mpa) 0 1000 1 999 2 999 3 998 4 998 5 997 10 994 60 966 120 932 600 705 1200 497 3600 122

(24) A second table below gives a correspondence between the annealing temperature of a block of Si and the annealing duration necessary to enable creep with an associated viscosity value.

(25) TABLE-US-00002 T( C.) viscosity (pa .Math. s) tcarac (s) 200 1.3E+18 5E+07 225 1.5E+17 6E+06 250 2.1E+16 9E+05 275 3.5E+15 1E+05 300 6.9E+14 3E+04 325 1.6E+14 7E+03 350 4.0E+13 2E+03 375 1.2E+13 5E+02 400 3.6E+12 2E+02 425 1.2E+12 5E+01 450 4.5E+11 2E+01 475 1.8E+11 8E+00 500 7.5E+10 3E+00 525 3.3E+10 1E+00 550 1.5E+10 7E01 575 7.6E+09 3E01 600 3.8E+09 2E01 625 2.0E+09 9E02 650 1.1E+09 5E02

(26) An annealing temperature equal to at least 300 C. is preferable to maintain a reasonable annealing duration relative to industrially applied stresses.

(27) When the block 12 is based on Si, the creep annealing temperature may thus advantageously be chosen between 300 C. and 400 C. while the duration may be fixed for example between several tens of seconds and several hours.

(28) Then, after performing the creep annealing, a recrystallization annealing is made on the lower region 12a of the semiconducting block 12, using the upper region 12b of the semiconducting block as the initial zone for a recrystallization front (FIG. 1D).

(29) In order to recrystallize the semiconducting block 12 when it is based on Si, annealing is done at a temperature preferably more than 500 C., that may for example be between 600 C. and 1150 C. The annealing duration may for example be more than 2 minutes for an annealing temperature of the order of 600 C. Since a high thermal budget gives better recrystallization, annealing at a temperature of the order of 1100 C. for a duration of 30 minutes can advantageously be used.

(30) According to one variant embodiment shown in FIG. 2, during the formation of the semiconducting block 12 by etching the superficial layer, this etching can be extended in the insulating layer 11 stopping on or in the support layer 10. The result is that trenches 17 are formed on each side of the semiconducting block 12 around a zone 18 of the insulating layer of the substrate on which this block is supported. The edges of the insulating zone 18 in this case are located along the extension of the lateral flanks of the semiconducting block.

(31) This may make it possible to further modify stresses applied on the semiconducting block.

(32) As a variant, these trenches may be formed after amorphization. In this case, the etching conditions, and particularly the temperature, are selected so that the block will not be crystallized.

(33) Another example process according to the invention is shown in FIGS. 3A-3E. In this case, this method is aimed at increasing the strain state of a semiconducting block.

(34) In this example, the initial material is a semiconducting on insulator type substrate, for example an SOI (silicon on insulator) type that is different from that in the previous example in that the surface semiconducting layer 12 located on and in contact with the insulating layer 11 in this case does not have any intrinsic strain.

(35) The next step is an ion implantation that makes a lower region 22a of a semiconducting block 22 of the superficial semiconducting layer amorphous while maintaining the crystalline structure of an upper region 22b of this block (FIG. 3B).

(36) The next step is to form a straining zone 24 on the upper region 22b of the semiconducting block. The straining zone 24 may be based on a strained amorphous material, for example such as Si.sub.xN.sub.y. The straining zone 24 may for example be based on Si.sub.xN.sub.y strained in compression in order to strain the semiconducting block 22 in tension.

(37) The next step is a creep annealing with a sufficient thermal budget so that the region made amorphous 22b can creep and designed so that this region is not recrystallized (FIG. 3D).

(38) This creep annealing is done at a temperature below the recrystallization temperature of the semiconducting material of the block 12 and sufficiently high so that this semiconducting material can relax. In the case of a semiconducting block 12 based on Si, the creep annealing may for example be made at a temperature of between 300 C. and 400 C., with a duration for example of between several seconds and several hours.

(39) The next step is a recrystallization annealing of the lower region 22a of the semiconducting block 22 at a temperature that may for example be between 500 C. and 1150 C. and for example a duration longer than 2 minutes.

(40) The next step is to remove the straining zone 24 (FIG. 3E). In the case in which this zone is based on Si.sub.xN.sub.y, this withdrawal may for example be made by etching using Ortho-phosphoric acid H.sub.3PO.sub.4, at a temperature for example of between 50 C. and 100 C.

(41) In one variant embodiment, the process as disclosed above is used starting from a bulk substrate 30, for example on which a semiconducting block 32 based on Si is formed (FIG. 4A).

(42) A lower region 32a of the semiconducting block 32 is made amorphous while maintaining the crystalline structure of an upper region 32b of this block (FIG. 4B).

(43) The next step is to form a straining zone 34 on the upper region 32b of the semiconducting block (FIG. 4C). For example, the zone 34 may be a compression zone of the semiconducting block 32 based on silicon nitride.

(44) The next step is creep annealing with an adapted temperature and duration pair so that the amorphous lower region 32a can creep without recrystallizing (FIG. 4D). Thus, the thermal budget is made sufficiently low to prevent recrystallization of the lower region 32a and sufficiently high so that this semiconducting material can creep and there can be a stress variation of at least 300 MPa.

(45) In the case of a semiconducting block 12 based on Si, the temperature of this creep annealing may for example be between 300 C. and 400 C., while the annealing duration may for example be between several tens of seconds and several hours.

(46) The next step is a recrystallization annealing of the lower region 32a of the semiconducting block 32 at a temperature that may for example be between 500 C. and 1150 C. for a duration for example of between 2 minutes and several hours.

(47) The next step is to remove the straining zone 34 (FIG. 4E).