Heterogeneous annealing method and device

Abstract

A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Claims

1. A bonded structure comprising: a first element having a first surface with a first insulating region and a first contact structure, the first element having a thickness less than 100 microns; a second element having a second surface with a second insulating region and a second contact structure, wherein the first insulating region is directly bonded to the second insulating region and the first contact structure is directly bonded to the second contact structure; and a third element directly bonded to the first element, wherein the third element has a thickness greater than the thickness of the first element and wherein a difference in coefficient of thermal expansion (CTE) between a base material of the third element and a base material of the first element is less than 1.0 ppm/ C., wherein the first element is vertically between the second element and the third element.

2. The bonded structure of claim 1, wherein the thickness of the third element is between about 0.5 mm-0.8 mm.

3. The bonded structure of claim 1, wherein the CTE difference is less than 0.5 ppm/ C.

4. The bonded structure of claim 3, wherein the CTE difference is less than 0.3 ppm/ C.

5. The bonded structure of claim 1, wherein at least one of the first and second elements has a conductive via extending at least partially through the element and electrically connected to the contact structures.

6. The bonded structure of claim 5, wherein each of the first and second elements has a plurality of conductive vias, and the conductive vias of the first element are aligned with the conductive vias of the second element.

7. The bonded structure of claim 5, wherein the conductive via extends through most or all of the thickness of the element.

8. The bonded structure of claim 1, wherein at least one of the first and second insulating regions comprises silicon oxide.

9. The bonded structure of claim 1, wherein the base material of the second element comprises a silicon substrate.

10. A bonded structure comprising: a first element having a first thinned semiconductor portion and a first direct bonding layer on the first thinned semiconductor portion, the first direct bonding layer comprising a first insulating portion and a first metal portion, the first thinned semiconductor portion having a thickness less than 100 microns; a second element having a second semiconductor portion and a second direct bonding layer on the second semiconductor portion, the second direct bonding layer comprising a second insulating portion directly bonded to the first insulating portion and a second metal portion directly bonded to the first metal portion; and a third element directly bonded to the first element, the third element having a thickness greater than the first element, and wherein a difference in coefficient of thermal expansion (CTE) between a third semiconductor portion of the third element and the second semiconductor portion of the second element is less than 1.0 ppm/ C., wherein a first plurality of conductive vias extend at least partially through the first element or the second element, wherein the second element and the third element are disposed on opposing sides of the first element.

11. The bonded structure of claim 10, wherein the first plurality of conductive vias extend at least partially through the first thinned semiconductor portion of the first element and are electrically connected to the first direct bonding layer, and wherein a second plurality of conductive vias extend at least partially through the second semiconductor portion and are electrically connected to the second direct bonding layer.

12. The bonded structure of claim 11, wherein the first plurality of conductive vias extend mostly or entirely through the first element and wherein the second plurality of conductive vias extend mostly or entirely through the second element.

13. The bonded structure of claim 12, wherein the first plurality of conductive vias are aligned with the second plurality of conductive vias.

14. The bonded structure of claim 10, wherein the third element has a thickness in a range of 0.5 mm to 0.8 mm.

15. The bonded structure of claim 10, wherein the first thinned semiconductor portion has a thickness in a range of 10 microns to 100 microns.

16. The bonded structure of claim 9, wherein a coefficient of thermal expansion (CTE) of the second semiconductor portion of the second element is substantially the same as a CTE of the third semiconductor portion of the third element.

17. The bonded structure of claim 9, wherein at least one of the first and second insulating portions comprises silicon oxide.

18. A bonded structure comprising: a first element having a first thinned semiconductor portion, a first direct bonding layer on the first thinned semiconductor portion, and a first plurality of conductive vias extending at least partially through the first thinned semiconductor portion and electrically connected to the first direct bonding layer, the first direct bonding layer comprising a first insulating portion and a first metal portion, the first thinned semiconductor portion having a thickness in a range of 10 microns to 100 microns; a second element having a second semiconductor portion, a second direct bonding layer on the second semiconductor portion, and a second plurality of conductive vias extending at least partially through the second semiconductor portion and electrically connected to the second direct bonding layer, the second direct bonding layer comprising a second insulating portion directly bonded to the first insulating portion and a second metal portion directly bonded to the first metal portion; and a third element directly bonded to the first element, wherein the third element has a thickness in a range of 0.5 mm to 0.8 mm, and wherein a coefficient of thermal expansion (CTE) of the second semiconductor portion is substantially the same as a CTE of a third semiconductor portion of the third element, wherein the second element and the third element are disposed on opposing sides of the first element.

19. The bonded structure of claim 18, wherein the first plurality of conductive vias are aligned with the second plurality of conductive vias.

20. The bonded structure of claim 18, wherein at least one of the first and second insulating portions comprises silicon oxide.

21. The bonded structure of claim 18, wherein the first thinned semiconductor portion has a thickness in a range of 10 microns to 100 microns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A more complete appreciation of the present invention and many attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

(2) FIG. 1 is a diagram of two wafers with a major portion and a direct metal bond portion.

(3) FIG. 2 is a diagram of two wafers with a major portion and a direct metal bond portion aligned and placed together forming a bond interface.

(4) FIG. 3 is a diagram of two wafers with a major portion and a direct metal bond portion aligned and placed together forming a bond interface with a substantial portion of the major portion of one of the two wafers removed resulting in a thinned portion of a direct metal bonded pair.

(5) FIG. 4 is a diagram of a stiffening wafer attached to the thinned portion of a direct metal bonded pair.

(6) FIG. 5 is a diagram of a thinned portion of a direct metal bonded pair after removal of a stiffening wafer.

(7) FIG. 6 is a diagram of a second embodiment including filled vias.

(8) FIG. 7 is a diagram of two wafers bonded each having filled vias.

(9) FIG. 8 is a diagram of showing the structure of FIG. 7 with the vias exposed.

(10) FIG. 9 shows the attachment of an additional substrate to the structure of FIG. 8.

(11) FIGS. 10A-10C are detailed views of the metal bonding region.

(12) FIG. 11 is a diagram of a wafer bonded with a clamp.

(13) FIG. 12 is another diagram of a wafer bonded with a clamp.

(14) FIG. 13 is a diagram of bonding using a flexible container.

(15) FIG. 14 is a diagram of applying pressure to the flexible container of FIG. 13.

(16) FIG. 15 is a diagram of bonding using a flexible container.

(17) FIG. 16 is a diagram of applying pressure to the flexible container of FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(18) Referring now to the drawings, in particular FIG. 1, a first embodiment of the method according to the invention will be described. It is noted here that the drawings are not drawn to scale but are drawn to illustrate the concepts of the invention.

(19) Two wafers, 1 and 2 are prepared for bonding. The wafers are of different material, and have different CTE. Wafer 2 includes a major portion 6 and a direct metal bond portion 5. Direct metal bond portion 5 has a surface with insulating and metal portions. The insulating portions are preferably an oxide or nitride, and more preferably a silicon oxide or silicon nitride. The portion 5 is shown in more detail in FIGS. 10A-10C. Metal pads 20 may be below, flush or above the oxide or nitride material 21 depending upon the process conditions and desired configuration. In the case where chemo-mechanical polishing is used on the surface, the metal pads can be dished and have a surface below the surface of the oxide or nitride material or the oxide or nitride material can be dished and have a surface below the surface of the metal pads.

(20) Major portion 6 can include substrate, device, and interconnect portions that are, for example, found in industry standard manufactured semiconductor wafers, such as CMOS wafers that typically are manufactured with a copper or aluminum back-end-of-line process. Wafer 1 includes a major portion 3 and a direct metal bond portion 4. Major portion 3 can include substrate, device, and contact portions that are, for example, found in industry standard gallium nitride-based hetero-epitaxial device structures grown on sapphire (GaN/sapphire) that have contacts formed to the hetero-epitaxial material.

(21) Wafer 1 and wafer 2 are direct metal bonded as described in application Ser. Nos. 09/505,283, 10/359,608 and 11/201,321, as shown in FIG. 2. If the surfaces of metal portions are below the surfaces of insulating portions, only the insulating portions may be in direct contact at interface 7 after the wafers are first placed into contact. The bonded wafers may then be heated to increase the bond energy between the bonded insulating portions, but not at too high a temperature for CTE induced strain to break the bond between the insulating portions or break the bonded wafers. The optimum temperature to increase bond energy will depend on the CTE difference and thickness of the wafers bonded. For example, when bonding a GaN/sapphire structure of approximate range 500-1000 micron sapphire thickness to silicon CMOS of approximate range 500-750 micron thickness, a temperature in the range of 75-150 C. may be preferable to achieve a bond energy of greater than 1 J/m.sup.2 and preferably greater than 2 J/m.sup.2. Higher temperatures are possible if a thinner material is used or materials with a lower CTE difference are used to facilitate achieving even higher bond energies greater 2.5 J/m.sup.2. Although this temperature range can be sufficient to achieve a very high bond energy, it may not be sufficient to form 3D interconnections depending on the relative height of the metal and insulating portions and the type of metal used. For example, if copper is used, a temperature range of 150-250 C. may be required if the copper is 0-10 nm below a silicon oxide insulating portion. Alternatively, if nickel is used, a 250-350 C. temperature range may be required to make 3D interconnections if the nickel is 0-10 nm below a silicon oxide insulating portion. The lower temperature range requirement of the copper compared to the nickel is an example of where the type of metal can affect the temperature range wherein the higher expansion coefficient of copper (17 ppm/ C.) compared to that of nickel (13 ppm/ C.) results in more expansion at a given temperature resulting in a lower temperature range for a given difference in height between the metal and insulating portions of the bond surface Higher temperatures may thus be required to facilitate electrical interconnections while higher temperatures may not be possible with this configuration of bonded wafers due to CTE induced strain that would break the bond between the insulating portions or break the bonded wafers.

(22) Major portion 3 is then thinned as shown in FIG. 3 to form thinned layer 8 having a thickness typically in the range of 1-10 microns. The thickness of layer 8 may be outside this range depending upon the application and materials. For example, bonded material combinations with a low CTE mismatch of <2 ppm/ C. may allow a thicker layer 8 in the range of 10-100 microns and applications requiring the transfer of layers less than one micron may use a thinner layer 8 of 0.10-1.0 microns. Thinning may include one or a combination of backgrinding, polishing, etching, or laser liftoff. For example, if wafer 2 is a GaN/sapphire structure, laser liftoff can be used to remove the sapphire resulting in a very thin GaN device layer with metal contact portions. The thinned layer 8 allows heating to a higher temperature without breaking the bond between the insulating portions or breaking the bonded wafers due to increased compliance or elasticity. The allowed increased temperature depends on the materials and the reduced thickness of layer 8. For example, temperatures in excess of 350 C., for example 350 C. to 400 C., can be enabled by this thinning for bonded material that have a high CTE mismatch of 2-5 ppm/ C. and a layer 8 thickness of 2-20 microns. This increased temperature range enabled by reduced layer 8 thickness may be suitable to enable 3D interconnections or for other processing, for example oxide deposition or annealing. It is not necessary to use the full extent of this increased temperature range for other processing. For example, other processing below the maximum increased temperature range that is higher than that allowed prior to increasing the temperature range is possible.

(23) In some cases, layer 8 may be too thin to provide adequate stiffness to produce adequate compression between metal portions at the surface of wafers 1 and 2 to form reliable 3D interconnections if wafers are heated to facilitate electrical interconnections. For example, if layer 8 is in the range of 1 to 10 microns thick, with an upper portion of this layer, for example 0.2 to 2.0 microns, comprising a heterogeneous combination of insulative and conductive bonding material, considerable stress normal to the bond interface in the vicinity of the interface between the insulating and conductive bonding material can be generated at low temperatures, for example less than 300 C., due to the CTE difference between insulative and conductive bonding material. This normal stress can distort the thin layer, resulting in less compressive force between metal portions and preventing electrical interconnections across the bond interface. This distortion results from a CTE mismatch induced extrusion of the conductive bonding material relative to the insulating bonding material at the thinned surface that is not constrained by the thinned layer due to the reduced stiffness of the thinned layer compared to that without partial or total removal of the substrate.

(24) This reduced stiffness can be compensated by bonding a third wafer 9 to thinned major portion 8 to reduce or prevent the distortion of layer 8 and enable adequate compression between metal portions at the surface of wafers 1 and 2 to form 3D interconnections with heating after the bonding of third wafer 9 as shown in FIG. 4. The minimum thickness of third wafer 9 required can be determined experimentally, however, this thickness will typically be less than a standard wafer thickness, for example 50-100 microns for 100-300 mm diameter wafers with standard thickness of about 0.5-0.8 mm as the stiffness is increased substantially with relatively small thickness being dependent on the cube of the thickness of third wafer 9. A reduced thickness of third wafer 9 may be obtained by thinning third wafer 9 before or after attaching. A wafer 9 thickness larger than the minimum thickness, for example a standard wafer thickness, may also be used.

(25) The attachment of third wafer 9 can be with a variety of methods, for example with a direct bond, as described in application Ser. No. 09/505,283, or a clamp 15 as shown in FIG. 11. If with a direct bond, the attachment may include the addition of bonding layers on wafer 9 and/or thinned portion 8. If with a clamp, clamp 15 is shown in FIG. 11 with the external pressure applied to both sides of wafer stack represented by the arrows. This can be done by applying external pressure from both sides as shown in FIG. 11 or by applying external pressure from one side with opposing side restrained by a chuck 16 as shown in FIG. 12. Third wafer 9 preferably has a CTE comparable to wafer 2 to prevent excessive stress during subsequent heating to form 3D interconnections. For example, if wafer 1 is GaN/sapphire, and wafer 2 is silicon CMOS, third wafer 9 can be silicon. The workable range of the difference in CTE depends on the materials, their area and their thicknesses. For example, when bonding 200 mm diameter silicon wafers and using silicon oxide and copper as insulating and conductive bond materials, respectively, it is preferable to have a difference in CTE less than 0.5 ppm/ C. When working with larger wafers, for example 300 mm wafers, it is preferable to have a smaller difference in CTE less than 0.3 ppm/ C. and when working with smaller wafers, for example 200 mm wafers, it is possible to have a larger difference in CTE less than 1.0 ppm/ C. When working with bond materials with a smaller difference in CTE, for example silicon oxide and nickel, it is preferable to have wafers with a smaller difference in CTE to allow for relatively more heating.

(26) A flexible clamping arrangement as shown in FIGS. 13-16, can be used to assist in holding the bonded wafers together during heating while in addition accommodating bowing of the wafers which will naturally occur during heating due to the CTE difference of the wafers. This method can be applied to the first bond of two wafers of FIG. 2 with different CTEs (shown with flexible clamp methods in FIGS. 13 and 14), and also to the 3 layer stack of FIG. 4 with two thick CTE matched materials bonded to the thinner layer of different CTE material sandwiched between the two thicker layers (shown with flexible clamp methods in FIGS. 15 and 16). The flexible clamping arrangement consists of 2 layers of flexible material, for example a silicone rubber sheet, enclosing the bonded materials, and sealed at the edges forming a sealed envelope 16. The material used must be able to withstand the temperature that is to be applied to the bonded layers. Pressure is applied either by evacuating the space within the flexible material envelope, thus applying atmospheric pressure evenly around the outside of the structure (FIGS. 13, 15), and/or by putting the flexible envelope and its contents into a high pressure chamber 17, and applying the desired pressure evenly around the envelope and its contents to compress the layers together (FIGS. 14, 16). In both cases, heat is then applied to the envelope and its contents to strengthen the bond(s) while bowing of the bonded stack is allowed to accommodate CTE mismatch and prevent breaking of the layers.

(27) The bonded stack of wafers 1, 2, and 3 shown in FIG. 4 can then be heated to higher temperatures than previously to form 3D interconnections if interconnections have not already been made due to a lack of temperature. For example, 300-350 C. may be required if wafer 1 is GaN/sapphire, wafer 2 is silicon CMOS, wafer 3 is silicon, and the metal is nickel. This ability to heat to a higher temperature has been enabled by replacing a major portion of wafer 2 that is CTE mis-matched to wafer 1 with wafer 9 that is CTE matched to wafer 1. These higher temperatures are now possible to facilitate electrical interconnections with higher temperatures due to this reduction in CTE mis-match. These higher temperatures were previously not possible due to CTE induced strain that would break the bond between the insulating portions or break the bonded wafers.

(28) After heating, wafer 3 can be removed as shown in FIG. 5, to leave portion 10. Portion 10 may be essentially thinned portion 8 or may be thicker, for example if a bonding layer portion of wafer 9 is not removed or may be thinner, for example if a bonding layer portion of thinned portion 8 is removed. Removal can be with a variety of methods, for example, one or a combination of backgrinding, chemo-mechanical polishing, or etching. Such techniques may be used when wafer 3 is silicon. Wafer 3 may also not be removed, for example if wafer 3 has a useful function, for example as part of a packaging function.

(29) A second embodiment of the method according to the invention will now be described. Either one or both of wafer 11 and wafer 12 may contain a via or vias 13 filled with metal that extend through all, most, or a portion of either one or both of wafer 11 and wafer 12, respectively as shown in FIGS. 6 and 7 for filled vias 13 and 14 that extend through about half of wafer 11 and wafer 12, respectively, and at a larger pitch than the conductive material at the bond interface. The vias may be electrically connected to the conductive material at the bond interface. If both wafer 11 and wafer 12 have filled vias, the filled vias may be opposed during the alignment and placement of wafer 1 and wafer 2 together as shown for filled vias 13 and 14, respectively. Vias 13 and 14 may also be not opposed.

(30) After wafer 12 is thinned, vias may be exposed as shown in FIG. 8 or may have a very thin residual portion of wafer 1 preventing exposure. For example, the residual wafer 12 thickness may be less than 100 microns. Heating of the structure in FIG. 8 or a similar structure with residual portion on filled vias will result in additional vertical and horizontal stress than described previously for the metal bonding due to the expansion coefficient difference between the filled vias surrounding material. The lack of a wafer 3 to inhibit relaxation of this stress can distort the direct metal bond interface and prevent proper bonding. The attachment or bonding of a wafer 15 as shown in FIG. 9 can inhibit relaxation of this stress and mitigate distortion of the metal bond interface and promote 3D electrical interconnections across the metal bond interface. As in embodiment 1, this wafer 15 is preferably made from material with a CTE match to that of wafer 11.

(31) Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.