Method for making III-V nanowire quantum well transistor

Abstract

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

Claims

1. A field-effect transistor, comprising: a semiconductor substrate; a germanium nanowire; a first III-V compound layer surrounding around said germanium nanowire; a barrier layer, a gate dielectric layer, and a gate electrode sequentially on said first III-V compound layer; and a source region and a drain region on said first III-V compound layer and at one side of said gate electrode respectively.

2. The field-effect transistor according to claim 1, wherein said germanium nanowires are doped with P type impurities, cross sections of said germanium nanowires are circular shapes, and the thickness of said germanium nanowires are 10 nm100 nm.

3. The field-effect transistor according to claim 1, wherein said first III-V compound layer is N type InGaAs, and the thickness of said first III-V compound layer is 10 nm100 nm.

4. The field-effect transistor according to claim 1, wherein said barrier layer is silicon doped InP, and the InP doping concentration is 1.010.sup.18 cm.sup.31.510.sup.18 cm.sup.3, the thickness of said barrier layer is 50 nm100 nm.

5. The field-effect transistor according to claim 1, wherein said gate dielectric layer is high dielectric constant materials, said gate dielectric layer is Al.sub.2O.sub.3, or TiSiO.sub.x, and the thickness of said gate dielectric layers is 1 nm5 nm.

6. The field-effect transistor according to claim 1, wherein said gate electrode is a material of TiN, NiAu or CrAu.

7. The field-effect transistor according to claim 1, wherein said source region and said drain region comprise In.sub.0.25Ga.sub.0.75As doped with N-type impurities.

8. The field-effect transistor according to claim 1, wherein said field effect transistor further comprises sidewalls at two sides of said gate electrode, a source electrode on said source region, and a drain electrode on said drain region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:

(2) FIG. 1 is a cross-sectional view of a field-effect transistor according to one embodiment of the present invention;

(3) FIG. 2 is a flowchart of a method for manufacturing a field-effect transistor according to one embodiment of the present invention;

(4) FIGS. 3a-3m are respectively cross-sectional views for manufacturing a field-effect transistor according to one embodiment of the present invention;

(5) FIG. 4 is an energy band diagram of a non-biased field-effect transistor according to one embodiment of the present invention;

(6) FIG. 5 is an energy band diagram of a forward-biased N-type field-effect transistor according to one embodiment of the present invention.

DETAILED DESCRIPTION

(7) For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features. Persons having ordinary skill in the art will understand other varieties for implementing example embodiments, including those described herein.

(8) The main idea of the present invention is to provide a field-effect transistor and method of making it. The germanium nanowire and the first III-V compound layer form a channel of the III-V/germanium quantum well, a width of a band gap of the barrier layer is wider than a width of a band gap of the first III-V compound layer, and a curvature of the band gap of the barrier layer is different than a curvature of the band gap of the first III-V compound layer, therefore, two dimensional electron gas (2DEG) is accumulated between the first III-V compound layer and the barrier layer. Since the 2DEG with higher mobility are used as the majority carriers of the field effect transistors, the transmission performance of the field-effect transistor can be enhanced substantially. Further, the field-effect transistor is a gate-all-around dielectric device that also increases its electrical performance.

(9) Reference is now made to the following description taken in conjunction with the accompanying drawings. The invention application provides a field-effect transistor shown in FIG. 1, this field-effect transistor includes a semiconductor substrate 100, a germanium nanowire 211 on the semiconductor substrate 100, a first III-V compound layer 212 surrounding around the first germanium nanowire 211, a barrier layer 220, a gate dielectric layer 231, and a gate electrode 232 sequentially formed on the first III-V compound layer 212, a source region 241 and a drain region 242 are also on the a first gate dielectric layer 231, and located at each side of the gate electrode 232 respectively.

(10) In one embodiment, the germanium nanowire 211 is doped with P-type impurities, and the cross section of the germanium nanowire 211 is round with diameter of 10 nm100 nm. The first III-V compound layer 212 is N-type InGaAs with a thickness of 10 nm100 nm. The germanium nanowire 211 and the first III-V compound layer 212 form a channel 210 of the N-type field effect transistor, that is, the channel of III-V/germanium quantum well transistor.

(11) The material of the barrier layer 220 is silicon doped InP, and the InP doping concentration is 1.010.sup.18 cm.sup.31.510.sup.18 cm.sup.3. The thickness of the barrier layer 220 is 50 nm100 nm. A heterojunction structure of the field-effect transistor is formed between the barrier layer 220 and the first III-V compound layer 212, a width of a band gap of the barrier layer is wider than a width of a band gap of the first III-V compound layer, and a curvature of the band gap of the barrier layer is different than a curvature of the band gap of the first III-V compound layer when biased on the gate electrode, therefore, two dimensional electron gas (2DEG) is accumulated between the first III-V compound layer 212 and the barrier layer 220. Since the 2DEG with higher mobility are used as the majority carriers of the field effect transistors, the transmission performance of the field-effect transistor can be enhanced substantially.

(12) The gate dielectric layer 231 is a high dielectric constant (K) material, and the thickness of the gate dielectric layer 231 is 1 nm5 nm. The material of the gate 232 is chosen from TiN, NiAu, and CrAu. The gate dielectric layer 231 and the gate electrode 232 form a gate of field-effect transistor 230. It should be noted that the field-effect transistor is entirely surrounded by gates to enhance the electrical performance of the field-effect transistor.

(13) In one embodiment, the field effect transistor is an N-type field-effect transistor. The source region 241 and drain region 242 are In.sub.0.25Ga.sub.0.75As doped by N-type impurities. The N-type field-effect transistor further comprises sidewalls 250 positioned at two opposite sides of the gate electrode 232, a source electrode 261 on the source region 241, and a drain electrode 262 on the drain region 242. The sidewalls 250 are silicon dioxide or silicon nitride to protect the gate electrode 232.

(14) The present invention further provides a method for manufacturing a field-effect transistor. FIG. 2 is a flowchart for manufacturing a field-effect transistor, wherein FIGS. 3a3m are cross-sectional views of the field-effect transistor during the manufacture process of the field-effect transistor. The method for manufacturing the field-effect transistor is described below.

(15) S1 to S6 steps are shown in FIG. 2. In S1 step, providing a semiconductor substrate 100, several trenches, germanium nanowires, wherein the trenches are disposed in the semiconductor substrate 100, and the germanium nanowires are floated above these trenches.

(16) The detail contents of S1 step are shown in FIGS. 3a-3g. Referring to FIG. 3a, the semiconductor substrate 100 is covered with a silicon germanium alloy layer 110.

(17) Referring to FIG. 3b, a plurality of shallow trench isolations 120 are formed in the semiconductor substrate 100, and the plurality of shallow trench isolations 120 are spaced apart and the silicon germanium alloy layer 110 is segmented by the shallow trench isolations 120.

(18) Referring to FIG. 3c, a part of each shallow trench 120 is removed, and sidewalls of the silicon germanium alloy layer 110 are exposed.

(19) Referring to FIG. 3d, the silicon germanium alloy layer 110 can become a polygon shaped silicon germanium alloy layer via a selective epitaxial growth because growth rates of the silicon germanium alloy layer 110 in all crystal orientations are not the same. For example, the silicon germanium alloy layer 110 can become a hexagon shaped silicon germanium alloy layer via the selective epitaxial growth. It is convenient to oxidize the polygon shaped silicon germanium alloy layer to form a germanium nanowire.

(20) Referring to FIG. 3e, the polygon shaped silicon germanium alloy layer 110 is transferred to a silicon oxide layer 130, wherein the silicon oxide layer 130 surrounds around the germanium nanowire 211. During the thermal oxidation, silicon and germanium are oxidized and concentrated to become the germanium nanowire 211. In one embodiment, the cross sections of the germanium nanowire 211 are circular shapes, and the diameters of the germanium nanowire 211 are 10 nm100 nm. Moreover, the silicon oxide layer 130 is covered with the semiconductor substrate 100 during the thermal oxidation.

(21) Referring to FIG. 3f, several trenches (not shown in the figure) are formed via removing the silicon oxide layer 130, and the germanium nanowires 211 are floated in the trenches. The germanium nanowires 211 are annealed at a hydrogen atmosphere so that the surfaces of the germanium nanowires 211 become smoother.

(22) Referring to FIG. 3g, another silicon oxide layer 150 is formed in the trenches in order to protect the semiconductor substrate 100 from damage during subsequent processes.

(23) S2 step is shown in FIGS. 3h and 3i, and FIG. 3i is a cross-sectional view of FIG. 3h along a AA direction. Forming the first III-V compound layer 212, and the second III-V compound layer 270, wherein the first III-V compound layer 212 and the second III-V compound layer 270 surrounded around the germanium nanowire 211 sequentially. In one embodiment, the first III-V compound layer 212 is manufactured by atomic layer deposition (ALD), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD). The materials of the first III-V compound layer 212 is N type InGaAs. The second III-V compound layer 270 is manufactured by MOCVD, ALD, or MBE. The materials of the second III-V compound layer 270 is In.sub.0.25Ga.sub.0.75As. The thickness of the first III-V compound layer 212 and the second III-V compound layer 270 is 10 nm200 nm.

(24) S3 step is shown in FIG. 3j. Etching the second III-V compound layer 270 to form an opening 280, wherein the first III-V compound layer 212 is exposed in the opening 280. The second III-V compound layer 270 is etched by induced coupling plasma (ICP).

(25) S4 step is shown in FIG. 3k. Sequentially forming a barrier layer 220, a gate dielectric layer 231, and a gate layer 232 in the opening 280. In one embodiment, the barrier layer 220 can be formed by the MOCVD, ALD, or MBE techniques. The materials of the barrier layer 220 is silicon doped InP, and the doping concentration of the barrier layer 220 is 1.010.sup.18 cm.sup.31.510.sup.18 cm.sup.3. The thickness of the barrier layer 220 is 50 nm100 nm. The gate dielectric layer 231 is manufactured by MOCVD, ALD, or MBE, and the gate dielectric layer 231 is high dielectric constant (high k) materials. For example, a material of the gate dielectric layer 231 is Al.sub.2O.sub.3 or TiSiO.sub.x, and a thickness of the gate dielectric layer 231 is 1 nm-5 nm. The gate layer 232 is manufactured by physical vapor deposition (PVD), MOCVD, ALD, or MBE, and a material of the gate layer 232 is TiN, NiAu or CrAu. The barrier layer 220, the gate dielectric layer 231, and the gate layer 232 are entirely surrounded around the channel 210. The field-effect transistor of the present invention is a gate-all-around dielectric device that increases its electrical performance.

(26) Referring to FIG. 3l, etching a portion of the gate layer 232, the gate dielectric layer 231, and the barrier layer 220, retaining the gate layer 232, the gate dielectric layer 231, and the barrier layer 220 inside the opening 280 as well as a portion on the second III-V compound layer 270. In one embodiment, the barrier layer 220 is used to adjust the density of 2DEG in the first III-V compound layer 212, therefore, it cam control the working current of the field effect transistor.

(27) S5 step is shown FIG. 3m. Forming the sidewalls 250 at two sides of the gate layer 232 on the second III-V compound layer 270, wherein the sidewalls 250 are sued to protect the gate electrode 230.

(28) S6 step is shown in FIG. 4. Forming the source region 241 and the drain region 242 by implanting N type impurities into the second III-V compound layer 270. According to the present invention, a simple method for manufacturing a source and a drain can form a nonplanar field effect transistor having a smaller parasitic resistance. Moreover, the method for manufacturing a field-effect transistor further comprises a step of forming the source electrode 261 on the source region 241, a step of forming the drain electrode 262 on the drain region 242. A material of the source electrode 261 and the drain electrode 262 is TiN, NiAu or CrAu.

(29) Referring to FIG. 4, when an input port (IN) is not biased, energy bands of the field effect transistor are not bent. Referring to FIG. 5, when the input port (IN) is forward biased, a width of a band gap of the barrier layer 220 is wider than a width of a band gap of the first III-V compound layer 212, and a curvature of the band gap of the barrier layer 220 is different than a curvature of the band gap of the first III-V compound layer 212. Moreover, when the input port (IN) is forward biased, a conduction band (Ec) drops below Fermi energy level (Ef) and two-dimensional electron gas (2DEG) is accumulated between the first III-V compound layer 212 and the barrier layer 220, the field effect transistor is turn on, and the output port (OUT) is coupled with a ground (GND). According to the present invention, 2DEG with higher mobility are used as the majority carriers of the field effect transistors, such that the transmission performance of the field-effect transistor can be enhanced substantially.

(30) In conclusion, a width of a band gap of the barrier layer is wider than a width of a band gap of the first III-V compound layer, and a curvature of the band gap of the barrier layer is different than a curvature of the band gap of the first III-V compound layer, therefore, two-dimensional electron gas (2DEG) is accumulated between the first III-V compound layer and the barrier layer. Since the 2DEG with higher mobility are used as the majority carriers of the field effect transistors, the transmission performance of the field-effect transistor can be enhanced substantially. Further, the field-effect transistor is a gate-all-around dielectric device that also increases its electrical performance.

(31) While various embodiments in accordance with the disclosed principles been described above, it should be understood that they are presented by way of example only, and are not limiting. Thus, the breadth and scope of exemplary embodiment(s) should not be limited by any of the above-described embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.

(32) Additionally, the section headings herein are provided for consistency with the suggestions under 37 C.F.R. 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically, a description of a technology in the Background is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Furthermore, any reference in this disclosure to invention in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings herein.