ARRAY SUBSTRATE OF DISPLAY PANEL

Abstract

An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region.

Claims

1. A display, comprising: a substrate; a gate line disposed on the substrate and extending along a first direction; a data line disposed on the substrate and intersecting with the gate line; a semiconducting layer disposed on the substrate, wherein the semiconducting layer has an enlarging portion, an joint portion, a channel portion and a turning portion, wherein the enlarging portion is electrically connected to the data line through a first via, the channel portion is overlapping with the gate line, the joint portion is between the enlarging portion and the channel portion, the channel portion is between the joint portion and the turning portion, wherein at least a part of the enlarging portion and at least a part of the joint portion are overlapping with the data line, wherein the joint portion has a first edge, the first edge is overlapping with the data line, and at least a part of the first edge is curved.

2. The display according to claim 1, wherein the data line has an overlapping region overlapping with the gate line, and at least a part of the overlapping region is overlapping with the channel portion.

3. The display according to claim 2, wherein, in the first direction, a width of the first via is greater than a width of the overlapping region.

4. The display according to claim 2, wherein the semiconducting layer is electrically connected to a drain by a second via, and, in the first direction, a width of the second via is greater than a width of the overlapping region.

5. The display according to claim 2, wherein the data line further comprise a connecting region and an intermediate region, the connecting region is overlapping with the enlarging portion, and the intermediate region is between the connecting region and the overlapping region, wherein the intermediate region is partially overlapping with the joint portion.

6. The display according to claim 5, wherein the intermediate region has a second edge, and at least a part of the second edge is curved.

7. The display according to claim 6, wherein gate line has a third edge, and the second edge is not perpendicular to the third edge.

8. The display according to claim 1, wherein, in the first direction, a width of the enlarging portion is greater than a width of the data line.

9. The display according to claim 1, wherein the semiconducting layer is electrically connected to a drain by a second via, and, in a direction perpendicular to the first direction, a distance between the first via and the gate line is greater than a distance between the second via and the gate line.

10. The display according to claim 1, wherein gate line has a third edge, and the first edge is not perpendicular to the third edge.

11. The display according to claim 1, wherein the semiconducting layer is in a form of L-shape or U-shape.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates a display panel according to an embodiment of the disclosure.

[0011] FIG. 2 is a top view of an array substrate of a display panel according to an embodiment of the disclosure.

[0012] FIG. 3 illustrates a bottom view of parts of the array substrate of a display panel according to an embodiment of the disclosure.

[0013] FIG. 4A is an enlarging view of the first transistor of FIG. 3, which labels the denotations of the related edges of the first lateral portion and turning portion.

[0014] FIG. 4B is an enlarging view of the first transistor of FIG. 3, which labels the denotations of the related edges of the second lateral portion and the turning portion.

[0015] FIG. 5 illustrates a bottom view of another part of the array substrate of a display panel according to the first embodiment of the disclosure.

[0016] FIG. 6 is a simple drawing of a semiconducting layer of a transistor.

[0017] FIG. 7 illustrates a bottom view of a part of an array substrate of a display panel according to the second embodiment of the disclosure.

[0018] FIG. 8 shows how to measure the curvatures of the inner and outer edges of the turning portion of FIG. 7.

DETAILED DESCRIPTION

[0019] In the embodiment of the present disclosure, an array substrate of a display panel is provided by forming a semiconducting layer with the particularly designed turning portion, thereby decreasing the resistance of the turning portion, and reducing resistance differences between the turning portion and the non-turning portion (linear portion). According to the disclosure, a semiconducting layer with uniform resistance can be obtained, and the display panel applied with the array substrate having the semiconducting layer of the embodiment can possess good electrical characteristics, thereby improving the reliability and the electrical performance of the display panel. Moreover, due to the particularly designed turning portion, the semiconducting layer of the embodiment would not be over-etched and broken easily after patterning procedure, thereby increasing the yield of production.

[0020] The embodiment of the present disclosure can be applied to an array substrate of a display panel, such as (but not limited to) an array substrate (thin-film-transistor substrate) of a low temperature polysilicon (LTPS) display panel.

[0021] The embodiments are described in details with reference to the accompanying drawings. It is noted that the details of the structures of the embodiments are provided for exemplification, and the described details of the embodiments are not intended to limit the present disclosure. The identical and/or similar elements of the embodiments are designated with the same and/or similar reference numerals. It is noted that not all embodiments of the invention are shown. Modifications and variations can be made without departing from the spirit of the disclosure to meet the requirements of the practical applications. Thus, there may be other embodiments of the present disclosure which are not specifically illustrated. Further, the accompany drawings are simplified for clear illustrations of the embodiment; sizes and proportions in the drawings are not directly proportional to actual products, and shall not be construed as limitations to the present disclosure. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense.

[0022] Moreover, use of ordinal terms such as first, second, third, etc., in the specification and claims to modify an element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.

[0023] FIG. 1 illustrates a display panel according to an embodiment of the disclosure. A display panel comprises a first substrate 11, a second substrate 12, and a display medium layer 13 disposed between the first substrate 11 and the second substrate 12. The first substrate 11 and the second substrate 12 can be a TFT substrate and a CF substrate, respectively. FIG. 2 is a top view of an array substrate of a display panel according to an embodiment of the disclosure. In FIG. 2, the array substrate has a plurality of gate lines GL and data lines DL intersecting to define pixels. Two adjacent gate lines GL and two adjacent data lines DL define one pixel PX. In one embodiment, each pixel has a first transistor T1 and a second transistor T2, and at least a drain D of one of the first transistor T1 and the second transistor T2 is coupled to the data line DL.

[0024] In order to reveal and describe the related elements of the embodiment, the accompanying drawings depict related elements from bottom views of an array substrate (such as TFT substrate) of the display panel.

[0025] FIG. 3 illustrates a bottom view of parts of the array substrate of a display panel according to an embodiment of the disclosure. The array substrate of the display panel of the embodiment can be a TFT substrate. In the embodiment, an array substrate comprises a substrate S1, a first transistor T1 and a second transistor T2 disposed on the substrate in series connection. The first transistor T1 and the second transistor T2 are electrically connected. Also, the first transistor T1 and the second transistor T2 share a semiconducting layer 100. In one embodiment, the semiconducting layer 100 is a polysilicon layer.

[0026] Relative positions of the first transistor T1 and the second transistor T2 can be optionally altered according to the requirements of circuit design in the practical applications. The pattern of the semiconducting layer 100 for connecting to the first transistor T1 and the second transistor T2 can be determined according to the positions of the first transistor T1 and the second transistor T2. For example, the semiconducting layer 100 can be in a form of L-shape or the like, or in a form of U-shape as shown in FIG. 3 or the like. The semiconducting layer 100 can be configured into other shape, as long as it accomplishes the connection between the first transistor T1 and the second transistor T2. According to the embodiment of the present disclosure, the semiconducting layer 100 with the turning portion is designed specifically to lower the resistance of the turning portion, thereby reducing resistance differences between the turning portion and the linear portion. Accordingly, the resistances of different sections of the semiconducting layer 100 can be closer, and the semiconducting layer 100 with uniform resistance is obtained.

[0027] In one embodiment, the semiconducting layer 100 at least includes a first lateral portion 110 extended from the first transistor T1 or the second transistor T2, a turning portion 101 connecting to the first lateral portion 110, and a bottom portion 130 connecting to the turning portion 101. FIG. 4A is an enlarging view of the first transistor of FIG. 3, which labels the denotations of the related edges of the first lateral portion 110 and turning portion 101. Please refer to FIG. 3 and FIG. 4A simultaneously.

[0028] According to the embodiment, a first outer edge extending line L1.sub.SO of the first lateral portion 110, a second outer edge extending line L.sub.BO of the bottom portion 130 and a third outer edge E.sub.CO of the turning portion 101 defines a first region A1. A first inner edge extending line L1.sub.SI of the first lateral portion 110, a second inner edge extending line L.sub.BI of the bottom portion 130 and a third inner edge E.sub.CI of the turning portion 101 defines a second region A2, as shown in FIG. 4A. In the embodiment, an area of the first region A1 is smaller than an area of the second region A2.

[0029] In one embodiment, a ratio of the area of the first region A1 to the area of the second region A2 is in a range of about 0.2 to about 0.7.

[0030] Moreover, according to the embodiment, the third inner edge E.sub.CI of the turning portion 101 is substantially non-parallel to the first inner edge E1.sub.SI of the first lateral portion 110 and also non-parallel to the second inner edge E.sub.BI of the bottom portion 130. The third outer edge ECO of the turning portion 101 is substantially non-parallel to the first outer edge E1.sub.SO of the first lateral portion 110 and also non-parallel to the second outer edge E.sub.BO of the bottom portion 130.

[0031] In one embodiment, the first lateral portion 110 is substantially perpendicular to the bottom portion 130. As shown in FIG. 3, the second inner edge E.sub.BI of the bottom portion 130 is substantially perpendicular to the first inner edge E1.sub.SI, of the first lateral portion 110, and the second outer edge E.sub.BO of the bottom portion 130 is substantially perpendicular to the first outer edge E1.sub.SO of the first lateral portion 110. Although configuration of the first lateral portion 110 and the bottom portion 130 presents an L-shape substantially, the disclosure is not limited thereto. The first lateral portion 110 and the bottom portion 130 can be arranged by varying an angle therebetween larger or smaller than 90 degrees. Configuration of the first lateral portion 110 and the bottom portion 130 can be optionally modified and altered depending on the positions of the first transistor T1 and the second transistor T2 and the setting condition of the semiconducting layer 100 in the practical applications.

[0032] Additionally, the semiconducting layer 100 of the embodiment as shown in FIG. 3 further comprises a second lateral portion 120, and the bottom portion 130 is positioned between the first lateral portion 110 and the second lateral portion 120. One end of the bottom portion 130 is connected to the turning portion 101, and the other end of the bottom portion 130 is connected to the second lateral portion 120 by the other turning portion 102.

[0033] FIG. 4B is an enlarging view of the first transistor of FIG. 3, which labels the denotations of the related edges of the second lateral portion 120 and the turning portion 102. Please refer to FIG. 3 and FIG. 4B simultaneously. Two ends of the turning portion 102 connect to the second lateral portion 120 and the bottom portion 130, respectively. In FIG. 3, the semiconducting layer 100, comprising the first lateral portion 110, the bottom portion 130 and the second lateral portion 120, is substantially, but not limitedly, in a form of U-shape. As shown in FIG. 4B, the second lateral portion 120 is substantially parallel to the first lateral portion 110. Accordingly, a fourth inner edge E2.sub.SI of the second lateral portion 120 is substantially parallel to the first inner edge E1.sub.SI of the first lateral portion 110, and a fourth outer edge E2.sub.SO of the second lateral portion 120 is substantially parallel to the first outer edge E1.sub.SO of the first lateral portion 110.

[0034] Also, the second lateral portion 120 is substantially perpendicular to the bottom portion 130. A second inner edge E.sub.BI of the bottom portion 130 is substantially perpendicular to the fourth inner edge E2.sub.SI of the second lateral portion 120, and a second outer edge E.sub.BO of the bottom portion 130 is substantially perpendicular to the fourth outer edge E2.sub.SO of the second lateral portion 120.

[0035] Similarly, a fourth outer edge extending line L2.sub.SO of the second lateral portion 120, a second outer edge extending line L.sub.BO of the bottom portion 130 and a third outer edge E.sub.CO of the turning portion 102 defines a third region A3. A fourth inner edge extending line L2.sub.SI of the second lateral portion 120, a second inner edge extending line L.sub.BI of the bottom portion 130 and a third inner edge E.sub.CI of the turning portion 102 defines a fourth region A4, as shown in FIG. 4B. In the embodiment, an area of the third region A3 is smaller than an area of the fourth region A4.

[0036] In one embodiment, a ratio (A3/A4) of the area of the third region A3 to the area of the fourth region A4 is in a range of about 0.2 to about 0.7. Also, the area of the first region A1 can be equal to or not equal to the area of the third region A3, and the area of the second region A2 can be equal to or not equal to the area of the fourth region A4.

[0037] FIG. 5 illustrates a bottom view of another part of the array substrate of a display panel according to the first embodiment of the disclosure. The identical elements of FIG. 5 and FIG. 3 are designated with the same reference numerals. According to a LTPS display panel applied with an array substrate of the embodiment, the first transistor T1 has a gate electrode GE, the first lateral portion 110 on the gate electrode GE has a first width W1, and the bottom portion 130 has a second width W2. In one embodiment, the first width W1 is smaller than the second width W2 (W1<W2). It is noted that the applicable embodiment is not limited to the configuration depicted in FIG. 5. In other embodiment, the first width W1 can be larger than the second width W2 (W1>W2). In one embodiment, the turning portion 101 has a third width W3, and the third width W3 is larger than (the first width W1.sup.2+the second width W2.sup.2).sup.0.5 (W3>{square root over (W1.sup.2+W2.sup.2)}).

[0038] Moreover, the semiconducting layer 100 comprises an enlarging portion 150, and the enlarging portion 150 has a fourth width W4, as shown in FIG. 5. In one embodiment, the enlarging portion 150 corresponds to the drain D of the first transistor T1. The semiconducting layer 100 has a joint portion 160 positioned between the first lateral portion 110 and the enlarging portion 150, and the joint portion 160 has a fifth width W5. In one embodiment, the fifth width W5 is larger than the first width W1 (W5>W1), and the fifth width W5 is smaller than the fourth width W4 (W5<W4).

[0039] In one embodiment, a second metal layer can be electrically connected to the enlarging portion 150 of the semiconducting layer 100 through a via 170. The via 170 may reveal an upper surface of the enlarging portion 150, or penetrate through the enlarging portion 150. As shown in FIG. 5, the via 170 has a width Wv, and the width Wv is smaller than the fourth width W4 of the enlarging portion 150 (Wv<W4).

[0040] FIG. 6 is a simple drawing of a semiconducting layer of a transistor. As described above, the first lateral portion 110 of the first transistor T1 has a first width W1, and the bottom portion 130 has a second width W2. If a triangle having two sides of the first width W1 and the second width W2 is drawn, the longest side Ws is equal to (the first width W1.sup.2+the second width W2.sup.2).sup.0.5 (Ws={square root over (W1.sup.2+W2.sup.2)}). In one embodiment, the third width W3 of the turning portion 101 is larger than (the first width W1.sup.2+the second width W2.sup.2).sup.0.5 (W3>{square root over (W1.sup.2+W2.sup.2)}). According to the embodiment, the third outer edge E.sub.CO of the turning portion 101 is less curving, while the third inner edge E.sub.CI of the turning portion 101 is more curving. When a voltage is applied to the display panel, the current tends to flow along the shortest path (i.e. the inner edge). Since the length of the third inner edge E.sub.CI (more curving) of the turning portion 101 is shorter than the inner edge E.sub.CI (i.e. the corner drawn by dashed lines, which is less curving), the embodied turning portion 101 having the third inner edge E.sub.CI does efficiently decrease the resistance. Also, the resistance of the turning portion 101 is typically larger than the resistance of the linear portions (such as the first lateral portion 110 and the second lateral portion 120). The width of the embodied turning portion 101 (with more curving inner edge and less-curving outer edge) is larger than the width of the conventional turning portion (with less-curving inner and outer edges), so that the resistance of the embodied turning portion is lower than the resistance of the conventional turning portion. Accordingly, the resistance differences between the embodied turning portion and the linear portion portions (such as the first lateral portion 110 and the second lateral portion 120) can be reduced, thereby obtaining a semiconducting layer 100 with more uniform resistances of different sections. Thus, the display panel applied with the array substrate having the semiconducting layer 100 of the embodiment can possess improved electrical characteristics and good reliability. Additionally, a mask for fabricating the semiconducting layer 100 of the embodiment is designed according to the pattern of the semiconducting layer 100 correspondingly. After fabricating through the mask lithography and etching, the semiconducting layer 100 of the embodiment is formed, particularly the semiconducting layer 100 having the embodied turning portion 101 with the more curving inner edge and the less-curving outer edge.

[0041] FIG. 7 illustrates a bottom view of a part of an array substrate of a display panel according to the second embodiment of the disclosure. The array substrate of the display panel of the embodiment can be a TFT substrate. The identical elements of FIG. 7 and FIG. 3 are designated with the same reference numerals. Also, it is known that the semiconducting layer 100 is not limited to the U-shaped configuration as depicted in the accompany drawings. The pattern of the semiconducting layer 100 for connecting to the first transistor T1 and the second transistor T2 can be adjusted and altered according to the conditions of the practical applications. The disclosure can be applied to various types of the semiconducting layers having turning portions.

[0042] In the second embodiment, an array substrate similarly comprises a substrate S1, a first transistor T1 and a second transistor T2 disposed on the substrate S1 in series connection. The first transistor T1 and the second transistor T2 are electrically connected and share a semiconducting layer 100 (such as a polysilicon layer). Similarly, the semiconducting layer 100 at least includes a first lateral portion 110 extended from the first transistor T1 or the second transistor T2, a turning portion 101 connecting to the first lateral portion 110, and a bottom portion 130 connecting to the turning portion 101.

[0043] The first embodiment is related to the design of the inner and outer edges of the turning portion 101 connecting to the first lateral portion 110, so as to form the first region A1 (defined by the outer edges) having the area smaller than the second region A2 (defined by the inner edges). The second embodiment is related to the curvature design of the inner and outer edges of the turning portion 101. Accordingly, the semiconducting layer of the second embodiment has the embodied turning portion 101 with the more curving inner edge and the less-curving outer edge, so as to achieve the result of resistance decrease.

[0044] As shown in FIG. 7, the third outer edge E.sub.CO of the turning portion 101 has a first curvature r1 (i.e. the reciprocal of the first radius of curvature R1, 1/R1), the third inner edge E.sub.CI of the turning portion 101 has a second curvature r2 (i.e. the reciprocal of the second radius of curvature R2, 1/R2). In the second embodiment, the first curvature r1 is larger than the second curvature r2, which means the first radius of curvature R1 is smaller than the second radius of curvature R2 (R1<R2). In one embodiment, a ratio of the first curvature r1 to the second curvature r2 (r1/r2) is in a range of about 1.1 to about 2.

[0045] In the practical applications, many different ways can be applied for measuring and obtaining the first curvature r1 and the second curvature r2 of the turning portion 101. One of applicable measurements is described below. Please refer to FIG. 8, which shows how to measure the curvatures of the inner and outer edges of the turning portion of FIG. 7.

[0046] First, the extending lines along the first lateral portion 110, such as the first outer edge extending line L1.sub.SO and the first inner edge extending line L1.sub.SI, are drawn. The extending lines along the bottom portion 130, such as the second outer edge extending line L.sub.BO and the second inner edge extending line L.sub.BI, are drawn.

[0047] Then, an outer arc C.sub.O can be determined according to a nearest contact point of the first outer edge extending line L1.sub.SO of the first lateral portion 110 and the turning portion 101 and a nearest contact point of the second outer edge extending line L.sub.BO of the bottom portion 130 and the turning portion 101. Similarly, an inner arc C.sub.I can be determined according to a nearest contact point of the first inner edge extending line L1.sub.SI, of the first lateral portion 110 and the turning portion 101 and a nearest contact point of the second inner edge extending line L.sub.BI of the bottom portion 130 and the turning portion 101.

[0048] Next, the perpendicular bisectors of any two chords are drawn, and the intersection of these two perpendicular bisectors is the center of the arc. As shown in FIG. 8, the center O.sub.O of the outer arc C.sub.O and the center O.sub.I of the inner arc C.sub.I are found. The distance between the center and the point of tangency is the radius of curvature. FIG. 8 depicts the first radius of curvature R1 and the second radius of curvature R2. Finding the radius of curvature R means finding the curvature r. The reciprocal of the radius of curvature R is the curvature r.

[0049] According to the aforementioned descriptions, an array substrate of a display panel is provided by forming a semiconducting layer with the particularly designed turning portion. In the embodiment, the inner and outer edges (i.e. the third outer edge E.sub.CO and the third inner edge E.sub.CI) of the turning portion 101 of the semiconducting layer 100 have different curving conditions. As described in the embodiments above, the turning portion 101 can be designed to form the first region A1 (defined by the outer edges) having the area smaller than the second region A2 (defined by the inner edges) (A2>A1) as described in the first embodiment, thereby decreasing the resistance of the turning portion. Alternatively, the turning portion 101 can be designed to form the embodied turning portion 101 with the more curving third inner edge E.sub.CI (i.e. smaller curvature r2) and the less-curving third outer edge E.sub.CO (i.e. larger curvature r1) as described in the second embodiment, thereby decreasing the resistance of the turning portion. Also, the resistance of the turning portion 101 is typically larger than the resistance of the linear portions (such as the first lateral portion 110 and the second lateral portion 120). The width of the embodied turning portion 101 (with more curving inner edge and less-curving outer edge) is larger than the width of the conventional turning portion (with less-curving inner and outer edges), so that the resistance of the embodied turning portion is lower than the resistance of the conventional turning portion. Accordingly, the resistance differences between the embodied turning portion and the linear portion portions (such as the first lateral portion 110 and the second lateral portion 120) can be reduced, thereby obtaining a semiconducting layer 100 with more uniform resistances of different sections. Thus, the display panel applied with the array substrate having the semiconducting layer 100 of the embodiment can possess improved electrical characteristics and good reliability. Moreover, due to the particularly designed turning portion, the semiconducting layer of the embodiment would not be over-etched and broken easily after patterning procedure, thereby increasing the yield of production.

[0050] While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.