Active-matrix substrate and display device

Abstract

In an active matrix substrate, each of at least two auxiliary capacitance electrodes contains a first electrode section and a second electrode section, at least a portion of the first electrode sections and at least a portion of a plurality of source bus lines overlap each other, the second electrode section has two linear sections that branch from the first electrode section and that extend in a second direction, a portion of the region between the two linear sections and at least a portion of the plurality of source bus lines overlap each other, and the first and second electrode sections, which are adjacent and arranged in a first direction, are disposed symmetrically to each other about a reference point that is on a straight line passing through a substantially central portion of respective pixels arranged in the first direction.

Claims

1. An active matrix substrate, comprising: a substrate; a plurality of gate bus lines that extend in a first direction on the substrate; a plurality of source bus lines that extend in a second direction that intersects said first direction on the substrate; a plurality of thin film transistors on the substrate that are respectively electrically connected to said plurality of gate bus lines and said plurality of source bus lines; a plurality of pixel electrodes on the substrate that are respectively electrically connected to drain electrodes of the plurality of thin film transistors and that are arranged in a matrix in the first and second directions; and, a plurality of an auxiliary capacitance bus lines that extend in said first direction, wherein at least one of the plurality of auxiliary capacitance bus lines has at least two auxiliary capacitance electrodes, wherein each of said at least two auxiliary capacitance electrodes includes a first electrode section and a second electrode section, wherein, in each of said at least two auxiliary capacitance electrodes, at least a portion of said first electrode section overlaps one of said plurality of source bus lines, wherein, in each of said at least two auxiliary capacitance electrodes, said second electrode section has two linear sections extending in said second direction, and at least a portion of a region between said two linear sections overlaps said one of said plurality of source bus lines, and wherein, in said at least one of the plurality of auxiliary capacitance bus lines, with respect to adjacent two of said at least two auxiliary capacitance electrodes, positions of said first electrode section and second electrode section in the second direction are alternated so as to be generally point-symmetric about a reference point on a straight line that passes through a central region of pixels arranged in the first direction along said at least one of the plurality of auxiliary capacitance bus lines.

2. The active matrix substrate according to claim 1, wherein said at least two auxiliary capacitance electrodes are disposed in a same layer as said plurality of gate bus lines.

3. The active matrix substrate according to claim 1, further comprising an insulating film disposed between said plurality of source bus lines and said plurality of pixel electrodes, wherein said insulating film is an inorganic insulating film.

4. The active matrix substrate according to claim 1, further comprising an insulating film disposed between said plurality of source bus lines and said plurality of pixel electrodes, wherein said insulating film is an organic insulating film.

5. The active matrix substrate according to claim 1, further comprising an insulating film disposed between said plurality of source bus lines and said plurality of pixel electrodes, wherein said insulating film includes an inorganic insulating film and an organic insulating film that are stacked together.

6. The active matrix substrate according to claim 1, wherein one of said plurality of gate bus lines is disposed in each row of said plurality of pixel electrodes arranged in the first direction, and wherein one of said plurality of source bus lines is disposed in each column of said plurality of pixel electrodes arranged in the second direction.

7. The active matrix substrate according to claim 6, wherein said reference point is located in a center of a pixel.

8. The active matrix substrate according to claim 1, wherein two of said plurality of gate bus lines are disposed in each row of said plurality of pixel electrodes arranged in the first direction, and wherein one of said plurality of source bus lines is disposed in every other column of said plurality of pixel electrodes arranged in the second direction.

9. The active matrix substrate according to claim 8, wherein said reference point is located between adjacent two pixels.

10. The active matrix substrate according to claim 1, wherein each of the plurality of gate bus lines have a group of thin film transistors attached thereto, and every adjacent two of said group of said thin film transistors are disposed on respective opposite sides of the gate bus line.

11. The active matrix substrate according to claim 1, wherein said plurality of auxiliary capacitance bus lines are disposed so as to pass through centers of a row of pixels that are arranged in the first direction.

12. The active matrix substrate according to claim 1, wherein said plurality of auxiliary capacitance bus lines are disposed on a periphery of a row of pixels that are arranged in the first direction.

13. The active matrix substrate according to claim 1, wherein said second electrode section has a loop-like structure in which ends of said two linear sections are connected to each other.

14. The active matrix substrate according to claim 1, wherein said plurality of thin film transistors have a semiconductor layer that includes an oxide semiconductor.

15. A display device, comprising: the active matrix substrate according to claim 1.

16. The active matrix substrate according to claim 14, wherein said oxide semiconductor includes indium, gallium, zinc, and oxygen.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 1.

(2) FIG. 2 is a schematic cross-section that illustrates a cross-section of the portion that corresponds to the line A-A in FIG. 1.

(3) FIG. 3 is a schematic cross-section that illustrates a cross-section of the portion that corresponds to the line B-B in FIG. 1.

(4) FIG. 4 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 2-1.

(5) FIG. 5 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 2-2.

(6) FIG. 6 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 2-3.

(7) FIG. 7 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 2-4.

(8) FIG. 8 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 3-1.

(9) FIG. 9 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 3-2.

(10) FIG. 10 is schematic plan view that shows a pixel in an active matrix substrate according to Embodiment 4.

(11) FIG. 11 illustrates a method for driving the active matrix substrate according to Embodiment 4.

(12) FIG. 12 is a graph that shows aperture ratios of liquid crystal display devices according to Embodiment 2-1.

(13) FIG. 13 is a graph that shows the capacitance of the source bus lines in liquid crystal display devices according to Embodiment 2-1.

(14) FIG. 14 is a graph that shows the aperture ratios of liquid crystal display devices according to Embodiment 4.

(15) FIG. 15 is a graph that shows the capacitance of the source bus lines in liquid crystal display devices according to Embodiment 4.

(16) FIG. 16 is a schematic plan view that shows a pixel in a conventional active matrix substrate (a -type auxiliary capacitance electrode configuration).

(17) FIG. 17 is a schematic plan view of a pixel in a conventional active matrix substrate (an auxiliary capacitance electrode under source bus line configuration).

(18) FIG. 18 is a schematic plan view of a pixel in a conventional active matrix substrate (a combination of a -type auxiliary capacitance electrode configuration and an auxiliary capacitance electrode under source bus line configuration).

DETAILED DESCRIPTION OF EMBODIMENTS

(19) In this specification, it is preferable that the concept of extending to a direction (such as the above-mentioned first and second directions) means to extend substantially parallel to the direction, for example. It is also preferable that the concept of intersecting a direction means to be substantially orthogonal to the direction, for example. Additionally, a substantially central portion of the respective pixels may be an actual central portion of the respective pixels, or may be an actual central portion of the display region (a region in which a black matrix of an opposing substrate that opposes the active matrix substrate and an auxiliary capacitance electrode are not disposed, for example) of the various pixels, for example. Furthermore, each of the above-mentioned plurality of auxiliary capacitance electrodes may be configured such that auxiliary capacitance is formed between the above-mentioned plurality of pixel electrodes. The capacitance of the source bus lines is the capacitance between the source bus lines and the wiring and the like (gate bus lines, auxiliary capacitance bus lines, and auxiliary capacitance electrodes, for example) that overlap the source bus lines by means of an insulating film, for example. The concept of being symmetrically disposed may mean that the locations of electrode sections (the above-mentioned first and second electrode sections, for example) are symmetrically disposed (such as first electrode sections 11a, 11b, and second electrode sections 12a, 12b shown in FIG. 1, for example), or may mean that the locations of the electrode sections are symmetrically disposed graphically when the shape of the electrode sections is taken into consideration (such as first electrode sections 111a, 111b and second electrode sections 112a, 112b shown in FIG. 4, for example), for example.

(20) Preferred embodiments of an active matrix substrate according to the present invention will be explained next.

(21) According to one aspect of an active matrix substrate according to the present invention, the above-mentioned plurality of auxiliary capacitance electrodes may be disposed in the same layer as the above-mentioned plurality of gate bus lines.

(22) Thus, the plurality of auxiliary capacitance electrodes and the plurality of gate bus lines can be formed in the same step, which allows for the manufacturing process to become shorter. It is also preferable that the plurality of auxiliary capacitance electrodes and the plurality of gate bus lines be formed of the same conductive material. Additionally, the above-mentioned phrase of the above-mentioned plurality of auxiliary capacitance electrodes are disposed in the same layer as the above-mentioned plurality of gate bus lines may mean that the plurality of auxiliary capacitance electrodes and the plurality of gate bus lines come into contact with the same member (a glass substrate, for example) on the glass substrate side and/or the side opposite of the glass substrate side, for example. The plurality of auxiliary capacitance electrodes and the plurality of gate bus lines may also be formed on the same glass substrate, and may be disposed in locations separate from one another, for example.

(23) According to one aspect of the active matrix substrate of the present invention, the active matrix substrate may further include an insulating film in a layer between the plurality of source bus lines and the plurality of pixel electrodes, and the insulating film may be an inorganic insulating film.

(24) According to one aspect of the active matrix substrate of the present invention, the active matrix substrate may further include an insulating film in a layer between the plurality of source bus lines and the plurality of pixel electrodes, and the insulating film may be an organic insulating film.

(25) According to one aspect of the active matrix substrate of the present invention, the active matrix substrate may further include an insulating film in a layer between the plurality of source bus lines and the plurality of pixel electrodes, and the insulating film may be an film in which an inorganic insulating film and an organic insulating film have been stacked.

(26) Thus, a configuration (hereafter referred to as a Pixel on Pas configuration) in which the pixel electrodes of the respective pixels are disposed upon the insulating film can exhibit the effects of an aspect of the present invention. A Pixel on Pas configuration is a configuration in which an insulating film 17 is disposed in a layer between a source bus line 3a and pixel electrodes 9 in an active matrix substrate 1 like the one shown in FIG. 2, for example. As mentioned above, the auxiliary capacitance electrodes partially block electric fields generated between the pixel electrodes and the source bus lines. In order for this effect to be exhibited, it is even more preferable that the insulating film be an inorganic insulating film. This is due to the fact that, compared to inorganic insulating films, organic insulating films have a lower relative permittivity and are more easily made thicker. As a result, in instances in which an organic insulating film is used, the capacitance between the source bus lines and the pixel electrodes is smaller and the electric fields that the auxiliary capacitance electrodes attempt to block are smaller compared to instances in which an inorganic insulating film is used. There is no particular limit to the thickness of the inorganic insulating film, but it is preferable that the thickness be 0.2 to 0.6 m. There is no particular limit to the thickness of the organic insulating film, but it is preferable that the thickness be 1 to 4 m.

(27) According to one aspect of the active matrix substrate of the present invention, one of the plurality of gate bus lines may be disposed in each row of the plurality of pixel electrodes arranged in the first direction, and one of the plurality of source bus lines may be disposed in each column of the plurality of pixel electrodes arranged in the second direction.

(28) Thus, the effect of one aspect of the present invention can be exhibited in a single scan configuration. In this specification, pixel rows can be understood to be, from among a plurality of one-dimensional pixel electrode arrangements disposed in a matrix, the pixel electrodes in one direction, and a pixel column can be understood as being another of the one-dimensional arrangements that is arranged in a direction that intersects the pixel rows (preferably being substantially orthogonal to the pixel rows). A single scan configuration is a configuration in which, in an active matrix substrate 1 like the one shown in FIG. 1, one gate bus line (a gate bus line 2a or a gate bus line 2b, for example) is disposed in each pixel row that is arranged in a horizontal direction (a direction to which the gate bus line 2a extends), and one source bus line (a source bus line 3a or a source bus line 3b, for example) is arranged in each pixel column that is arranged in a vertical direction (a direction to which the source bus line 3a extends), for example. According to a single scan configuration, there will be one gate bus line for each pixel row.

(29) According to one aspect of the active matrix substrate of the present invention, the above-mentioned reference point may be disposed in the center of the respective pixels.

(30) In an active matrix substrate 1 that has a single scan configuration, such as the one shown in FIG. 1, when the point P1 that is in the center of the display region of a pixel is used as the reference point, the adjacent first electrode sections 11a, 11b are disposed symmetrically with respect to each other about the point P1, for example. In addition, the adjacent second electrode sections 12a, 12b are disposed symmetrically with respect to each other about the point P1. The first electrode sections 11a, 11b and the second electrode sections 12a, 12b are disposed identically to those in the other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR1, AR2 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness such as that mentioned above can be prevented from occurring. Therefore, a decrease in display quality can be adequately prevented. It is preferable that the aperture ratios are substantially identical mean that the difference between the aperture ratios of the various regions be 10% or less, with 1% or less being more preferable, for example. Since the difference between aperture ratios of the various regions will vary according to factors such as pixel pitch, liquid crystal display mode, and the like, for example, it is preferable that such factors also be taken into consideration.

(31) According to one aspect of an active matrix substrate of the present invention, two of the plurality of gate bus lines may be disposed in each of the plurality of pixel electrode rows arranged in the first direction, and one of the plurality of source bus lines may be disposed in every other of the plurality of pixel electrode columns arranged in the second direction.

(32) Thus, the effect of one aspect of the present invention can be exhibited in a dual gate configuration. A dual gate configuration is a configuration in which, in an active matrix substrate 101 such as the one shown in FIG. 4, two gate bus lines (gate bus lines 102a, 102b, or gate bus lines 102c, 102d, for example) are disposed in each pixel row arranged in the horizontal direction (the direction to which the gate bus line 102a extends), and one source bus line (source bus lines 103a, 103b, 103c, for example) is disposed in every other pixel column arranged in the vertical direction (the direction to which the source bus line 103a extends), for example. According to a dual gate configuration, there will be two gate bus lines for each pixel row. In addition, according to a dual gate configuration, the number of gate bus lines will double and the number of source bus lines will be cut in half. As a result, the number of gate drivers will double and the number of source drivers will be cut in half. Normally, source drivers are more expensive than gate drivers, which means that the total cost of drivers can be reduced in such a case. Therefore, by applying the present invention to an active matrix substrate that has a dual gate configuration, the effects of one aspect of the present invention will be exhibited, and the total cost of drivers can be decreased.

(33) According to one aspect of the active matrix substrate of the present invention, the above-mentioned reference point may be disposed between adjacent pixels.

(34) In an active matrix substrate 101 that has a dual gate configuration such as the one shown in FIG. 4, when a point P2, which is located between adjacent pixels on a straight line that passes through the center of the display region of the various pixels arranged in the horizontal direction, is used as the reference point, adjacent first electrode sections 111a, 111b are disposed symmetrically with respect to each other about the point P2, for example. In addition, adjacent second electrode sections 112a, 112b are also disposed symmetrically with respect to each other about the point P2. The first electrode sections 111a, 111b and the second electrode sections 112a, 112b are disposed identically to those in the other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR3, AR4 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of the upper region ARu and the lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, a decrease in display quality can be adequately prevented.

(35) According to one aspect of the active matrix substrate of the present invention, the plurality of thin film transistor elements, which are adjacent to each other and arranged in the first direction, may be respectively disposed on different sides of the plurality of gate bus lines.

(36) Thus, the effect of an aspect of the present invention can be exhibited in a structure (hereafter referred to as an upper and lower individually driven structure) in which the upper and lower halves of pixels arranged in the first direction are each driven individually. An upper and lower individually driven structure is a structure in which, in an active matrix substrate such as the one shown in FIG. 11, thin film transistor elements, which are electrically connected to the gate bus line 2a and which are arranged in the direction in which the gate bus line 2a extends, are alternately disposed on both sides (in FIG. 11, the upper and lower sides) of the gate bus line 2a, thus resulting in a structure in which pixels corresponding to thin film transistor elements (thin film transistor elements 4a, 4a, 4a, for example) arranged on one side (lower side) of the gate bus line 2a and pixels corresponding to thin film transistor elements (thin film transistor elements 4b, 4b, 4b, for example) arranged on the other side (the upper side) of the gate bus line 2a are driven, for example. Thus, all of the pixels disposed on both sides of the gate bus line 2a are driven in a manner in which the upper and lower halves of each pixel are driven individually. The upper and lower individually driven structure will be explained in more detail below. A concept in which the plurality of thin film transistor elements, which are adjacent to each other and arranged in the first direction, are respectively disposed on different sides of the plurality of gate bus lines was mentioned above. This concept means that, in an active matrix substrate such as the one shown in FIG. 11, the thin film transistor elements 4a, 4b, which are adjacent to each other and arranged in the horizontal direction, are disposed on both sides (the upper and lower sides) of the gate bus line 2a, for example.

(37) According to one aspect of an active matrix substrate of the present invention, the above-mentioned plurality of auxiliary capacitance bus lines may be disposed so as to pass through the center of the pixels.

(38) According to one aspect of an active matrix substrate of the present invention, the above-mentioned plurality of auxiliary capacitance bus lines may be disposed on the periphery of the pixels.

(39) An active matrix substrate 101 such as the one shown in FIG. 4, for example, is an example of a substrate in which the above-mentioned plurality of auxiliary capacitance bus lines may be disposed so as to pass through the center of the pixels. When auxiliary capacitance bus lines 110 are disposed so as to pass through the center of the pixels, the distance between the gate bus line 102b (102c) and the auxiliary capacitance bus line 110 increases. This leads to fewer leak defects, and as a result, the manufacturing yield increases. In order to decrease the number of leak defects, it is preferable that the distance between the gate bus line and the auxiliary capacitance line be 7 m or above, and even more preferable that the distance be 10 m or above.

(40) An active matrix substrate 501 such as that shown in FIG. 8, for example, is an example of a substrate in which the above-mentioned plurality of auxiliary capacitance bus lines are disposed on the periphery of the pixels, and the auxiliary capacitance bus line 110 may be disposed near the gate bus line 102b. When the auxiliary capacitance bus line 110 is disposed on the periphery of the pixel, even if a decrease in display quality, such as that due to light leakage as a result of orientation disorder, occurs near the gate bus line 102b, it is easy to block the locations where light leakage is occurring due to the auxiliary capacitance bus line 110 being disposed near the gate bus lines 102. For such blocking of light leakage to occur, it is preferable that the distance between the gate bus line and the auxiliary capacitance bus line be 7 m or less, and even more preferable that the distance be 5 m or less.

(41) The plurality of auxiliary capacitance bus lines may have an arrangement different from that mentioned above (passing through the center of the pixels or to the periphery of the pixels) as long the effect according to one aspect of the present invention is exhibited.

(42) According to one aspect of the active matrix substrate of the present invention, the second electrode section may have a loop-like structure in which the ends of the two linear sections mentioned above are connected to each other.

(43) An electrode section, such as the second electrode section 12b shown in FIG. 1, for example, in which the ends of two linear sections are connected to each other to form a loop, may be used as an electrode section having a loop-like structure. When the electrode section has a loop-like structure like that of the second electrode section 12b, even if a portion (the portion corresponding to the line C-C in FIG. 1, for example) becomes disconnected, there will not be any portions that become so-called floating islands (electrically insulated from everything else). Therefore, the effect of the auxiliary capacitance electrodes partially blocking electric fields generated between the pixel electrodes and the source bus lines can be maintained.

(44) According to one aspect of the active matrix substrate of the present invention, the plurality of thin film transistor elements may have a semiconductor layer that includes an oxide semiconductor.

(45) An oxide semiconductor has higher mobility and less characteristic variation than amorphous silicon. As a result, thin film transistor elements that include an oxide semiconductor have a high driving frequency and can be driven at a faster speed than thin film transistor elements that include amorphous silicon, and a smaller number of transistor elements need to be used for one pixel. Therefore, such transistor elements are suitable for next generation display devices which have higher resolution. Furthermore, an oxide semiconductor film is formed by a process that is simpler than that for a polycrystalline silicon film, and thus, the oxide semiconductor film can be applied to devices requiring a large area. Therefore, when thin film transistor elements included in one aspect of an active matrix substrate of the present invention have a semiconductor layer that includes an oxide semiconductor, the effect of one aspect of the present invention can be exhibited, and an even higher driving speed can be achieved.

(46) A compound (InGaZnO) formed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O), a compound (InSnZnO) formed of indium (In), tin (Sn), zinc (Zn), and oxygen (O), a compound (InAlZnO) formed of indium (In), aluminum (Al), zinc (Zn), and oxygen (O), or the like, for example, may be used to form the oxide semiconductor.

(47) The respective configurations mentioned above may be appropriately combined within a scope that does not depart from the gist of the present invention.

(48) A display device of the present invention that has the preferred configurations may be a display device that includes an active matrix substrate that has the above-mentioned preferred configurations.

(49) The respective configurations mentioned above may be appropriately combined within a scope that does not depart from the gist of the present invention.

(50) Embodiments are shown below and the present invention is described in further detail with reference to the drawings, but the present invention is not limited to these embodiments. Furthermore, the respective configurations of the embodiments described below may be appropriately combined or changed within a scope that does not depart from the gist of the present invention.

(51) The present invention can be applied generally to active matrix substrates that include auxiliary capacitance electrodes and display devices that include such active matrix substrates. Such active matrix substrates and liquid crystal display devices that include such active matrix substrates will be described in the embodiments below.

Embodiment 1

(52) Embodiment 1 has a single scan configuration in which auxiliary capacitance bus lines are disposed on the periphery of pixels and second electrode sections of a portion of auxiliary capacitance electrodes have a loop-like structure. The ratio (the ratio of the length in the direction to which source bus lines extend) of first electrode sections to second electrode sections in the auxiliary capacitance electrodes is 1:1. Overlapping descriptions of a single scan configuration, a configuration in which auxiliary capacitance bus lines are disposed on the periphery of pixels, and a loop-like structure will not repeated here since such configurations and structures were described above.

(53) FIG. 1 is schematic plan view that illustrates the pixels of an active matrix substrate according to Embodiment 1. While FIG. 1 mainly illustrates the configuration of an active matrix substrate, a portion of the configuration of an opposing substrate (a black matrix 14, for example) that opposes the active matrix substrate is also shown. As shown in FIG. 1, an active matrix substrate 1 includes a gate bus line 2a, a source bus line 3a that extends in a direction that intersects the gate bus line 2a, a thin film transistor element 4 that is electrically connected to the gate bus line 2a and the source bus line 3a, and a pixel electrode 9 that is electrically connected to a drain electrode 7 of the thin film transistor element 4 via a contact hole 8. In a pixel such as that shown in FIG. 1, a voltage provided by the source bus line 3a is applied to the pixel electrode 9 via a source electrode 5, a semiconductor layer 6, the drain electrode 7, and the contact hole 8 when the pixel is selected by the gate bus line 2a. There are no particular restrictions regarding the structure of the semiconductor layer 6, but it is preferable that the semiconductor layer 6 include an oxide semiconductor.

(54) The active matrix substrate 1 includes an auxiliary capacitance bus line 10 that extends in the same direction as the gate bus line 2a, and an auxiliary capacitance electrode 13a (13b) that branches from the auxiliary capacitance bus line 10 and that extends in the same direction as the source bus line 3a (3b). The auxiliary capacitance electrode 13a (13b) is formed of a first electrode section 11a (11b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 12a (12b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 1, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line. The first and second electrode sections prevent shadowing, which was mentioned above. The first electrode section 11a and the second electrode section 12a also partially block an electric field generated between the pixel electrode 9 and the source bus line 3a and decrease the capacitance between the source bus line 3a and the pixel electrode 9, for example.

(55) In the active matrix substrate 1, when a point P1 that is in the center of a display region of a pixel is set as a reference point, adjacent first electrode sections 11a, 11b are disposed symmetrically with respect to the point P1. Adjacent second electrode sections 12a, 12b are also disposed symmetrically with respect to point P1. The first electrode sections 11a, 11b and the second electrode sections 12a, 12b are disposed the same as those in the other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR1, AR2 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 1, decreases in display quality can be adequately prevented.

(56) The second electrode section 12a does not have a loop-like structure itself. However, since the second electrode section 12a is electrically connected to the auxiliary capacitance bus line 10, a loop-like structure is formed by combining the second electrode section 12a with the auxiliary capacitance bus line 10. Thus, even if a portion of the second electrode section 12a becomes disconnected, the effect of partially blocking an electric field generated between the pixel electrode and the source bus line can be maintained.

(57) The horizontal direction (the direction to which the gate bus line 2a extends) and the vertical direction (the direction to which the source bus line 3a extends) in FIG. 1 respectively correspond to the first and second directions mentioned above in one aspect of the present invention. This also applies to the embodiments that will be described hereafter.

(58) Next, the structure of a liquid crystal display device that corresponds to the section in which the first and second electrode sections are disposed will be explained using FIGS. 2 and 3. As shown in FIGS. 2 and 3, the basic structure of a liquid crystal display device includes the active matrix substrate 1, an opposing substrate 20 that opposes the active matrix substrate 1, and a liquid crystal layer 21 sandwiched between the two substrates.

(59) The structure of a liquid crystal display device that corresponds to the section in which the first electrode section is disposed will be explained first. FIG. 2 is a schematic cross-section that illustrates a cross-section of the section that corresponds to the line A-A in FIG. 1. As shown in FIG. 2, the active matrix substrate 1 has: a glass substrate 15a; the first electrode section 11a provided on a main surface of the glass substrate 15a; a protective film 16a provided so as to cover the first electrode section 11a; the source bus line 3a, which is provided above a portion of the protective film 16a and provided in a location so as to overlap at least a portion of the first electrode section 11a in a plan view of the main surface of the glass substrate 15a; a protective film 16b provided so as to cover the source bus line 3a; an insulating film 17 that is provided on the protective film 16b and that is provided on the side opposite of the glass substrate 15a side of the protective film 16b; and a pixel electrode 9 provided on a portion of the insulating film 17, and provided in a location so as to overlap at least a portion of the first electrode section 11a in a plan view of the main surface of the glass substrate 15a. In addition, an alignment film 18a is provided on the liquid crystal layer 21 side of the active matrix substrate 1.

(60) The first electrode section 11a is disposed in the same layer as the gate bus line 2a (which is shown in FIG. 1 but not FIG. 2). The insulating film 17 may be an inorganic insulating film, an organic insulating film, or a film in which an inorganic insulating film and an organic insulating film have been stacked. It is preferable that the insulating film 17 be an inorganic insulating film so that the effect of preventing shadowing may be exhibited. A silicon nitride (SiNx) or the like, for example, can be used as the inorganic insulating film, and a photosensitive organic film or the like, for example, can be used as the organic insulating film.

(61) As shown in FIG. 2, the opposing substrate 20 has: a glass substrate 15b; a black matrix 14 that is provided on the main surface of the glass substrate 15b and that overlaps the first electrode section 11a; and a color filter 19 that covers a portion of the black matrix 14. In addition, an alignment film 18b is provided on the liquid crystal layer 21 side of the opposing substrate 20.

(62) The structure of a liquid crystal display device that corresponds to the section in which the second electrode section is disposed will be explained next. FIG. 3 is a schematic cross-section that illustrates a cross-section of the section that corresponds to the line B-B in FIG. 1. As shown in FIG. 3, the active matrix substrate 1 has: the glass substrate 15a; the second electrode section 12a (corresponding to the cross-section of two linear sections) provided on the main surface of the glass substrate 15a; the protective film 16a provided so as to cover the second electrode section 12a; the source bus line 3a, which is provided on a portion of the protective film 16a and provided in a location so as to overlap at least a portion of the region between the two sections of the second electrode section 12a in a plan view of the main surface of the glass substrate 15a; the protective film 16b provided so as to cover the source bus line 3a; the insulating film 17 that is provided on the protective film 16b and that is provided on the side opposite of the glass substrate 15a side of the protective film 16b; and the pixel electrode 9 that is provided on a portion of the insulating film 17, and provided in a location so as to overlap at least a portion of the second electrode section 12a in a plan view of the main surface of the glass substrate 15a. In addition, an alignment film 18a is provided on the liquid crystal layer 21 side of the active matrix substrate 1.

(63) The second electrode section 12a is disposed in the same layer as the gate bus line 2a (which is shown in FIG. 1 but not FIG. 3).

(64) As shown in FIG. 3, the opposing substrate 20 has: the glass substrate 15b; the black matrix 14 that is provided on the main surface of the glass substrate 15b and that overlaps the second electrode sections 12a and the space therebetween; and a color filter 19 that covers a portion of the black matrix 14. In addition, the alignment film 18b is provided on the liquid crystal layer 21 side of the opposing substrate 20.

(65) Looking at the width of the black matrix 14, the section of the black matrix 14 that opposes the second electrode section 12a is wider than the section that opposes the first electrode section 11a. As shown in FIG. 1, Embodiment 1 has a configuration in which the second electrode sections, which oppose the black matrix where the black matrix is relatively wider, are not continuously aligned in the horizontal direction. Therefore, an adequate distance between second electrode sections can be maintained in the horizontal direction, the margins between the black matrix can be improved with respect to the resolution limit, and it becomes easier to form a black matrix with high precision. As a result, Embodiment 1 can be suitably applied to a high resolution liquid crystal display device in which the size of the pixels is small (the pixel pitch in the horizontal direction is small).

(66) In Embodiment 1, the auxiliary capacitance bus line is disposed on the periphery of the pixel. However, the auxiliary capacitance bus line is not limited to this location, and may be disposed so as to pass through the center of the pixel, for example.

(67) In Embodiment 1, the second electrode section has a loop-like structure. There are no particular restrictions as to whether or not the second electrode section has a loop-like structure, however. For example, all of the second electrode sections may have a loop-like structure, none of the second electrode sections may have a loop-like structure, or a portion of the second electrode sections may have a loop-like structure. If a second electrode section has a loop-like structure, as mentioned above, even if a portion of the electrode section becomes disconnected, the effect of partially blocking an electric field that is generated between the pixel electrode and the source bus line can still be maintained. If the second electrode section does not have a loop-like structure, the capacitance between the source bus line and the auxiliary capacitance electrode (the second electrode section) will decrease even further.

(68) In Embodiment 1, the ratio (the ratio of the length in the direction to which the source bus lines extend) of the first electrode sections to the second electrode sections is 1:1. There is no particular limit to this ratio, however, and the ratio may be set to any desired value in accordance with the pixel size, shape of the pixel electrodes, any desired specifications (power consumption, display quality, and the like), and the like so that the effect of an aspect of the present invention may be exhibited.

(69) As shown in FIG. 1, in Embodiment 1, the first and second electrode sections were disposed in the same location with respect to the pixel columns in the vertical direction. There are no particular restrictions as to how the electrode sections are disposed, however, and the location of the electrode sections may be switched with each other, for example.

(70) There are no particular restrictions regarding the liquid crystal display mode of the liquid crystal display device according to Embodiment 1. Looking at the present invention from the perspective of blocking light leakage from a backlight, a normally white mode (a mode that displays in white when no voltage is being applied) such as TN (twisted nematic) mode has a particularly significant effect, for example. However, looking at the present invention from the perspective of improving contrast by blocking light leakage resulting from orientation disorder in the periphery of the pixels, normally black modes (modes that display in black when no voltage is being applied) such as MVA mode, CPA mode, FFS mode, IPS (in-plane switching) mode, and TBA (transverse bend alignment) mode are effective, for example. In a normal MVA mode, according to one aspect of the present invention, variations in the aperture ratio of four domain regions can be prevented, meaning that variations in brightness due to the viewing angle can be adequately prevented, for example. In addition, there are no particular restrictions regarding the method of alignment, and the present embodiment can be suitably used in PSA (polymer sustained alignment) technology, photoalignment technology, or the like. There are also no particular restrictions regarding the driving method (multi-pixel technology, for example). There are also no particular limitations regarding the shape of the pixels, and the pixels may be vertically-long pixels, horizontally-long pixels, or V-shaped pixels.

Embodiment 2

(71) Embodiment 2 has a dual gate configuration in which auxiliary capacitance bus lines are disposed so as to pass through the center of pixels. In Embodiment 2, there are no particular restrictions as to whether or not the second electrode section has a loop-like structure. For example, all of the second electrode sections may have a loop-like structure, none of the loop second electrode sections may have a loop-like structure, or a portion of the second electrode sections may have a loop-like structure. There is also no particular limit to the ratio (the ratio of the length in the direction to which the source bus lines extend) of the first electrode section to the second electrode section, and the ratio may be set to any desired value in accordance with the pixel size, shape of the pixel electrodes, any desired specifications (power consumption, display quality, and the like) and the like so that the effect of an aspect of the present invention may be exhibited. More detailed examples will be given in Embodiments 2-1 to 2-4, which will be explained below. Descriptions of a dual gate configuration and a configuration in which the auxiliary capacitance bus lines are disposed so as to pass through the center of the pixels will not be repeated since such descriptions were given above.

Embodiment 2-1

(72) In Embodiment 2-1, second electrode sections of auxiliary capacitance electrodes do not have a loop-like structure. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section to a second electrode section of an auxiliary capacitance electrode is 1:1.

(73) FIG. 4 is schematic plan view that shows a pixel of an active matrix substrate according to Embodiment 2-1. While FIG. 4 mainly illustrates the configuration of an active matrix substrate, it also shows a portion of a configuration of an opposing substrate (a black matrix 114, for example) that opposes the active matrix substrate. As shown in FIG. 4, an active matrix substrate 101 includes: a gate bus line 102b; a source bus line 103a that extends in a direction that intersects the gate bus line 102b; a thin film transistor element 104 that is electrically connected to the gate bus line 102b and the source bus line 103a; and a pixel electrode 109 that is electrically connected to a drain electrode 107 of the thin film transistor element 104 via a contact hole 108. In a pixel such as that shown in FIG. 4, a voltage provided by the source bus line 103a is applied to the pixel electrode 109 via a source electrode 105, a semiconductor layer 106, the drain electrode 107, and the contact hole 108 when the pixel is selected by the gate bus line 102b. There are no particular restrictions regarding the structure of the semiconductor layer 106, but it is preferable that the semiconductor layer 106 include an oxide semiconductor.

(74) The active matrix substrate 101 includes an auxiliary capacitance bus line 110 that extends in the same direction as the gate bus line 102b, and an auxiliary capacitance electrode 113a (113b, 113c) that branches from the auxiliary capacitance bus line 110 and that extends in the same direction as the source bus line 103a (103b). The auxiliary capacitance electrode 113a (113b) is formed of a first electrode section 111a (111b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 112a (112b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 2-1, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line. The first and second electrode sections prevent shadowing, which was mentioned above. The first electrode section 111a and the second electrode section 112a also partially block an electric field generated between the pixel electrode 109 and the source bus line 103a and decrease the capacitance between the source bus line 103a and the pixel electrode 109, for example.

(75) In the active matrix substrate 101, when a point P2, which is disposed between adjacent pixels on a line that passes through the center of a display region of respective pixels aligned in the horizontal direction, is set as a reference point, adjacent first electrode sections 111a, 111b are disposed symmetrically with respect to the point P2. Adjacent second electrode sections 112a, 112b are also disposed symmetrically with respect to point P2. The first electrode sections 111a, 111b and the second electrode sections 112a, 112b are disposed the same as those in other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR3, AR4 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 2-1, decreases in display quality can be adequately prevented.

(76) The structure of a liquid crystal display device that corresponds to the section in which the first and second electrode sections are disposed is the same as that of Embodiment 1, so an explanation of identical parts will not be repeated here.

Embodiment 2-2

(77) In Embodiment 2-2, the second electrode sections of the auxiliary capacitance electrodes do not have a loop-like structure. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section to a second electrode section of an auxiliary capacitance electrode is 1:3.

(78) Other than the configuration of the auxiliary capacitance electrode, an active matrix substrate and a liquid crystal display device according to Embodiment 2-2 are identical to those of Embodiment 2-1. An explanation of identical parts will therefore not be repeated here.

(79) FIG. 5 is schematic plan view that illustrates a pixel of an active matrix substrate according to Embodiment 2-2. An active matrix substrate 201 includes an auxiliary capacitance bus line 110 that extends in the same direction as a gate bus line 102b, and an auxiliary capacitance electrode 213a (213b, 213c) that branches from the auxiliary capacitance bus line 110 and that extends in the same direction as the source bus line 103a (103b). The auxiliary capacitance electrode 213a (213b) is formed of a first electrode section 211a (211b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 212a (212b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 2-2, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

(80) In the active matrix substrate 201, when a point P2, which is disposed between adjacent pixels on a line that passes through the center of a display region of respective pixels aligned in the horizontal direction, is set as a reference point, adjacent first electrode sections 211a, 211b are disposed symmetrically with respect to the point P2. Adjacent second electrode sections 212a, 212b are also disposed symmetrically with respect to point P2. The first electrode sections 211a, 211b and the second electrode sections 212a, 212b are disposed the same as those in other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR5, AR6 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 2-2, decreases in display quality can be adequately prevented.

Embodiment 2-3

(81) In Embodiment 2-3, a portion of the second electrode sections of the auxiliary capacitance electrodes have a loop-like structure. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section to a second electrode section of an auxiliary capacitance electrode is 1:3.

(82) Other than the configuration of the auxiliary capacitance electrode, an active matrix substrate and a liquid crystal display device according to Embodiment 2-3 are identical to those of Embodiment 2-1. An explanation of identical parts will therefore not be repeated here.

(83) FIG. 6 is schematic plan view that illustrates a pixel of an active matrix substrate according to Embodiment 2-3. An active matrix substrate 301 includes an auxiliary capacitance bus line 110 that extends in the same direction as a gate bus line 102b, and an auxiliary capacitance electrode 313a (313b, 313c) that branches from the auxiliary capacitance bus line 110 and that extends in the same direction as the source bus line 103a (103b). The auxiliary capacitance electrode 313a (313b) is formed of a first electrode section 311a (311b) that has an auxiliary capacitance electrode under source bus line configuration, and second electrode sections 312a, 312a (312b, 312b) that have a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 2-3, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

(84) In the active matrix substrate 301, when a point P2, which is disposed between adjacent pixels on a line that passes through the center of a display region of respective pixels aligned in the horizontal direction, is set as a reference point, adjacent first electrode sections 311a, 311b are disposed symmetrically with respect to the point P2. Adjacent second electrode sections 312a, 312b are also disposed symmetrically with respect to point P2. Adjacent second electrode sections 312a, 312b are also disposed symmetrically with respect to point P2. The first electrode sections 311a, 311b, the second electrode sections 312a, 312b, and the second electrode sections 312a, 312b are disposed the same as the electrode sections in other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR7, AR8 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 2-3, decreases in display quality can be adequately prevented.

(85) The second electrode sections 312a, 312b have a loop-like structure in which the ends of the two linear sections are connected to each other. Therefore, as mentioned above, even if a portion of the second electrode section becomes disconnected, the effect of partially blocking an electric field that is generated between the pixel electrode and the source bus line can still be maintained.

Embodiment 2-4

(86) In Embodiment 2-4, all second electrode sections of auxiliary capacitance electrodes have a loop-like structure. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section to a second electrode section of an auxiliary capacitance electrode is 1:2.

(87) Other than the configuration of the auxiliary capacitance electrode, an active matrix substrate and a liquid crystal display device according to Embodiment 2-4 are identical to those of Embodiment 2-1. An explanation of identical parts will therefore not be repeated here.

(88) FIG. 7 is schematic plan view that illustrates a pixel of an active matrix substrate according to Embodiment 2-4. An active matrix substrate 401 includes an auxiliary capacitance bus line 110 that extends in the same direction as a gate bus line 102b, and an auxiliary capacitance electrode 413a (413b, 413c) that branches from the auxiliary capacitance bus line 110 and that extends in the same direction as the source bus line 103a (103b). The auxiliary capacitance electrode 413a (413b) is formed of a first electrode section 411a (411b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 412a (412b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 2-4, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

(89) In the active matrix substrate 401, when a point P2, which is disposed between adjacent pixels on a line that passes through the center of a display region of respective pixels aligned in the horizontal direction, is set as a reference point, adjacent first electrode sections 411a, 411b are disposed symmetrically with respect to the point P2. Adjacent second electrode sections 412a, 412b are also disposed symmetrically with respect to point P2. The first electrode sections 411a, 411b and the second electrode sections 412a, 412b are disposed the same as those in other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR9, AR10 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 2-4, decreases in display quality can be adequately prevented.

(90) The second electrode sections 412a, 412b have a loop-like structure in which the ends of two linear sections are connected to each other. Therefore, as mentioned above, even if a portion of the second electrode section becomes disconnected, the effect of partially blocking an electric field that is generated between the pixel electrode and the source bus line can still be maintained.

(91) As shown in FIGS. 4 to 7, in Embodiments 2-1 to 2-4, the first and second electrode sections are disposed in the same location with respect to the pixel columns in the vertical direction. There are no particular restrictions as to how the sections are disposed, however, and the location of the electrode sections may be switched with each other, for example.

(92) There are no particular limitations regarding liquid crystal display mode, method of alignment, method of driving, and pixel shape for the liquid crystal display devices according to Embodiments 2-1 to 2-4. In addition, since such configurations are the same as those of Embodiment 1, an explanation will not be repeated here.

Embodiment 3

(93) Embodiment 3 has a dual gate configuration in which auxiliary capacitance bus lines are disposed on the periphery of pixels. In Embodiment 3, there are no particular restrictions as to whether or not second electrode sections have a loop-like structure. For example, all of the second electrode sections may have a loop-like structure, none of the second electrode sections may have a loop-like structure, or a portion of the second electrode sections may have a loop-like structure. There is also no particular limit to the ratio (the ratio of the length in the direction to which the source bus lines extend) of the first electrode section to the second electrode section, and the ratio may be set to any desired value in accordance with the pixel size, shape of the pixel electrodes, and any desired specifications (power consumption, display quality, and the like) so that the effect of an aspect of the present invention may be exhibited. More detailed examples will be given in Embodiments 3-1 and 3-2, which will be explained below. Descriptions of a dual gate configuration and a configuration in which the auxiliary capacitance bus lines are disposed on the periphery of the pixels will not be repeated since such descriptions were given above.

Embodiment 3-1

(94) In Embodiment 3-1, second electrode sections of auxiliary capacitance electrodes do not have a loop-like structure. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section to a second electrode section of an auxiliary capacitance electrode is 1:1.

(95) Other than the arrangement of the auxiliary capacitance bus line and the configuration of the auxiliary capacitance electrode, an active matrix substrate and a liquid crystal display device according to Embodiment 3-1 are identical to those of Embodiment 2-1. An explanation of identical parts will therefore not be repeated here.

(96) FIG. 8 is schematic plan view that illustrates a pixel of an active matrix substrate according to Embodiment 3-1. An active matrix substrate 501 includes an auxiliary capacitance bus line 110 that extends in the same direction as a gate bus line 102b, and an auxiliary capacitance electrode 513a (513b, 513c) that branches from the auxiliary capacitance bus line 110 and that extends in the same direction as the source bus line 103a (103b). The auxiliary capacitance electrode 513a (513b) is formed of a first electrode section 511a (511b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 512a (512b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 3-1, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

(97) In the active matrix substrate 501, when a point P2, which is disposed between adjacent pixels on a line that passes through the center of a display region of respective pixels aligned in the horizontal direction, is set as a reference point, adjacent first electrode sections 511a, 511b are disposed symmetrically with respect to the point P2. Adjacent second electrode sections 512a, 512b are also disposed symmetrically with respect to point P2. The first electrode sections 511a, 511b and the second electrode sections 512a, 512b are disposed the same as those in other electrodes arranged in the horizontal direction. Consequently, the placement of two regions AR11, AR12 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 3-1, decreases in display quality can be adequately prevented.

(98) The second electrode section 512a does not have a loop-like structure itself. However, since the second electrode section 512a is electrically connected to the auxiliary capacitance bus line 110, a loop-like structure is formed by combining the second electrode section 512a with the auxiliary capacitance bus line 110. Thus, even if a portion of the second electrode section 512a becomes disconnected, the effect of partially blocking an electric field generated between the pixel electrode and the source bus line can be maintained.

Embodiment 3-2

(99) In Embodiment 3-2, a portion of second electrode sections of auxiliary capacitance electrodes have a loop-like structure. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section to a second electrode section of an auxiliary capacitance electrode is 1:1.

(100) Other than the arrangement of an auxiliary capacitance bus line and the configuration of the auxiliary capacitance electrode, an active matrix substrate and a liquid crystal display device according to Embodiment 3-2 are identical to those of Embodiment 2-1. An explanation of identical parts will therefore not be repeated here.

(101) FIG. 9 is schematic plan view that illustrates a pixel of an active matrix substrate according to Embodiment 3-2. An active matrix substrate 601 includes an auxiliary capacitance bus line 110 that extends in the same direction as a gate bus line 102b, and an auxiliary capacitance electrode 613a (613b, 613c) that branches from the auxiliary capacitance bus line 110 and that extends in the same direction as the source bus line 103a (103b). The auxiliary capacitance electrode 613a (613b) is formed of a first electrode section 611a (611b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 612a (612b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 3-2, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

(102) In the active matrix substrate 601, when a point P2, which is disposed between adjacent pixels on a line that passes through the center of the display region of respective pixels aligned in the horizontal direction, is set as a reference point, adjacent first electrode sections 611a, 611b are disposed symmetrically with respect to the point P2. Adjacent second electrode sections 612a, 612b are also disposed symmetrically with respect to point P2. The first electrode sections 611a, 611b and the second electrode sections 612a, 612b are disposed the same as those in other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR13, AR14 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 3-2, decreases in display quality can be adequately prevented.

(103) The second electrode section 612b has a loop-like structure in which the ends of two linear sections are connected to each other. Therefore, as mentioned above, even if a portion of the second electrode section becomes disconnected, the effect of partially blocking an electric field that is generated between the pixel electrode and the source bus line can still be maintained.

(104) As shown in FIGS. 8 and 9, in Embodiments 3-1 and 3-2, the first and second electrode sections are disposed in the same location with respect to the pixel columns in the vertical direction. There are no particular restrictions as to how the electrode sections are disposed in the vertical direction, however, and the location of the electrode sections may be switched with each other, for example.

(105) There are no particular limitations regarding liquid crystal display mode, method of alignment, method of driving, and pixel shape for the liquid crystal display devices according to Embodiments 3-1 and 3-2. In addition, since such configurations are the same as those for Embodiment 1, an explanation will not be repeated here.

Embodiment 4

(106) Embodiment 4 has a single scan configuration with an upper and lower individually driven configuration. An auxiliary capacitance bus line is disposed so as to pass through the center of pixels. In addition, the ratio (the ratio of the length in the direction to which the source bus lines extend) of a first electrode section and a second electrode section of an auxiliary capacitance electrode is 1:1.

(107) Other than the arrangement of a thin film transistor element, the arrangement of the auxiliary capacitance bus line, and the configuration of the auxiliary capacitance electrode, an active matrix substrate and a liquid crystal display device according to Embodiment 4 are identical to those of Embodiment 1. An explanation of identical parts will therefore not be repeated here. Description of a configuration in which the auxiliary capacitance bus lines are disposed so as to pass through the center of the pixels will not be repeated since such a description was given above. Thin film transistor elements 4a, 4b such as those shown in FIG. 10 correspond to the thin film transistor element 4 of Embodiment 1.

(108) FIG. 10 is schematic plan view that illustrates a pixel of an active matrix substrate according to Embodiment 4. An active matrix substrate 701 includes an auxiliary capacitance bus line 10 that extends in the same direction as a gate bus line 2a, and an auxiliary capacitance electrode 713a (713b) that branches from the auxiliary capacitance bus line 10 and that extends in the same direction as a source bus line 3a (3b). The auxiliary capacitance electrode 713a (713b) is formed of a first electrode section 711a (711b) that has an auxiliary capacitance electrode under source bus line configuration, and a second electrode section 712a (712b) that has a -type auxiliary capacitance electrode configuration. Therefore, according to an aspect of Embodiment 4, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

(109) In the active matrix substrate 701, when a point P1, which is disposed in the center of a display region of a pixel, is set as a reference point, adjacent first electrode sections 711a, 711b are disposed symmetrically with respect to the point P1. Adjacent second electrode sections 712a, 712b are also disposed symmetrically with respect to point P1. The first electrode sections 711a, 711b and the second electrode sections 712a, 712b are disposed the same as those in other pixels arranged in the horizontal direction. Consequently, the placement of two regions AR15, AR16 within the display region of the pixel switches between adjacent pixels arranged in the horizontal direction. As a result, the aperture ratios of an upper region ARu and a lower region AR1 in one pixel row are substantially identical, and line-shaped unevenness like that mentioned above can be prevented from occurring. Therefore, according to an aspect of Embodiment 4, decreases in display quality can be adequately prevented.

(110) Next, the upper and lower individually driven configuration will be explained using FIG. 11. FIG. 11 illustrates a method for driving the active matrix substrate according to Embodiment 4. In FIG. 11, the solid lines extending in the horizontal direction represent the gate bus lines, and the dotted lines extending in the vertical direction represent the source bus lines. In addition, in FIG. 11, the symbols + (plus) and (minus) represent the polarity of voltage output from a source driver, for example. The source driver inputs image signals into the thin film transistor elements via the source bus lines.

(111) As mentioned above, an upper and lower individually driven configuration is a configuration in which, in an active matrix substrate such as the one shown in FIG. 11, upper and lower halves of all pixels (pixels corresponding to the thin film transistor elements 4a, 4a, 4a, 4b, 4b, 4b, for example) disposed on both sides of the gate bus line 2a are individually driven, for example. The same occurs for any other gate bus lines (gate bus line 2b, for example) as well. Looking at the polarity of the voltage output by the source driver, as shown in FIG. 11, dot inversion driving, which reverses the polarity of each of the pixels disposed along the same source bus line, is used. By using an upper and lower individually driven configuration, the pixels aligned in the direction to which the gate bus lines extend will all have the same polarity, and the pixels can thus be put into a state similar to the state of pixels in a configuration in which line inversion driving causes the polarity of all pixels in the horizontal direction to become inverted. Therefore, domains can be prevented from occurring on the source bus lines.

(112) Similar to Embodiment 1, Embodiment 4 has a configuration, as shown in FIG. 10, in which second electrode sections that oppose a black matrix that is relatively wide are not continuously arranged in the horizontal direction. Thus, distance in the horizontal direction between second electrode sections can be adequately maintained, the margin of the resolution limit between the black matrix is increased, and it becomes easier to form a black matrix with high precision. As a result, Embodiment 4 can be suitably applied to a high resolution liquid crystal display device in which the size of the pixels is small (the pixel pitch in the horizontal direction is small). In addition, the thin film transistor elements are not continuously arranged in the horizontal direction; thus, Embodiment 4 can be suitably applied to a high definition liquid crystal display device in which the pixel pitch is smaller.

(113) In Embodiment 4, the auxiliary capacitance bus line is disposed so as to pass through the center of pixels. There are no restrictions as to where the auxiliary capacitance bus line is disposed, however, and the auxiliary capacitance bus line may be disposed on the periphery of the pixels, for example.

(114) In Embodiment 4, the second electrode sections do not have a loop-like structure, but there are no particular restrictions as to whether or not the second electrode sections have a loop-like structure. For example, all of the second electrode sections may have a loop-like structure, none of the loop second electrode sections may have a loop-like structure, or a portion of the second electrode sections may have a loop-like structure.

(115) In Embodiment 4, the ratio (ratio of the length in the direction to which the source bus lines extend) of the first electrode sections to the second electrode sections is 1:1. There is no particular limit to this ratio, however, and the ratio may be set to any desired value in accordance with the pixel size, shape of the pixel electrodes, any desired specifications (power consumption, display quality, and the like) and the like so that the effect of an aspect of the present invention may be exhibited.

(116) As shown in FIG. 10, in Embodiment 4, the first and second electrode sections are disposed in the same location with respect the pixel columns in the vertical direction. There are no particular restrictions as to how the electrode sections are disposed in the vertical direction, however, and the location of the electrode sections may be switched with each other, for example.

(117) There are no particular limitations regarding liquid crystal display mode, method of alignment, method of driving, and pixel shape for the liquid crystal display device according to Embodiment 4. In addition, since such configurations are the same as those for Embodiment 1, an explanation will not be repeated here.

Evaluation Results

(118) Various data for liquid crystal display devices according to Embodiments 2-1 and 4 are displayed in Table 1. Aperture ratios and source bus line capacitance (for one line) for liquid crystal display devices according to Embodiments 2-1 and 4 are displayed in Table 2. The aperture ratio and source bus line capacitance have been calculated separately for three cases which each have a different resolution (ppi: pixels per inch). FIGS. 12 to 15 display the contents of Tables 1 and 2 in graph form. FIG. 12 is a graph that shows the aperture ratios of liquid crystal display devices according to Embodiment 2-1. FIG. 13 is a graph that shows the capacitance of source bus lines in liquid crystal display devices according to Embodiment 2-1. FIG. 14 is a graph that shows aperture ratios of liquid crystal display devices according to Embodiment 4. FIG. 15 is a graph that shows the capacitance of source bus lines in liquid crystal display devices according to Embodiment 4. In Table 2 and FIGS. 12 to 15, data for cases in which the configuration (described as both) of the auxiliary capacitance electrodes from Embodiments 2-1 and 4 has been changed to just a -type auxiliary capacitance electrode configuration (described as only -type) and instances in which the configuration has been changed to just an auxiliary capacitance electrode under source bus line configuration (described as only under source bus line) are shown. In addition, the capacitance of the source bus lines was calculated under the assumption that the specification was 74 pF.

(119) TABLE-US-00001 TABLE 1 Pixel Pitch Reso- Screen Number of Pixels (M) lution Size (individual pixels) Short Long Case (ppi) (inches) Horizontal Vertical Side Side Embodi- 1 297 6.3 1800 480 69 207 ment 2 465 6.8 3072 768 45 135 2-1 3 722 6.9 4800 1200 29 87 Embodi- 1 297 6.3 1800 480 69 207 ment 2 465 6.8 3072 768 45 135 4 3 722 6.9 4800 1200 29 87

(120) TABLE-US-00002 TABLE 2 Source Bus Line Aperture Ratio Capacitance Per Line (%) (pF) Only Only Under Under Only Source Only Source Case Both -type Bus Line Both -type Bus Line Embodi- 1 58.8 52.8 61.6 74 27 95 ment 2 38.5 33.6 44.8 74 42 114 2-1 3 13.0 11.7 23.5 74 66 138 Embodi- 1 66.3 57.8 67.4 74 13 82 ment 2 49.2 39.5 52.7 74 21 93 4 3 25.8 16.5 33.0 74 33 105

(121) The evaluation results of the various examples will be explained below.

Embodiment 2-1

(122) As shown in FIGS. 12 and 13, the aperture ratio was larger than in examples that only had a -type auxiliary capacitance electrode configuration, and the source bus line capacitance was smaller than in examples that only had an auxiliary capacitance electrode under source bus line configuration. Therefore, according to an aspect of Embodiment 2-1, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line.

Embodiment 4

(123) As shown in FIGS. 14 and 15, the aperture ratio was larger than in examples that only had a -type auxiliary capacitance electrode configuration, and the source bus line capacitance was smaller than in examples that only had an auxiliary capacitance electrode under source bus line configuration. Therefore, according to an aspect of Embodiment 4, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus line. In addition, the aperture ratio of Embodiment 4 was larger than that of Embodiment 2-1, and, as was mentioned above, it can be seen that Embodiment 4 is suitable for high definition liquid crystal display devices in which the pixel pitch is small.

(124) It can be surmised that other embodiments would have results similar to those shown above. For example, in Embodiments 2-1 to 2-4, 3-1, and 3-2, the auxiliary capacitance bus lines have the same amount of surface area in the display region of the pixels regardless of whether the auxiliary capacitance bus lines are disposed so as to pass through the center of the pixels or disposed on the periphery of the pixels. Therefore, it can be surmised that the effect on the aperture ratio would be the same for each embodiment. In addition, regardless of whether or not the second electrode sections have a loop-like structure, the width of the black matrix that opposes the source bus lines and the second electrode sections remains the same. Therefore, it can be surmised that the effect on the aperture ratio would be the same for each embodiment. Therefore, according to an aspect of Embodiments 2-1 to 2-4, 3-1, and 3-2, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus lines.

(125) Also, in Embodiments 1 and 4, since changing the arrangement of the thin film transistor elements only causes the alignment of the pixels to be different, it can be surmised that the effect on the aperture ratio would be the same for each embodiment, for example. Therefore, according to an aspect of Embodiments 1 and 4, the aperture ratio can be increased while still adequately suppressing the capacitance of the source bus lines.

DESCRIPTION OF REFERENCE CHARACTERS

(126) 1, 101, 201, 301, 401, 501, 601, 701, 1001, 1101, 1201 active matrix substrate

(127) 2a, 2b, 102a, 102b, 102c, 102d, 1002 gate bus line

(128) 3a, 3b, 103a, 103b, 103c, 1003 source bus line

(129) 4, 4a, 4a, 4a, 4b, 4b, 4b, 104, 1004 thin film transistor element

(130) 5, 105, 1005 source electrode

(131) 6, 106 semiconductor layer

(132) 7, 107, 1007 drain electrode

(133) 8, 108 contact hole

(134) 9, 109, 1009 pixel electrode

(135) 10, 110, 1010, 1110, 1210 auxiliary capacitance bus line

(136) 11a, 11b, 111a, 111b, 211a, 211b, 311a, 311b, 411a, 411b, 511a, 511b, 611a, 611b, 711a, 711b, 1211 first electrode section

(137) 12a, 12b, 112a, 112b, 212a, 212b, 312a, 312a, 312b, 312b, 412a, 412b, 512a, 512b, 612 a, 612b, 712a, 712b, 1212 second electrode section

(138) 13a, 13b, 113a, 113b, 11b, 213a, 213b, 313a, 313b, 413a, 413b, 513a, 513b, 613a, 613b, 713a, 713b, 1013, 1113, 1213 auxiliary capacitance electrode

(139) 14, 14a, 14b, 114, 1214 black matrix (outside of the section surrounded by the solid line)

(140) 15a, 15b glass substrate

(141) 16a, 16b protective film

(142) 17 insulating film

(143) 18a, 18b alignment film

(144) 19 color filter

(145) 20 opposing substrate

(146) 21 liquid crystal layer