Epitaxial silicon wafer having reduced stacking faults

Abstract

An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m.Math.cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.

Claims

1. An epitaxial silicon wafer comprising: a silicon wafer added with red phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m.Math.cm; an epitaxial film directly formed on a first side of the silicon wafer, wherein the uniformity of the resistivity in the plane of the epitaxial film is less than 9.6%; and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein a total number of Light Point Defects, generated due to stacking faults, of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.

2. The epitaxial silicon wafer according to claim 1, wherein the uniformity of the resistivity in the plane of the epitaxial film is less than or equal to 1.9%.

3. The epitaxial silicon wafer according to claim 1, wherein the uniformity of the resistivity in the plane of the epitaxial film is defined as P, wherein:
P=(maximumminimum)/(2average)100%.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a graph showing results of an experiment for deriving a manufacturing condition of an epitaxial silicon wafer according to the invention, which shows a relationship between a solidification rate of a single crystal ingot and an SF number.

(2) FIG. 2 is another graph showing results of Experiment 1 for deriving the manufacturing condition, which shows a relationship between the solidification rate, the SF number and a residence time at each of temperatures.

(3) FIG. 3 shows results of Experiment 2 showing a generation state of LPD on a silicon wafer before a pit-evaluation heat treatment.

(4) FIG. 4 shows the results of Experiment 2 showing a generation state of LPD after the pit-evaluation heat treatment on a silicon wafer corresponding to a solidification rate at which SF are generated.

(5) FIG. 5 shows the results of Experiment 2 showing a generation state of LPD after the pit-evaluation heat treatment on a silicon wafer corresponding to a solidification rate at which SF are not generated.

(6) FIG. 6 shows the results of Experiment 2 showing AFM observation results of LPD on a silicon wafer increased after the pit-evaluation heat treatment.

(7) FIG. 7 shows results of Experiment 3 for deriving the manufacturing condition, which shows an LPD generation state after growing an epitaxial film and experimental results shown in FIG. 4 in an overlapped manner.

(8) FIG. 8 shows results of Experiment 3, which shows a part of FIG. 7 in an enlarged manner.

(9) FIG. 9 is a graph showing results of Experiment 4 for deriving the manufacturing condition, which shows a correlation between a substrate resistivity and the number of SF generated.

(10) FIG. 10 is a graph showing results of Experiment 5 for deriving the manufacturing condition, which shows a correlation between an argon annealing time and the number of SF generated.

(11) FIG. 11 is a graph showing results of Experiment 6 for deriving the manufacturing condition, which shows a correlation between a distance from a center of an epitaxial silicon wafer and resistivity of an epitaxial film.

(12) FIG. 12 is a graph showing results of Experiment 7 for deriving the manufacturing condition, which shows a relationship between the solidification rate and a center temperature of the crystal.

(13) FIG. 13 is a graph showing the results of Experiment 7, which shows a relationship between the solidification rate, a center temperature of the crystal, and the LPD number in the single crystal ingot.

(14) FIG. 14 is a graph showing results of Experiment 7, which shows a relationship between the solidification rate, a residence time at each of temperatures, and the LPD number when a temperature width is 30 degrees C.

(15) FIG. 15 is another graph showing the results of Experiment 7, which shows a relationship between the solidification rate, a residence time at each of temperatures, and the LPD number when the temperature width is 50 degrees C.

(16) FIG. 16 is still another graph showing the results of Experiment 7, which shows a relationship between the solidification rate and a residence time in each of temperatures, and the LPD number when a temperature width is 70 degrees C.

(17) FIG. 17 is a further graph showing the results of Experiment 7, which shows a relationship between the solidification rate and the residence time of the single crystal ingot.

(18) FIG. 18 is a still further graph showing results of Experiment 7, which shows a relationship between the solidification rate, the residence time at each of the temperatures, and the LPD number.

(19) FIG. 19 is a graph showing results of an experiment performed for verifying the results of Experiment 7, which shows a relationship between the solidification rate and the residence time at each of the temperatures, and the LPD number.

(20) FIG. 20 is a flowchart showing a manufacturing method of an epitaxial silicon wafer according to an exemplary embodiment of the invention.

(21) FIG. 21A is an illustration schematically showing a manufacturing process of the epitaxial silicon wafer according to the exemplary embodiment.

(22) FIG. 21B is another illustration schematically showing the manufacturing process of the epitaxial silicon wafer according to the exemplary embodiment.

(23) FIG. 21C is still another illustration schematically showing the manufacturing process of the epitaxial silicon wafer according to the exemplary embodiment.

(24) FIG. 21D is a further illustration schematically showing the manufacturing process of the epitaxial silicon wafer according to the exemplary embodiment.

(25) FIG. 21E is a still further illustration schematically showing the manufacturing process of the epitaxial silicon wafer according to the exemplary embodiment.

(26) FIG. 21F is a still further illustration schematically showing the manufacturing process of the epitaxial silicon wafer according to the exemplary embodiment.

DESCRIPTION OF EMBODIMENT(S)

(27) Exemplary embodiment(s) of the invention will be described below with reference to the attached drawings.

(28) As shown in FIG. 20, a single crystal ingot manufacturing step (step S1) is conducted in the manufacturing method of an epitaxial silicon wafer.

(29) In the single crystal ingot manufacturing step, a single crystal ingot 1 as shown in FIG. 21A is manufactured from a silicon melt added with red phosphorus (n-type dopant) according to CZ method (Czochralski process) using a pull-up device (not shown). A diameter of the single crystal ingot 1 is 200 mm. The single crystal ingot 1 includes a shoulder 11, a straight body 12 and a tail 13.

(30) In this exemplary embodiment, the single crystal ingot 1 is manufactured according to the following conditions so that the resistivity of silicon wafers cut out from the single crystal ingot 1 falls in a range from 0.6 m.Math.cm to 0.9 m.Math.cm.

(31) Red phosphorus concentration: 8.2910.sup.19 atoms/cm.sup.3 or more and 1.3210.sup.20 atoms/cm.sup.3 or less

(32) Oxygen concentration: 710.sup.17 atoms/cm.sup.3 or more and 1210.sup.17 atoms/cm.sup.3 or less

(33) In order to restrain a misfit dislocation, germanium of a concentration in a range from 3.7010.sup.19 atoms/cm.sup.3 to 2.9310.sup.20 atoms/cm.sup.3 may be added.

(34) Subsequently, as shown in FIG. 20, an evaluation wafer cut-out step for cutting out evaluation silicon wafers 141 as shown in FIG. 21B from the single crystal ingot 1 manufactured in the step S1 is performed (step S2).

(35) In the evaluation wafer cut-out step, a section of the straight body 12 of the single crystal ingot 1 that has been subjected to a temperature of 57070 degrees C. for more than 200 minutes in the single crystal ingot manufacturing step is cut out in a form of a cylindrical to-be-annealed block 14 as shown in FIG. 21A. Since the to-be-annealed block 14 has experienced the above-described temperature conditions, it is highly likely that clusters are generated in the to-be-annealed block 14.

(36) Then, the to-be-annealed block 14 is divided into three cylindrical small blocks 140. Subsequently, the evaluation silicon wafers 141 are cut out from an end of each of the small blocks 140 near the tail 13.

(37) It should be noted that the evaluation silicon wafers 141 may be cut out from both ends of each of the small blocks 140 or from an end of each of the small blocks 140 near the shoulder 11.

(38) Subsequently, as shown in FIG. 20, an evaluation annealing step is performed on the evaluation silicon wafers 141 cut out in the step S2 (step S3).

(39) In the evaluation annealing step, a pit-evaluation heat treatment is applied using a batch furnace that is capable of annealing at one time a plurality of evaluation silicon wafers 141. In the batch furnace, the evaluation silicon wafers 141 are subjected to a heat treatment at 1200 degrees C. for 30 seconds in a hydrogen gas atmosphere.

(40) Subsequently, a pit-observation step is performed on the silicon wafers 141 that has been subjected to the evaluation annealing step in the step S3 (step S4). In the pit-observation step, micropits are observed using a surface inspection system (Magics manufactured by Lasertec Corporation).

(41) Next, whether the micropits are observed or not in step S4 is judged (step S5).

(42) In the step S5, when it is judged that the micropits are observed (i.e. when there is one or more micropits of which diameter is 500 nm or more per one square centimeter (314 or more per one silicon wafer of 200 mm diameter)), product silicon wafers 142 are cut out as shown in FIGS. 21B and 21C from the small block(s) 140 from which the evaluation silicon wafer 141 has been cut out. Then, as shown in FIG. 20, the product silicon wafers 142 are subjected to the steps of a backside-oxidation-film-formation step (step S6), a backside-oxidation-film-removal step (step S7), an argon annealing step (step S8), a hydrogen baking step ((epitaxial-film-formation step) step S9), and an epitaxial film growth step ((epitaxial-film-formation step) step S10).

(43) In other words, since it is highly likely that the clusters are generated in the product silicon wafers 142, the silicon wafers 142 are subjected to all of the steps including the argon annealing step.

(44) Specifically, in the backside-oxidation-film-formation step of the step S6, a backside of each of the product silicon wafers 142 is subjected to a treatment according to the following conditions with a continuous normal-pressure CVD apparatus (AMAX1200 manufactured by Amaya Co., Ltd.) to form an oxidation film 16 (referred to as a backside oxidation film 16 hereinafter) on the backside of the product silicon wafer 142 as shown in FIG. 21D.

(45) Material gas: mixture gas of silane (SiH.sub.4) and oxygen (O.sub.2)

(46) Thickness of the backside proxidation film: 550 nm (in a range from 100 nm to 1500 nm)

(47) Film-formation temperature: 430 degrees C. (in a range from 400 to 450 degrees C.)

(48) The formation of the backside oxidation film 16 restrains the auto-doping.

(49) In the backside-oxidation-film-removal step (step S7), the oxidation film 16 present on the outer periphery of the backside of each of the product silicon wafers 142 is removed as shown in FIG. 21E with the use of various methods including polishing and etching (see, for instance, JP-A-2003-273063 and JP-A-2011-114210). The oxidation film 16 is preferably removed at an area less than 5 mm from an outer edge of each of the product silicon wafers 142.

(50) The removal of the backside oxidation film 16 at the outer periphery of the silicon wafer 142 restrains the generation of so-called nodules.

(51) In the argon annealing step (step S8), the batch furnace capable of annealing a plurality of product silicon wafers 142 at a single time is used to apply a heat treatment according to the following conditions. Atmosphere: argon gas Heat treatment temperature: from 1200 to 1220 degrees C. Heat treatment time: from 60 to 120 minutes

(52) The argon annealing step applies the solution treatment to the clusters to eliminate or reduce the clusters generated in the product silicon wafers 142.

(53) Incidentally, red phosphorus out-diffuses in the argon annealing step to form an out-diffusion layer of a thickness in a range from 0.65 m to 0.91 m is formed on the surface of the product silicon wafers 142, thereby increasing a transition region width. However, since the red phosphorus moves from a high-concentration area to a low-concentration area due to a heat treatment(s) in the subsequent device production process, little problem occurs.

(54) In the hydrogen baking step (step S9), a heat treatment is applied on each of the product silicon wafers 142 in an epitaxial apparatus according to the following conditions. Atmosphere: hydrogen gas Heat treatment temperature: 1200 degrees C. (in a range from 1050 to 1200 degrees C.) Heat treatment time: 30 seconds (in a range from 30 to 300 seconds)

(55) In other words, the heat treatment is applied under substantially the same conditions as the pit-evaluation heat treatment in the evaluation annealing step.

(56) The hydrogen baking step removes a natural oxidation film or particles adhered on the surface of the product silicon wafers 142, thereby cleaning the product silicon wafers 142.

(57) In the epitaxial film growth step (step S10), an epitaxial film is grown according to the following conditions on the product silicon wafers 142 after being subjected to the hydrogen baking step. Dopant gas: phosphine (PH.sub.3) gas Material source gas: trichlorosilane (SiHCl.sub.3) gas Carrier gas: hydrogen gas Growth temperature: 1080 degrees C. (in a range from 1000 to 1150 degrees C.) Thickness of the epitaxial film: 5 m (in a range from 1 m to 10 m) Resistivity (epitaxial film resistivity): 1 .Math.cm (in a range from 0.01 to 10 .Math.cm) (Red phosphorus concentration: 4.8610.sup.15 atoms/cm.sup.3 (in a range from 4.4410.sup.14 atoms/cm.sup.3 to 4.5310.sup.18 atoms/cm.sup.3))

(58) With the epitaxial film growth step being performed, an epitaxial silicon wafer 2 provided by forming an epitaxial film 17 on the surface of each of the product silicon wafers 142 as shown in FIG. 21F can be manufactured.

(59) Even when the clusters are generated in the product silicon wafers 142 before the backside-oxidation-film-formation step, the argon annealing step eliminates or reduces the clusters, so that the number of SF generated on the epitaxial silicon wafer 2 falls at or below one per square centimeter. Further, the number of LPD generated on a single epitaxial silicon wafer 2 falls at or below 314. Thus, a high-quality epitaxial silicon wafer 2 can be manufactured.

(60) In addition, since the argon annealing step is performed after performing the backside-oxidation-film-removal step, the out-diffusion of red phosphorus from the outer periphery uncovered by the backside oxidation film 16 can be promoted, thereby restraining the occurrence of auto-doping. Thus, the resistivity on the surface of the epitaxial film 17 can be equalized.

(61) On the other hand, when it is judged that the micropits are not observed in the step S5 as shown in FIG. 20, in other words, that one or more per square centimeter (314 or more per a single 200-mm-diameter silicon wafer) of the micropit of which diameter is 500 nm or more is not observed, the backside-oxidation-film-formation step (step S11), the backside-oxidation-film-removal step (step S12), the hydrogen baking step ((epitaxial-film-formation step) step S13) and epitaxial film growth step ((epitaxial-film-formation step) step S14) under the same conditions as the steps S6, S7, S9 and S10 are performed on the product silicon wafers 142 cut out from the small block 140 including the evaluation silicon wafer 141.

(62) In other words, since it is unlikely that the clusters are generated in the product silicon wafers 142, it is not necessary for the silicon wafers 142 to be subjected to the argon annealing step for solution treatment on the clusters. For the above reasons, all of the steps except for the argon annealing step are performed.

(63) With the above steps S11 to S14 being performed, a high-quality epitaxial silicon wafers 2 with one or less per square centimeter of SF (i.e. 314 or less of LPD per a single epitaxial silicon wafer 2) can be manufactured.

(64) Additionally, as shown in FIG. 21A, the section(s) that has experienced the temperature of 57070 degrees C. for 200 minutes or less (the section(s) near the tail 13 of the to-be-annealed block 14) in the single crystal ingot manufacturing step is cut out in a form of a cylindrical unnecessary-to-be-annealed block 15. Since the unnecessary-to-be-annealed block 15 is manufactured under the above-mentioned temperature conditions, it is extremely unlikely that the clusters are generated.

(65) The product silicon wafers are cut out from the unnecessary-to-be-annealed block 15 and are subjected only to the process of steps S11 to S14 without applying the above-described steps S2 to S10, whereby the above-described high-quality epitaxial silicon wafer 2 can be manufactured.

(66) Modifications

(67) It should be understood that the scope of the invention is not limited to the above-described exemplary embodiment(s) but various improvements and design alterations are possible as long as such improvements and alterations are compatible with the invention.

(68) For instance, without applying the processes according to the steps S2 to S5 and S11 to S14, the processes according to the steps S6 to S10 may be applied on all of the product silicon wafers 142 cut out from the straight body 12.

(69) Further, the unnecessary-to-be-annealed block 15 in the above exemplary embodiment may be cut out as the to-be-annealed block 14 and the processes according to the steps S2 to S14 may be applied on the to-be-annealed block 14. In other words, irrespective of whether or not being subjected to the temperature of 57070 degrees C. for 200 minutes or less in the single crystal ingot manufacturing step, the processes according to the steps S2 to S14 may be performed.