Method for causing tensile strain in a semiconductor film

Abstract

A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).

Claims

1. A method for producing a structure comprising a layer of strained semiconductor material, the method comprising steps consisting of: a) providing on a substrate a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask formed by one or a plurality of separate blocks, the mask being symmetrical with respect to a plane of symmetry, this plane of symmetry being orthogonal to a main plane of the substrate and passing through at least one first block of the mask, c) performing one or a plurality of inclined implantations with respect to a normal to the main plane of the substrate, so as to render amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the mask block(s), d) performing recrystallisation of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained.

2. The method according to claim 1, wherein the inclined implantations are symmetrical with respect to a plane of symmetry of the mask.

3. The method according to claim 1, wherein a first block of the mask is arranged facing a first region of the first semiconductor layer wherein a transistor channel is suitable for being produced.

4. The method according to claim 2, wherein the first block is a transistor gate pattern.

5. The method according to claim 1, wherein the mask is formed from a plurality of identical blocks arranged in the plane of symmetry according to a constant distribution interval.

6. The method according to claim 5, wherein the mask is formed by depositing at least one layer via block copolymer-based masking.

7. The method according to claim 1, wherein at least one block of the mask has a cylinder shape wherein a base extends along the second semiconductor layer.

8. The method according to claim 1, wherein one or a plurality of the blocks of the mask have a parallelepiped shape extending parallel with the main plane of the substrate and orthogonally to the plane of symmetry.

9. The method according to claim 1, further comprising after the recrystallisation step: a step for removing the second semiconductor layer.

10. The method according to claim 9, further comprising, after the step for removing the second semiconductor layer, the formation of a transistor having a gate wherein the gate is arranged facing the first region and wherein the channel extends entirely in the first region.

11. The method according to claim 10, wherein the first semiconductor layer is made of silicon, the second semiconductor layer is made of silicon-germanium.

12. The method according to claim 11, wherein the second semiconductor layer has a germanium concentration gradient.

13. The method according to claim 1, wherein the first semiconductor layer is rendered amorphous over the entire thickness thereof.

14. The method for forming a transistor comprising the use of a method according to claim 1.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The present invention will be understood more clearly on reading the description of examples of embodiments given merely by way of indication and in no way as a limitation, with reference to the appended figures wherein:

(2) FIGS. 1A-1F illustrate an example of a method for producing a first strained semiconductor-on-insulator layer wherein this first layer is rendered amorphous and then recrystallised by applying the lattice parameter of a second semiconductor layer thereto;

(3) FIG. 2 illustrates the use of a transistor wherein the channel region extends in the strained semiconductor layer and is provided outside zones wherein recrystallisation fronts met during recrystallisation;

(4) FIG. 3 illustrates an example of an implantation mask having a symmetrical arrangement and formed of cylindrical blocks suitable for protecting certain regions of the second semiconductor layer during amorphisation;

(5) FIGS. 4A-4C illustrate an alternative embodiment of a method wherein the implantation mask has a configuration suitable for creating uniaxial stress in the first semiconductor layer;

(6) Identical, similar or equivalent parts in the various figures bear the same reference numbers for an easier transition from one figure to another.

(7) The various parts represented in the figure are not necessarily represented according to a uniform scale, to render the figures more legible.

(8) Moreover, in the description hereinafter, terms such as lower, upper which are dependent on the orientation of the structure are applied considering that the structure is oriented in the manner illustrated in the figures.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

(9) An example of a method for producing a structure provided with a layer of strained semiconductor material will now be given with reference to FIGS. 1A-1F.

(10) The starting material of the method may be a semiconductor-on-insulator substrate 1, in particular a SOI substrate comprising a semiconductor base layer 2 for example made of Si, coated with an insulating layer 3 referred to as BOX (for Buried Oxide), in turn coated with a superficial semiconductor layer 4, for example based on Si, intended to be strained, and referred to hereinafter as the first semiconductor layer.

(11) On the first semiconductor layer 4, a second semiconductor layer 6 based on a semiconductor material having a different lattice parameter to that of the material of the first layer 4 is then grown epitaxially.

(12) When the first semiconductor layer 4 is based on silicon, the second semiconductor layer 6 may be envisaged based on silicon-germanium (Si.sub.1-xGe.sub.x where x for example is between 20 and 50%). In this case, during the epitaxial growth, the silicon-germanium tends to observe the lattice parameter of the silicon resulting in a compressive strained layer of Si.sub.1-xGe.sub.x.

(13) Preferably, the thickness e.sub.1 of the first semiconductor layer 4 is chosen below a critical thickness of plastic relaxation. This critical thickness is notably dependent on the stress level of the second semiconductor layer 6, this level being in turn dependent notably on the thickness e.sub.2 of the second semiconductor layer 6 and the lattice parameter of the constituent material thereof. When the second semiconductor layer 6 is based on Si.sub.1-xGe.sub.x, the critical thickness below which the thickness e.sub.1 of the superficial semiconductor layer 4 is chosen is dependent on the Germanium concentration of the second semiconductor layer 6. For example, it is possible to envisage a first semiconductor layer 4 made of silicon having a thickness e.sub.1 less than 10 nm when the second semiconductor layer 6 is made of Si.sub.1-xGe.sub.x where x is in the region of 0.20.

(14) The thickness e.sub.2 of the second semiconductor layer 6 may be greater than e.sub.1 and preferably as high as possible while remaining less than a critical thickness of plastic relaxation hc as mentioned for example in the document entitled: Critical thickness for plastic relaxation of SiGe by Hartmann et al. Journal of Applied Physics 2011.

(15) For example, when the second semiconductor layer 6 is made of Si.sub.1-xGe.sub.x, the thickness thereof may be envisaged in the region of 20 nm.

(16) FIG. 1A represents a step for forming an implantation mask 10 on the second semiconductor layer 6.

(17) This implantation mask 10 is configured to protect certain regions of the second semiconductor layer 6 during a subsequent ion implantation step. The material and the thickness of the implantation mask 10 are adapted according to the implantation condition and in particular the dose, energy, species envisaged for this implantation.

(18) According to one example, an implantation mask 10 is formed by etching a layer of HfO.sub.2 having a thickness in the region of 25 nm deposited on a 3 nm layer of SiO.sub.2. The layer wherein the block(s) of the mask 10 are produced may be etched according to an Al.sub.2O.sub.3 hard mask produced by ALD (Atomic Layer Deposition) type deposition via openings of block copolymer-based masking. The use of such masking may notably make it possible to produce an implantation mask 10 wherein the blocks have a homogeneous size and are distributed regularly on the second semiconductor layer 6.

(19) The implantation mask 10 may be formed from a plurality of separate blocks 10a, 10b, 10c, with a symmetry of distribution of the blocks 10a, 10b, 10c with respect to at least one given plane P, passing through the second semiconductor layer 6 and through at least one masking block, the given plane P being orthogonal to a main plane of the substrate 1. The term main plane of the substrate denotes herein and throughout the description a plane passing through the substrate and which is parallel with the plane [O; x; y] of the orthogonal reference point [O; x; y; z] given in FIG. 1A. In the example in FIG. 1A, the plane P of symmetry is a plane passing through a first masking block 10a and separating two equal portions of this first block 10a.

(20) The blocks 10a, 10b, 10c forming the mask 10 are distributed according to a constant interval in at least one direction parallel with the main plane of the substrate 1. As such, in the example in FIG. 1A, the blocks 10a, 10b, 10c are arranged such that a first minimum distance D1 min between the first block 10a and the second block 10b adjacent to the first block 10a is equal to a minimum distance D2 min between the first block 10a and the third block 10b adjacent to the first block 10a, D1 min, D2 min being equal to d, where d may be for example in the region of 1 to 4 times the length of the blocks 10a, 10b, 10c, this length being measured parallel with the y axis in FIG. 1A.

(21) According to one example of an embodiment, the blocks 10a, 10b, 10c may be envisaged with a length in the region of 1 to 3 times the thickness e.sub.2 of the second semiconductor layer 6. This length is measured parallel with the x axis in FIG. 1A.

(22) The blocks 10a, 10b, 10c may also be formed with a width equal or substantially equal to the length thereof. The width of the blocks is herein measured parallel with the y axis in FIG. 1A.

(23) Advantageously, among the blocks 10a, 10b, 10c of the mask 10, at least one block 10a is arranged facing a region 4a of the first semiconductor layer 4 wherein a transistor channel structure is envisaged.

(24) Subsequently, the first semiconductor layer 4 and certain zones 6 of the semiconductor layer 6 which are not protected by the mask 10 are rendered amorphous.

(25) For this, inclined ion implantations are performed, i.e. such that the ion beam creates an angle different to zero, also referred to as tilt, with a normal n to the main plane of the substrate 1. Regions 6a, 6b, 6c, of the semiconductor layer 6 arranged below the blocks 10a, 10b, 10c of the mask 10 and protected thereby are not rendered amorphous.

(26) The number of implantations made may be dependent on the shape of the blocks 10a, 10b, 10c of the mask 10. In one case, for example, where the blocks 10a, 10b, 10c have an equal width and length, implantations may be made according to four different quadrants, in other words four different orientations of the ion beam.

(27) FIG. 1B illustrates an embodiment of at least two inclined implantations symmetrical with one another with respect to the given plane P. Symmetrical implantations with respect to the plane P of symmetry are produced on either side of the plane of symmetry preferably with the same angle of inclination and equal respective energies and doses. FIG. 1C illustrates a use of at least two further inclined implantations symmetrically with one another with respect to a further plane P.

(28) The plane P is also a plane of symmetry of the mask. The plane P is this time orthogonal to the main plane of the substrate and to the given plane P. In the example illustrated in FIGS. 1B, 1C, the first layer is rendered amorphous over the entire thickness thereof.

(29) By way of example, in a case where the semiconductor layer 6 is a 20 nm layer of Si.sub.1-xGe.sub.x where x is equal to 20%, whereas the first semiconductor layer 4 is made of Silicon and has a thickness of 10 nm, and the mask 10 made of HfO.sub.2 has a thickness in the region of 10 nm, the amorphisation step may be carried out by means of Si implantations, according to a 20 tilt, a dose between 1.5 and 310.sup.14 at/cm.sup.2 and an energy between 20 and 30 keV.

(30) This amorphisation makes it possible to obtain a relaxation of the regions 6a, 6b, 6c of the semiconductor layer 6. Following the amorphisation, an arrangement of the regions 6a, 6b, 6c is obtained wherein the crystalline structure has been preserved which observes that of the blocks 10a, 10b, 10c of the implantation mask 10.

(31) The implantation mask 10 may then be removed. For example, when this mask 10 is made of W on SiO.sub.2, the removal may be carried out using hydrogen peroxide (H.sub.2O.sub.2) followed by hydrofluoric acid (HF).

(32) Then, recrystallisation of the first semiconductor layer 4 and the zones 6 rendered amorphous of the superficial layer 6 is performed, using the regions 6a, 6b, 6c wherein the crystalline structure has been preserved as zones of origin of recrystallisation fronts. FIG. 1D gives schematically and using arrows the direction of propagation of the recrystallisation fronts.

(33) Recrystallisation is performed using at least one thermal annealing. By way of example, in a case where the semiconductor layer 6 is a 20 nm layer of Si.sub.1-xGe.sub.x where x is equal to 20%, whereas the first semiconductor layer 4 is made of silicon and has a thickness of 10 nm, an annealing of at least 2 minutes at a temperature in the region of 600 C. may be performed.

(34) During the recrystallisation, the material of the regions 6a, 6b, 6c, for example Si.sub.1-xGe.sub.x, applies the lattice parameter thereof to that of the first semiconductor layer 4, which is then strained. When the first semiconductor layer 4 is based on Si, a layer 4 of strained silicon-on-insulator may be obtained.

(35) Due to the arrangement of the crystalline regions 6a, 6b, 6c with respect to the zones rendered amorphous, any crystalline nucleus rotation phenomena are limited which makes it possible to obtain, in the end, a recrystallised semiconductor material of enhanced quality and in particular of more uniform crystalline orientation.

(36) FIG. 1E represents the stack of semiconductor layers 4, 6 once recrystallisation has been performed. In this figure, dotted lines Z1, Z2 correspond to zones where the recrystallisation fronts meet.

(37) A region 4a of the first semiconductor layer 4 wherein a transistor channel region is envisaged is thus as removed as possible from zones where recrystallisation fronts meet, enabling the use of a transistor with enhanced electrical performances.

(38) Subsequently, the second semiconductor layer 6 is removed. This removal may be performed by selective etching with respect to the material of the first semiconductor layer 4.

(39) By way of example, the selective etching of the second semiconductor layer 6 when it is made of Si.sub.1-xGe.sub.x and arranged on a layer 4 of Si may be carried out using a mixture of acetic acid, hydrogen peroxide, and hydrofluoric acid.

(40) Following this removal, a strained semiconductor-on-insulator type substrate as illustrated in FIG. 1F is obtained, using which a microelectronic device may be produced.

(41) FIG. 2 represents a transistor structure T equipped with a channel structure provided in the region 4a of the first semiconductor layer 4 which is the most removed from the zones Z1, Z2 where the recrystallisation fronts meet.

(42) One alternative embodiment of the example of an embodiment described above envisages creating an implantation mask 100 formed in this case from blocks 100a, 100b, 100c having a cylinder shape wherein a base extends parallel to the main plane of the substrate 1.

(43) Such a mask 100 is represented in FIG. 3 as a top view.

(44) The mask 100 also has a symmetrical arrangement if considering a plane P of symmetry orthogonal to the main plane of the substrate and passing through at least one block 100a. This mask 100 may be formed by depositing a layer via masking made of a block copolymer material. Such a material is suitable for self-organising into a plane hexagonal lattice of cylinders of substantially circular or polygonal cross-section in a matrix. Such a material makes it possible to obtain satisfactory homogeneity of the masking patterns and distribution according to a constant interval. The masking material may be in particular a diblock copolymer wherein one of the polymers forms cylinders and wherein the other polymer forms a matrix. The diblock copolymer material may be for example one of the following: PS-PMMA (polystyrene-poly(methyl methacrylate)), PS-PVP (polystyrene-polyvinylpyrrolidone), PS-PEO (polystyrene-polyethylene oxide). The step for forming the masking patterns comprises the selective elimination of the cylinders with respect to the matrix. In one case, for example, where the cylinders are based on PMMA in a PS matrix, removal may be carried out using a method comprising immersion in a bath of acetic acid for a period of several minutes, followed by exposure to an argon and oxygen plasma. The mask 100 also has in this example a symmetrical arrangement if considering a further plane P of symmetry orthogonal to the main plane of the substrate and orthogonal to the plane P.

(45) With such a mask, it is possible to produce symmetrical and inclined amorphisation implantations with respect to the plane P or the plane P.

(46) A further alternative of the example of an embodiment described above is illustrated in FIGS. 4A-4C. This time, an implantation mask 110 comprising parallelepiped-shaped blocks 110a, 110b, 110c, which extend in the direction of the length thereof, parallel to the main plane of the substrate 1, is produced.

(47) Such a mask 110 is represented in FIG. 4A as a top view. The parallelepipedic block mask 110 also has a symmetrical arrangement with respect to a plane P of symmetry orthogonal to the main plane of the substrate and passing through the blocks 110a, 110b, 110c. The blocks 110a, 110b, 110c of the mask are arranged facing regions 4a, 4b, 4c of the first semiconductor layer 4 provided to respectively accommodate transistor channel regions. Advantageously, these blocks 110a, 110b, 110c have a similar pattern to that envisaged for gates 41, 42, 43 of transistors T.sub.1, T.sub.2, T.sub.3 intended to be produced on the regions 4a, 4b, 4c of the first semiconductor layer 4.

(48) As such, in this example, a block 110a of the mask extends facing the whole of the region 4a wherein the channel of the transistor T.sub.1 is envisaged.

(49) Inclined ion implantations are then performed in order to carry out the amorphisation of the first layer 4 and of zones 6 of the second layer. In this example, the amorphisation may be performed using implantations carried out on two different quadrants, in other words, as illustrated in FIG. 4B, using at least two inclined implantations symmetrical with one another with respect to a plane P. This plane P is orthogonal to the main plane of the substrate and to the plane P of symmetry of the mask 110.

(50) After this amorphisation, the recrystallisation steps are performed so as to strain the first semiconductor layer 4. Due to the arrangement of the mask 110 and the shape of these blocks 110a, 110b, 110c, it is possible, following the recrystallisation, to obtain a first semiconductor layer 4 subject to uniaxial strain in direction parallel to the main plane of the substrate and orthogonal to that wherein the blocks 110a, 110b, 110c of the mask 110 extend.

(51) Steps for removing the mask 110, removing the second semiconductor layer 6 are also implemented.

(52) FIG. 4C illustrates the subsequent embodiment of transistors T.sub.1, T.sub.2, T.sub.3 on regions 4a, 4b, 4c of the first semiconductor layer 4 facing which the blocks 100a, 100b, 100c of the mask were arranged. The arrangement of the respective channel regions 4a, 4b, 4c of the transistors T.sub.1, T.sub.2, T.sub.3 is envisaged outside zones where the recrystallisation fronts meet symbolised by the lines Z1, Z2, these zones being in this example situated at the source and drain blocks. As such, degradation of the performances of the channels of the transistors T.sub.1, T.sub.2, T.sub.3 is prevented.

(53) As an alternative embodiment of one or another of the methods described above, it is possible to envisage producing the implantation mask 10 from a strained material, such as tensile strained Silicon nitride, in order to increase the stress transferred during the recrystallisation of the zones 6 and the first semiconductor layer 4.

(54) According to a further alternative embodiment of one or another of the examples described above, a second layer made of Si.sub.1-yGe.sub.y is formed where y varies for example between y=0.20 at the lower face thereof, and y=0.50 at the upper face thereof.

(55) The term lower face denotes that in contact with the first semiconductor layer 4, whereas the so-called upper face is opposite the lower face.

(56) The second layer made of Si.sub.1-yGe.sub.y thus has a Germanium concentration gradient with a Germanium concentration which increases on moving away from the first semiconductor layer. This may make it possible to preserve crystalline regions having a high Germanium concentration below the blocks of the mask 10 following the amorphisation step. It is then possible to perform recrystallisation using crystal nuclei having a high Germanium concentration in order to obtain increased stress in the first semiconductor layer 4.

(57) A method according to the invention may be applied to other pairs of materials than silicon and silicon-germanium. A different stack of semiconductor layers 4 and 6 may be envisaged. For example, it is possible place a first strained semiconductor layer 4 made of Germanium this time by growing epitaxially a second semiconductor layer 6 made of a material having a higher lattice parameter such as for example Ge.sub.xSn.sub.1-x.

(58) According to a further example, a first strained semiconductor layer 4 made of In.sub.yGa.sub.1-yAs may be produced by growing a second semiconductor layer 6 made of In.sub.zAl.sub.1-zAs (where z>y).