LOW-NOISE MOS TRANSISTORS AND CORRESPONDING CIRCUIT

Abstract

An integrated circuit includes a MOS transistor situated in and on an active region of a semiconductor substrate. The active region is bounded by an insulating region for example of the shallow trench isolation type. The drain region of the transistor is positioned in the semiconductor substrate situated away from the insulating region. An insulated gate of the transistor includes a central opening that is positioned in alignment with the drain region. A channel region of the transistor is annularly surrounds the drain region.

Claims

1. An integrated circuit, comprising: a metal oxide semiconductor (MOS) transistor situated in and on an active region of a semiconductor substrate, wherein the active region is bounded by an insulating region, and wherein a drain region of the MOS transistor is positioned separated away from the insulating region.

2. The integrated circuit according to claim 1, wherein an insulated gate region of the MOS transistor has a hole which exposes a first part of the active region, this first part forming the drain region of the MOS transistor positioned separated away from the insulating region, and wherein a source region of the MOS transistor is positioned situated in a second part of the region on each side of the insulated gate region.

3. The integrated circuit according to claim 1, wherein the insulating region comprises a shallow trench isolation (STI) type insulating region.

4. The integrated circuit according to claim 1, wherein the semiconductor substrate is a silicon-on-insulator (SOI) type substrate. Customer No. 117381 Attorney Docket 140649-1141

5. The integrated circuit according to claim 1, wherein the semiconductor substrate is a fully-depleted silicon-on-insulator (FDSOI) type substrate.

6. The integrated circuit according to claim 1, insulated gate region of the MOS transistor has a hole positioned over the drain region of the MOS transistor.

7. An integrated circuit, comprising: a semiconductor substrate having an active region bounded by a shallow trench isolation, the semiconductor substrate further including a drain region and a source region; and an insulated gate positioned over the active region, said insulated gate having a central opening extending therethrough, said central opening being aligned with the drain region.

8. The integrated circuit of claim 7, wherein the semiconductor substrate further includes a channel region annularly surrounding the drain region.

9. The integrated circuit of claim 7, further comprising a drain contact extending through the central opening to make electrical contact to the drain region.

10. The integrated circuit of claim 7, wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate.

11. An integrated circuit, comprising: a semiconductor substrate having an active region bounded by a shallow trench isolation, the semiconductor substrate further including a drain region and an annularly surrounding channel region; and an insulated gate positioned over the active region, said insulated gate having a gate region annularly surrounding a central opening that is positioned over the drain region with the gate region positioned over the channel region.

12. The integrated circuit of claim 11, wherein the semiconductor substrate further includes a source region annularly surrounding the channel region.

13. The integrated circuit of claim 11, wherein the semiconductor substrate further includes a source region positioned between the channel region and the shallow trench isolation.

14. The integrated circuit of claim 13, wherein the source region is in contact with both the channel region and the shallow trench isolation.

15. The integrated circuit of claim 11, wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other advantages and features of the invention will become apparent upon studying the detailed description of embodiments, taken by way of non-limiting examples and illustrated by the appended drawings in which:

[0016] FIGS. 1 to 4 relate to various aspects of an electronic device.

DETAILED DESCRIPTION

[0017] Reference is now made to FIG. 1 in order to illustrate a schematic top view of an example of an integrated circuit CI. FIG. 2 is a cross-section along the line II-II in FIG. 1.

[0018] The integrated circuit CI comprises, in this example, a transistor T, for example of the NMOS type, situated in and on an active region ZA of a semiconductor substrate S.

[0019] By way of non-limiting example, here the semiconductor substrate S is a bulk substrate.

[0020] This active region ZA illustrated by a dashed line in FIG. 1 is bounded by an insulating region RI, here a shallow trench region of the STI type. The latter allows an efficient isolation to be provided between devices, such as transistors, of the integrated circuit CI and a higher density of integration.

[0021] The insulated gate region RGI of the transistor T comprises a central part PC disposed on top of the active region ZA, and a first lateral part PL1 and a second lateral part PL2 in the extension of the central part PC on top of the insulating region on either side of the active region ZA. Furthermore, the second lateral part PL2 here comprises a gate contact CG.

[0022] As illustrated in FIG. 2, the insulated gate region RGI of the transistor T comprises a gate region RG disposed on a dielectric region RDI itself situated on top of the active region ZA.

[0023] A hole is furthermore formed in the central part PC of the insulated gate region RGI, in such a manner as to expose a first part P1 of the active region ZA. An orifice OR is therefore formed in the middle of the central part PC.

[0024] It should be noted that the first part P1 of the active region ZA is away from the insulating region RI, in other words from the shallow trench region STI.

[0025] The drain region RD of the transistor T is then formed in the first part P1 in such a manner as to form a central drain region which is away from the insulating region RI.

[0026] The active region ZA furthermore comprises a second part P2 situated on either side of the insulated gate region RGI and forming the source region RS of the transistor T, as can be seen in FIGS. 1 and 2.

[0027] Accordingly, the transistor T has a double conduction channel CC, situated on either side of the drain region RD on which the shallow trench region STI has little influence. The 1/f noise of the transistor T is consequently minimized.

[0028] The steps for fabricating the transistor T are conventional except that for the formation of the insulated gate region, which comprises an additional etch step, for example a dry etch, in order to locally etch the gate material and the underlying dielectric in such a manner as to expose the first part P1 of the active region ZA.

[0029] During the step for formation of a metal silicide (silicidation step) on the active region ZA, the drain region RD is silicided through the orifice OR.

[0030] Source and drain contacts (not shown in FIGS. 1 and 2 for the sake of simplification) are formed on these regions in the same way as the gate contact CG.

[0031] Furthermore, insulating spacers (not shown in FIGS. 1 and 2 for the sake of simplification) are formed in a conventional manner known per se on the outer flanks of the gate region RGI and on the inner flanks of the latter bounding the orifice OR.

[0032] As a variant, the transistor T illustrated in FIGS. 1 and 2 may also be fabricated in and on a substrate S.sub.FDSOI of the fully-depleted silicon-on-insulator type, as illustrated in FIG. 3.

[0033] The references of the transistor T are unchanged since the structure of the transistor T remains the same in FIG. 3.

[0034] The substrate S.sub.FDSOI comprises a semiconductor film F, for example of silicon, situated on top of a buried insulating layer BOX, commonly denoted by the acronym BOX (Buried OXide), itself situated on top of a carrier substrate SP, for example a semiconductor well.

[0035] One part of the semiconductor film F forms the active region ZA of the transistor T comprising the source region RS, the drain region RD, and the double channel CC situated between the drain region RD and the source region RS.

[0036] In view of the limited thicknesses of the film F, the source and drain regions are elevated by epitaxy. For the sake of simplification of FIG. 3, this elevation is not shown.

[0037] As the buried insulating layer BOX is very thin, the carrier substrate SP itself can be biased in order to provide a back gate region in order to control the double conduction channel CC.

[0038] For this purpose, the substrate S.sub.FDSOI furthermore comprises at least one back gate contact area PCGA for example situated between two shallow trench regions STI, as illustrated in FIG. 3.

[0039] FIG. 4 illustrates a configuration diagram of another example of MOS transistor according to the invention.

[0040] As can be seen in FIG. 4, the integrated circuit CI comprises a transistor T, for example of the NMOS type, situated in and on an active region ZA of a substrate S.

[0041] The active region ZA is bounded by a shallow trench region STI and comprises a first part P1 forming the central drain region RD of the transistor T.

[0042] The insulated gate region RGI of the transistor T here takes the form of a ring. The insulated gate region RGI comprises an orifice OR at its center, so as to expose the first part P1, and comprises a gate contact CG.

[0043] The active region ZA furthermore comprises a second part P2 partially surrounding the insulated gate region RGI and forming the source region RS of the transistor T.

[0044] Advantageously, several drain contacts CD and source contacts CS are respectively formed on the drain region RD and the source region RS.

[0045] As illustrated in FIG. 4, the drain region RD is completely surrounded by the insulated gate region RDI and is therefore away from the shallow trench region STI.

[0046] Thus, a transistor T is obtained whose conduction channel is annular and away from the region STI. For this reason, the 1/f noise of the transistor T is decreased or even eliminated.

[0047] The invention is not limited to the embodiments that have just been described but encompasses all their variants.

[0048] Thus, although transistors of the NMOS type have been described, situated in and on an active region of a bulk substrate or of a substrate of the fully-depleted silicon-on-insulator (FDSOI) type, these transistors can also be PMOS transistors. Similarly, and independently of their type, NMOS or PMOS, the transistors may be formed on any given type of substrate of the silicon-on-insulator (SOI) type, and not only of totally-depleted (FDSOI) type.