ACCELERATED COMPUTER SYSTEM AND METHOD FOR WRITING DATA INTO DISCRETE PAGES

Abstract

The instant disclosure provides an accelerated computer system and an accelerated method for writing data into discrete pages. The accelerated method includes executing write commands, with each write command including write data and a write address such that the write address corresponds to a write page of the first pages in a block of a hard drive, identifying whether the write pages are successive according to the write addresses, acquiring stored data by reading the block according to the write addresses if the write pages are discrete, writing the data stored in the first pages into the second pages of a memory, writing write data bit by bit into the second pages according to the write addresses, and writing the data stored in the second pages into the first pages.

Claims

1. An accelerated computer system for writing data into discrete pages, comprising: a hard drive including a read-write head and a magnetic track, the magnetic track defining at least one sector, the sector having a plurality of successive first pages; a memory having a plurality of second pages, wherein the write speed over the second pages is faster than that over the discrete first pages; and a processor for executing a plurality of write commands, each write command including write data and a write address, the write address corresponding to a write page of the first pages, the processor determining whether the write pages are successive according to the write addresses, wherein when the write pages are discrete, the processor reads the first pages according to the write addresses and writes stored data read from the first pages into the second pages, with the processor writing the write data into the second pages, and after the write data is written into the memory, the processor writes the stored data of the second pages into the first pages.

2. The accelerated computer system of claim 1, wherein prior to determining whether the write pages are successive, the processor counts the number of write pages according to the write addresses, and compares the counted number to the number of the first pages of the sector, and wherein if the number of the write pages is greater than or equal to half of the number of the first pages, the processor then proceeds to determine whether the write pages are successive.

3. The accelerated computer system of claim 1, wherein the second pages are discrete and have a one-to-one mapping relationship with the first pages, with the processor writing the stored data of the first pages from the hard drive into the discrete second pages according to the one-to-one mapping relationship, and wherein the processor writes the stored data of the discrete second pages into the first pages according to the one-to-one mapping relationship after the write data is written into the memory.

4. The accelerated computer system of claim 1, wherein the processor determines whether another first page exists between any two write pages corresponding to the write addresses, and wherein if so, the processor determines the write pages are discrete.

5. The accelerated computer system of claim 1, wherein the second pages and the first pages have a one-to-one mapping relationship, with the write pages being within the range of two first pages while if the number of the write pages is greater than or equal to half the number of the first pages and the write pages are discrete, the processor reads the stored data within the range of the two first pages and writes the stored data into the second pages according to the one-to-one mapping relationship, and wherein after the processor has written the write data into the memory, the processor writes the stored data of the second pages corresponding to the range defined by the two first pages into the first pages within the range defined by the two first pages in accordance with the one-to-one mapping relationship.

6. An accelerated method of writing data into discrete pages for use with a hard drive, the hard drive including a read-write head and a magnetic region, the magnetic region defining at least one sector, the sector defining successive first pages, the write speed over the discrete first pages being less than that in a plurality of second pages of the memory, comprising: executing a plurality of write commands, with each write command including write data and a write address and the write address corresponding to a write page within the first pages; determining whether the write pages being successive according to the write addresses; reading the first pages according to the write addresses if the write pages being discrete; writing stored data of the first pages into the second pages; writing the write data into the second pages according to the write addresses; and writing the stored data of the second pages into the first pages.

7. The accelerated method of claim 6, wherein prior to determine whether the write pages are successive, the method further comprises: counting the number of the write pages; and determining whether the number of the write pages is greater than or equal to half of the number of the first pages prior to determine whether the write pages are successive.

8. The accelerated method of claim 6, wherein for the step of determining whether the write pages are successive according to the write addresses, the write pages corresponding to the write addresses are determined if any other first page exists in between any two write pages, and wherein if yes, the write pages are determined to be discrete.

9. The accelerated method of claim 6, wherein the second pages are discrete with the second pages and the first pages having a one-to-one mapping relationship, such that during the step of writing stored data of the first pages into the discrete second pages, the one-to-one mapping relationship is utilized to write the stored data of the first pages into the discrete second pages, and wherein during the step of writing the stored data of the second pages into the first pages, the one-to-one mapping relationship is utilized to write the stored data of the second pages into the first pages.

10. The accelerated method of claim 6, wherein the second pages and the first pages have a one-to-one mapping relationship, with the write pages being within the range of two first pages such that if the number of the write pages is greater than or equal to half of the number of the first pages, the stored data within the range defined by the two first pages are read during the step of reading the first pages according to the write addresses, wherein during the step of writing the stored data of the first pages into the second pages according to the write addresses, the stored data within the range defined by the two first pages is written into the second pages according to the one-to-one mapping relationship, and wherein during the step of writing the stored data of the second pages into the first pages, the stored data of the second pages corresponding to the range defined by the two first pages is written into the first pages within the range defined by the two first pages in accordance to the one-to-one mapping relationship.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a functional block diagram for one embodiment of the computer system of the instant disclosure.

[0013] FIG. 2 is a schematic view showing the structural components for one embodiment of a hard drive in FIG. 1.

[0014] FIG. 3A is a first schematic view of the data stored in the first and second pages in FIG. 1.

[0015] FIG. 3B is a second schematic view of the data stored in the first and second pages in FIG. 1.

[0016] FIG. 3C is a third schematic view of the data stored in the first and second pages in FIG. 1.

[0017] FIG. 3D is a fourth schematic view of the data stored in the first and second pages in FIG. 1.

[0018] FIG. 4A is a schematic view of a first embodiment for the first pages of FIG. 1 having discrete write pages.

[0019] FIG. 4B is a schematic view of a second embodiment for the first pages of FIG. 1 having discrete write pages.

[0020] FIG. 4C is a schematic view of a third embodiment for the first pages of FIG. 1 having discrete write pages.

[0021] FIG. 4D is a schematic view of one embodiment for the first pages of FIG. 1 having successive write pages.

[0022] FIG. 5 is a flowchart of a method for accelerating data writing into discrete pages for one embodiment of the instant disclosure.

DETAILED DESCRIPTION

[0023] FIG. 1 shows a functional block diagram for one embodiment of the computer system of the instant disclosure. FIG. 2 is a schematic view of the components of one embodiment of a hard drive 1 in FIG. 1. Please refer to FIGS. 1 and 2 simultaneously. The computer system comprises the hard drive 1, a processor 2, and a memory 3, where the processor 2 is coupled to the hard drive 1 and the memory 3. As shown in FIG. 2, the hard drive 1 includes a read-write head 11 and a plurality of magnetic tracks 12 having magnetic areas. The read-write head 11 is used for reading data from or writing data to the magnetic tracks 12. For each magnetic track 12, its magnetic areas individually define at least one block. The block has a plurality of successive pages for holding data. As shown in FIG. 1, taking a block 121 within the magnetic area of the hard drive 1 as an example, the block 121 has a plurality of first pages 121A121J arranged in succession. In other words, the addresses corresponding to the first pages 121A121J are successive. For instance, for an 8 bit address and assuming the address corresponding to the first page 121A is 0x00, if the address increment is 0x02, for hexadecimal the corresponding addresses of the first pages 121A121J are 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0xe, 0x10, and 0x12.

[0024] The memory 3 is used for data storage. As illustrated in FIG. 1, the memory 3 may include a plurality of second pages 31A31J for holding data. In particular, the data write speed over the second pages 31A31J is greater than that over discrete pages of the first pages 121A121J. The reason being, the read-write head 11 of the hard drive 1 needs to move back and forth between discrete pages among the first pages 121A 121J. In practice, the memory 3 can be a static random-access memory (SRAM), a dynamic random-access memory (DRAM), a flash memory, or any memory having a write speed greater than that over the discrete pages of the hard drive 1.

[0025] The processor 2 is for executing write commands. The write commands may be generated by the front-end circuit that is electrically connected to the processor 2 or by the processor 2 on its own. Each of the write commands includes a write address and corresponding data, where the write address corresponds to a page within a block of the hard drive 1. Taking FIG. 1 as an example, if the hard drive 1 receives the write address and write data from the processor 2, and the write address corresponds to the first pages 121A121J of the block 121, then the write data can be written into one of the write pages of the first pages 121A121J. In practice, the processor 2 may utilize software or firmware with application programming interface (API) to access the hard drive 1. Buses are used to connect the processor 2 to the hard drive 1 so that they can communicate with each other and perform bus transaction. Whereas the processor 2 may be a central processing unit (CPU), a micro controlling unit (MCU), or a control circuit specific for integrated circuit (IC) application (Application-Specific IC; ASIC).

[0026] When the processor 2 is executing the write commands, since the time it takes for the read-write head 11 of the hard drive 1 to writing data into discrete pages of the magnetic tracks 12 is greater than that for successive pages, the processor 2 would first determine whether the write pages are successive or discrete based on the write addresses. If the write pages are successive, the processor 2 writes write data directly into the hard drive 1 to implement the write command. However, if the write pages are discrete, the processor 2 can implement the write command in an accelerated mode, in order to reduce the time wasted while writing into discrete pages.

[0027] For the accelerated mode, the processor 2 reads the pages of the write pages within a block according to the write addresses. Taking the block 121 as an example, the processor 2 reads all the stored data of the first pages 121A121J of the block 121 and writes the stored data into the second pages 31A31J of the memory 3. Further, according to the write addresses, the processor 2 writes the write data bit by bit into the corresponding pages of the second pages 31A31J. For instance, the write data to be written into the first page 121A is written into the second page 31A. Similarly, the write data to be written into the first page 121E is written into the second page 31E. After all the data has been written into the memory 3, the processor 2 writes the stored data of the second pages 31A31J into the first pages 121A121J of the hard drive 1. Thereby, the first pages 121A121J of the hard drive 1 hold all of the updated write data. However, since the first pages 121A121J are successive, when writing the stored data of the second pages 31A31J into the first pages 121A121J of the hard drive 1, the read-write head 11 does not have to travel back and forth. Hence, the write time can be shortened as compared to conventional techniques.

[0028] For the instant embodiment, the first pages 121A121J and the second pages 31A31J have a one-to-one mapping relationship. Based on this relationship, the processor 2 reads the stored data of the first pages 121A121J and writes the stored data into the second pages 31A31J. After the write data has been written into the memory 3, the processor 2 rewrites the stored data of the second pages 31A31J into the first pages 121A121J based on the one-to-one mapping relationship. It should be noted that the exemplary embodiment in FIG. 1 is based on successive second pages 31A31J, but the instant disclosure is not restricted thereto.

[0029] In one embodiment, the second pages 31A31J may be discrete. That is to say the addresses corresponding to the second pages 31A31J can be discrete. Under such a circumstance, the processor 2 reads the stored data of the first pages 121A121J and writes the stored data into the discrete second pages 31A31J according to the abovementioned one-to-one mapping relationship. Then, after the write data has been written into the memory 3, the processor 2 reads the stored data of the discrete second pages 31A31J and writes the stored data of the discrete second pages 31A31J into the first pages 121A121J according to the one-to-one mapping relationship. In other words, as long as the processor 2 is capable of obtaining the one-to-one mapping relationship between the first pages 121A121J and the second pages 31A31J (e.g., by lookup tables), the second pages 31A31J can be dispersed among different regions in the memory 3 with discrete addresses.

[0030] FIGS. 3A-3D are schematic views showing the data updating process of stored data of the first pages 121A121J and the second pages 31A31J of FIG. 1, with the processor 2 executing the write commands under the accelerated mode. The illustrations are based on six write data files. As shown in FIG. 3A, prior to any execution steps, the first pages 121A121J include stored data, while the second pages 31A31J do not include stored data like the first pages 121A121J. As shown in FIG. 3B, under the accelerated mode, the processor 2 writes the stored data of the first pages 121A121J into the second pages 31A31J in a one-to-one manner, to make the stored data of the second pages 31A31J same as the stored data of the first pages 121A121J. Next, as shown in FIG. 3C, the processor 2 writes six pieces of write data namely 4, 1, 3, 13, 4, and 2 into the second pages 31A, 31C, 31D, 31H, 31I, and 31J, respectively, that correspond to six write addresses and overwrites original data. Lastly, as shown in FIG. 3D, the processor 2 writes the stored data of the second pages 31A31J into the first pages 121A121J in a one-to-one manner. Hence, the stored data of the first pages 121A, 121C, 121D, 121H, 121I, and 121J is updated to be 4, 1, 3, 13, 4, and 2, respectively, while other first pages 121B, 121E, 121F, and 121G keep the original stored data.

[0031] For the instant embodiment, when the processor 2 is determining whether the write pages are discrete, the processor 2 determines if there is any other first page in between any two write pages corresponding to the write addresses. If yes, the processor 2 determines the write pages are discrete. FIGS. 4A-4D show the schematic views of four embodiments of the first pages 121A121J of FIG. 1 having discrete write pages and successive write pages. Taking the write pages of block 121 as an example, the grey-colored first pages represent the write pages. As shown in FIG. 4A, each pair of the write pages has one non-write page in between, namely 121B, 121D, 121F, and 121H. As shown in FIG. 4B, the write pages (i.e., the first pages 121D and 121F; 121H and 121J), have non-write pages 121E and 121I sandwiched in between, respectively. As shown in FIG. 4C, two write pages (that is first pages 121D and 121F), has a non-write first page 121E in between. As shown in FIG. 4D, there is no page sandwiched in between the write pages of the first pages 121C121G. Thus, based on FIGS. 4A-4D, as long as if any other first page is in between two write pages, the write pages are taken as discrete.

[0032] Furthermore, prior to determining whether the write pages are discrete, the processor 2 first determines whether the number of write pages is greater than or equal to half of the number of total pages in the block based on the write addresses. Taking FIG. 1 as an example and assuming the write pages are in the block 121, the processor 2 determines whether the number of write pages in block 121 is greater than or equal to half of the number of first pages 121A121J (i.e., five). If the number of write pages in block 121 is greater than or equal to five, the processor 2 starts to determine whether the write addresses are successive. However, if the number of write pages in block 121 is less than five, regardless whether the write pages are successive or discrete, the processor 2 writes write data directly into the write pages of the first pages 121A121J. For example, assuming the processor 2 intends to executes five write commands, with the write pages of three write commands being in the block 121, since the number of write pages is less than five, the processor 2 directly writes the write data bit by bit into the three write pages without determining whether they are successive or not. On the other hand, if the write pages of all five write commands are in the block 121, since the number of write pages is five, the processor 2 proceeds to determine whether those five write pages are successive.

[0033] In one embodiment, the write pages are located between two first pages within the range of 121A121J. Taking the write pages in the block 121 as an example, after the processor 2 has determined that the number of write pages is greater than or equal to five and the write pages are discrete, the processor 2 reads the stored data between the two first pages. Based on the one-to-one mapping relationship, the processor 2 writes the stored data between the two first pages into the corresponding second pages. In other words, the processor 2 is capable of writing stored data of the first pages for a portion of the block 121 into the memory 3 according to the write address status.

[0034] For example, if the write addresses correspond to the first pages 121B, 121D, 121E, 121G, and 121I, under such a circumstance, when the write pages are located between the first pages 121B and 121I, the processor 2 reads the stored data from the first pages 121B121I. Then, based on the aforementioned one-to-one mapping relationship, the processor 2 writes the stored data of the first pages 121B121I into the corresponding pages of the second pages 31A31J, such as the second pages 31B31I or different locations in the memory 3 with discrete addresses.

[0035] Next, according to the write addresses, the processor 2 writes the write data bit by bit into the corresponding pages of the second pages 31B-31I of the memory 3. For instance, the write data to be written into the first page 121B is written into the second page 31B, and the write data to be written into the first page 121D is written into the second page 31D. After all the data has been written into the memory 3, based on the aforementioned one-to-one mapping relationship, the processor 2 rewrites the stored data of the second pages 31A31J corresponding to the first page range of 121B to 121I back to the first pages 121B121I within the range of 121A121J. In other words, the processor 2 writes the stored data of the second pages 31B31I back to the first pages 121B121I, such as writing the stored data of the second page 31B into the first page 121B. Hence, the first pages 121B121I of the hard drive 1 are stored with updated write data. Since the first pages 121B121I are successive, when writing the stored data of the second pages 31B31I into the first pages 121B121I of the hard drive 1 in a single operation, the read-write head 11 does not have to move back and forth, which helps reduce the write time as comparing to the conventional technique.

[0036] FIG. 5 is a flowchart of the accelerated method of writing data into discrete pages for one embodiment of the instant disclosure. Please refer to FIGS. 1 and 5 simultaneously. As an example, when the write commands include write pages corresponding to the block 121, the processor 2 executes these write commands and counts the number of write pages (step S11). The processor 2 then determines whether the number of write pages is greater than or equal to half of the number of first pages 121A121J (step S12) before determining whether to perform step S14. If no, the processor 2 writes the write data into the write pages of the first pages 121A121J according to the write addresses (step S13). In other words, the processor 2 is not operated under the accelerated mode. However, if yes, according to the write addresses of the write commands, the processor 2 determines whether the write pages are successive (step S14). After implementing step S14, if the write pages are successive (i.e., yes), the processor 2 proceeds to execute step S13, which means the processor 2 does not operate under the accelerated mode. However, if the write pages are discrete (i.e., no), the processor 2 reads the first pages 121A121J of the block 121 according to the write addresses (step S15). Then, the processor 2 writes the stored data of the first pages 121A 121J into the second pages 31A31J of the memory 3 (step S16). After step S16 is completed, the processor 2 writes the write data into the second pages 31A31J according to the write addresses (step S17). Finally, the processor 2 writes the stored data of the second pages 31A31J into the first pages 121A121J (step S18).

[0037] In step S14, the processor 2 determines whether there is any other first page existing between any two write pages of the corresponding write addresses. If yes, the processor 2 determines that the write pages are discrete and proceeds to step S15.

[0038] In some embodiments, the second pages 31A31J of the memory 3 have a one-to-one mapping relationship with the first pages 121A121J of the hard drive 1, while the second pages 31A31J are discrete. In step S16, according to the abovementioned one-to-one mapping relationship, the processor 2 writes the stored data of the first pages 121A121J into the discrete second pages 31A31J. In step S18, based on the same one-to-one mapping relationship, the processor 2 writes the stored data of the discrete second pages 31A31J into the first pages 121A121J.

[0039] In one embodiment, if the number of write pages is greater than or equal to five, with the write pages falling in the range of 121B121I of the first pages 121A121J, the processor 2 in step S15 reads the stored data that falls in the range of 121B121I (i.e., first pages 121B121I). For step S16, based on the aforementioned one-to-one mapping relationship, the processor writes the stored data within the range of 121B121I to the successive or discrete pages of the second pages 31A31J, such as second pages 31B 31I. Then, in step S18, based on the aforementioned one-to-one mapping relationship, the processor 2 writes the stored data of the second pages 31A31J corresponding to the range of 121B121I into the write pages ranging from 121B to 121I and overwrites the original data.

[0040] Based on the above, in accordance to an embodiment of the accelerated computer system and method for writing data into discrete pages, when writing data into the pages of a hard drive, the processor can begin with writing stored data in succession of discrete write pages of a disk block into the second pages of a memory. Also, for data to be written into the hard drive, the processor writes the data into the corresponding second pages. In comparing to the data within the hard drive, the second pages include updated or original stored data. Then, the processor writes all or a portion of stored data of the second pages into the aforementioned block of the hard drive. Hence, the pages within the block can be written over successively according to the write addresses. Thus, the time wasted by writing into discrete pages can be reduced, and the write speed of the hard drive can be increased.

[0041] While the instant disclosure has been described by way of example and in terms of the preferred embodiments, it is to be understood that the instant disclosure needs not be limited to the disclosed embodiments. For anyone skilled in the art, various modifications and improvements within the spirit of the instant disclosure are covered under the scope of the instant disclosure. The covered scope of the instant disclosure is based on the appended claims.