An apparatus comprises at least one processing device configured to identify a snapshot lineage comprising snapshots of a storage volume, the snapshot lineage comprising (i) a local snapshot lineage stored on a storage system and (ii) cloud snapshot lineages stored on cloud storage external to the storage system, to select at least one snapshot that is to be copied from the local snapshot lineage, to determine at least two of the cloud snapshot lineages as destinations for the selected snapshot, to generate a snapshot copy job for copying the selected snapshot to the at least two cloud snapshot lineages, and to process the snapshot copy job by reading data of the selected snapshot stored in the local snapshot lineage once and writing the data of the selected snapshot to the at least two cloud snapshot lineages.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A computer-implemented method according to one embodiment includes causing a plurality of I/O queues to be created between an initiator and a storage target device. The created I/O queues are reserved for I/O requests for which adjustments of current priorities of extents of data associated with the I/O requests are to be performed. The method further includes determining identifying information of an I/O request sent from the initiator to the storage target device and determining whether the I/O request was sent from the initiator to the storage target device using one of the created I/O queues. In response to a determination that the I/O request was sent using a first of the created I/O queues having one of the adjustments associated therewith, a tiering manager of the storage target device is instructed to perform the adjustment on the current priority of the extent of data associated with the I/O request.

Methods, systems, and devices for adjusting a granularity associated with read disturb tracking are described. In some examples, a memory system may receive a set of read commands from a host system instructing the memory system to read data stored at a memory array. The memory system may track a quantity of executed read commands corresponding to a first portion of the memory array according to a first granularity and determine whether the quantity of read commands satisfies a threshold. If the quantity of read commands satisfies the threshold, the memory system may adjust the granularity for tracking executed read commands for the first portion from the first granularity to a second granularity. For example, the memory system may increase or decrease the granularity for tracking executed read commands for the first portion. The memory system may use the tracked quantities of executed read commands for read disturb remediation.

Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.

A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

The present invention discloses a method for external devices accessing computer memory, which includes: the external device applying to a computer for a memory space with a certain size, and receiving multiple memory blocks fed back by the computer; the external device establishing a memory mapping relation between the external device and the computer by means of a sequential storage structure or a chain storage structure; and when initiating a read-and-write operation, the external device finding the corresponding offset address in said computer according to the memory mapping relation between the external device and the computer, generating a read-and-write burst command, and actualizing read-and-write operations in the computer memory. The present invention can achieve the rapid and continuous access to multiple discontinuous memory areas of the computer memory, and improve the speed in the computer’s operating system and external devices accessing the memory.

A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.