Rectifier circuit including transistor whose channel formation region includes oxide semiconductor

Abstract

In a rectifier circuit, by using a transistor whose off-state current is small as a so-called diode-connected MOS transistor included in the rectifier circuit, breakdown which is caused when a reverse bias is applied is prevented. Thus, an object is to provide a rectifier circuit whose reliability is increased and rectification efficiency is improved. A gate and a drain of a transistor are both connected to a terminal of the rectifier circuit to which an AC signal is input. In the transistor, an oxide semiconductor is used for a channel formation region and the off-state current at room temperature is less than or equal to 10.sup.20 A/m, which is equal to 10 zA/m (z: zepto), when the source-drain voltage is 3.1 V.

Claims

1. A rectifier circuit comprising: a transistor; an input terminal; a capacitor; and an output terminal, wherein a gate of the transistor and one of a source and a drain of the transistor are electrically connected to the input terminal, wherein the gate of the transistor is directly connected to the one of the source and the drain of the transistor, wherein the other of the source and the drain of the transistor and an electrode of the capacitor are electrically connected to the output terminal, wherein the transistor comprises a channel formation region comprising an oxide semiconductor, and wherein off-state current of the transistor at room temperature is less than or equal to 10 zA/m when source-drain voltage is 3.1V.

2. The rectifier circuit according to claim 1, wherein a carrier density in the oxide semiconductor is lower than 110.sup.12/cm.sup.3.

3. The rectifier circuit according to claim 1, wherein the oxide semiconductor is purified by removing impurities and supplying oxygen.

4. The rectifier circuit according to claim 1, wherein the transistor comprises: an oxide semiconductor layer over an insulating layer, the oxide semiconductor layer comprising the channel formation region; a source electrode over the oxide semiconductor layer and the insulating layer; a drain electrode over the oxide semiconductor layer and the insulating layer; a gate insulating layer over the oxide semiconductor layer, the source electrode and the drain electrode, the gate insulating layer comprising a first opening and a second opening; and a gate electrode over the gate insulating layer, wherein a part of the source electrode is in contact with the insulating layer, wherein a part of the drain electrode is in contact with the insulating layer, wherein a first wiring over the gate insulating layer is in contact with the part of the source electrode through the first opening, and wherein a second wiring over the gate insulating layer is in contact with the part of the drain electrode through the second opening.

5. A rectifier circuit comprising: a first transistor; a second transistor; an input terminal; a first capacitor; a second capacitor; and an output terminal, wherein a first electrode of the first capacitor is electrically connected to the input terminal, wherein one of a source and a drain of the first transistor, a gate of the first transistor, and one of a source and a drain of the second transistor are electrically connected to a second electrode of the first capacitor, wherein the other of the source and the drain of the first transistor and a first electrode of the second capacitor are electrically connected to the output terminal, wherein a gate of the second transistor, and the other of the source and the drain of the second transistor are electrically connected to a second electrode of the second capacitor, wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor, and wherein off-state current of each of the first transistor and the second transistor at room temperature is less than or equal to 10 zA/m when source-drain voltage is 3.1 V.

6. The rectifier circuit according to claim 5, wherein a carrier density in the oxide semiconductor is lower than 110.sup.12/cm.sup.3.

7. The rectifier circuit according to claim 5, wherein the oxide semiconductor is purified by removing impurities and supplying oxygen.

8. The rectifier circuit according to claim 5, wherein the gate of the first transistor is directly connected to the one of the source and the drain of the first transistor, and wherein the gate of the second transistor is directly connected to the other of the source and the drain of the second transistor.

9. The rectifier circuit according to claim 5, wherein the first transistor comprises: an oxide semiconductor layer over an insulating layer, the oxide semiconductor layer comprising the channel formation region; a source electrode over the oxide semiconductor layer and the insulating layer; a drain electrode over the oxide semiconductor layer and the insulating layer; a gate insulating layer over the oxide semiconductor layer, the source electrode and the drain electrode, the gate insulating layer comprising a first opening and a second opening; and a gate electrode over the gate insulating layer, wherein a part of the source electrode is in contact with the insulating layer, wherein a part of the drain electrode is in contact with the insulating layer, wherein a first wiring over the gate insulating layer is in contact with the part of the source electrode through the first opening, and wherein a second wiring over the gate insulating layer is in contact with the part of the drain electrode through the second opening.

10. A wireless communication device comprising: an antenna, and a rectifier circuit comprising: a transistor; an input terminal; a capacitor; and an output terminal, wherein a gate of the transistor and one of a source and a drain of the transistor are electrically connected to the input terminal, wherein the other of the source and the drain of the transistor and an electrode of the capacitor are electrically connected to the output terminal, wherein the transistor comprises a channel formation region comprising an oxide semiconductor, wherein off-state current of the transistor at room temperature is less than or equal to 10 zA/m when source-drain voltage is 3.1 V, and wherein an AC signal received by the antenna is inputted into the input terminal.

11. The wireless communication device according to claim 10, wherein a carrier density in the oxide semiconductor is lower than 110.sup.12/cm.sup.3.

12. The wireless communication device according to claim 10, wherein the oxide semiconductor is purified by removing impurities and supplying oxygen.

13. The wireless communication device according to claim 10, wherein the gate of the transistor is directly connected to the one of the source and the drain of the transistor.

14. The wireless communication device according to claim 10, wherein the transistor comprises: an oxide semiconductor layer over an insulating layer, the oxide semiconductor layer comprising the channel formation region; a source electrode over the oxide semiconductor layer and the insulating layer; a drain electrode over the oxide semiconductor layer and the insulating layer; a gate insulating layer over the oxide semiconductor layer, the source electrode and the drain electrode, the gate insulating layer comprising a first opening and a second opening; and a gate electrode over the gate insulating layer, wherein a part of the source electrode is in contact with the insulating layer, wherein a part of the drain electrode is in contact with the insulating layer, wherein a first wiring over the gate insulating layer is in contact with the part of the source electrode through the first opening, and wherein a second wiring over the gate insulating layer is in contact with the part of the drain electrode through the second opening.

15. A wireless communication device comprising: an antenna, and a rectifier circuit comprising: a first transistor; a second transistor; an input terminal; a first capacitor; a second capacitor; and an output terminal, wherein a first electrode of the first capacitor is electrically connected to the input terminal, wherein one of a source and a drain of the first transistor, a gate of the first transistor, and one of a source and a drain of the second transistor are electrically connected to a second electrode of the first capacitor, wherein the other of the source and the drain of the first transistor and a first electrode of the second capacitor are electrically connected to the output terminal, wherein a gate of the second transistor, and the other of the source and the drain of the second transistor are electrically connected to a second electrode of the second capacitor, wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor, wherein off-state current of each of the first transistor and the second transistor at room temperature is less than or equal to 10 zA/m when source-drain voltage is 3.1 V, and wherein an AC signal received by the antenna is inputted into the input terminal.

16. The wireless communication device according to claim 15, wherein a carrier density in the oxide semiconductor is lower than 110.sup.12/cm.sup.3.

17. The wireless communication device according to claim 15, wherein the oxide semiconductor is purified by removing impurities and supplying oxygen.

18. The wireless communication device according to claim 15, wherein the gate of the first transistor is directly connected to the one of the source and the drain of the first transistor, and wherein the gate of the second transistor is directly connected to the other of the source and the drain of the second transistor.

19. The wireless communication device according to claim 15, wherein the first transistor comprises: an oxide semiconductor layer over an insulating layer, the oxide semiconductor layer comprising the channel formation region; a source electrode over the oxide semiconductor layer and the insulating layer; a drain electrode over the oxide semiconductor layer and the insulating layer; a gate insulating layer over the oxide semiconductor layer, the source electrode and the drain electrode, the gate insulating layer comprising a first opening and a second opening; and a gate electrode over the gate insulating layer, wherein a part of the source electrode is in contact with the insulating layer, wherein a part of the drain electrode is in contact with the insulating layer, wherein a first wiring over the gate insulating layer is in contact with the part of the source electrode through the first opening, and wherein a second wiring over the gate insulating layer is in contact with the part of the drain electrode through the second opening.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) In the accompanying drawings:

(2) FIGS. 1A and 1B are circuit diagrams illustrating configurations of rectifier circuits;

(3) FIG. 2 is a graph showing reverse-bias static characteristics of diode-connected transistors included in a rectifier circuit;

(4) FIG. 3 is a diagram of a circuit for evaluating characteristics of a transistor in which an oxide semiconductor is used for a channel formation region;

(5) FIG. 4 is a graph showing characteristics of a transistor in which an oxide semiconductor is used for a channel formation region;

(6) FIG. 5 is a graph showing characteristics of a transistor in which an oxide semiconductor is used for a channel formation region;

(7) FIG. 6 is a graph showing characteristics of a transistor in which an oxide semiconductor is used for a channel formation region;

(8) FIG. 7 is a graph showing a diode characteristic of a diode-connected transistor in which an oxide semiconductor is used for a channel formation region;

(9) FIGS. 8A to 8E are views illustrating an example of a method for manufacturing a transistor; and

(10) FIGS. 9A and 9B are graphs showing input voltage and output voltage of rectifier circuits.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1

(11) As a transistor included in a rectifier circuit, a transistor described below is used, in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region.

(12) <Transistor in which Oxide Semiconductor is Used for Channel Formation Region>

(13) An oxide semiconductor disclosed in this specification will be described. Impurities such as hydrogen, water, a hydroxyl group, or hydroxide (also referred to as a hydrogen compound) which serve as donors are intentionally removed from the oxide semiconductor included in the transistor, and then oxygen which is simultaneously reduced in the step of removing these impurities is supplied, so that the oxide semiconductor is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic). The purpose of this treatment is to suppress fluctuation in electric characteristics of the transistor.

(14) Hydrogen included in the oxide semiconductor is removed as much as possible; thus, the carrier density in the oxide semiconductor is lower than 110.sup.14/cm.sup.3, preferably lower than 110.sup.12/cm.sup.3, further preferably lower than 110.sup.10/cm.sup.3.

(15) In an oxide semiconductor, which is a wide bandgap semiconductor, the density of the minority carrier is low and the minority carrier is difficult to be induced. Thus, it can be said that, in the transistor in which an oxide semiconductor is used for the channel formation region, tunneling current is difficult to be generated; consequently, off-state current is difficult to flow.

(16) In addition, impact ionization and avalanche breakdown are less likely to occur in the transistor in which the oxide semiconductor, which is a wide bandgap semiconductor, is used for the channel formation region. The hot carrier deterioration is mainly caused by increase in the number of carriers due to avalanche breakdown and by injection of the carriers accelerated to high speed to a gate insulating film. Therefore, it can be said that the transistor in which an oxide semiconductor is used for the channel formation region has resistance to hot carrier deterioration.

(17) Note that in this specification, off-state current refers to current that flows between a source and a drain of an n-channel transistor whose threshold voltage Vth is positive when a given gate voltage of higher than or equal to 20 V and lower than or equal to 5 V is applied at room temperature. Note that the room temperature refers to a temperature of higher than or equal to 15 C. and lower than or equal to 25 C.

(18) The current value per micrometer in a channel width W at room temperature of the transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for the channel formation region is less than or equal to 10.sup.16 A/m, preferably less than or equal to 10.sup.18 A/m, which is equal to 1 zA/m (a: atto), further preferably less than or equal to 10.sup.21 A/m, which is equal to 1 zA/m (z: zepto).

(19) <Result of Measurement of Off-State Current>

(20) Results of measurement of off-state current of a transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region will be described.

(21) First, an element for characteristic evaluation which is used for a method for measuring current will be described with reference to FIG. 3. In the element for characteristic evaluation in FIG. 3, three measurement systems 30 are connected in parallel. Each of the measurement systems 30 includes a capacitor C30, transistors M30 and M31 in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for channel formation regions, and transistors M32 and M33.

(22) One of a source and a drain of the transistor M30 is connected to a power source which supplies voltage V2. The other of the source and the drain of the transistor M30 is connected to one of a source and a drain of the transistor M31. A gate of the transistor M30 is connected to a wiring through which voltage Vext_b2 is supplied.

(23) The other of the source and the drain of the transistor M31 is connected to a power source which supplies voltage V1. A gate of the transistor M31 is connected to a wiring through which voltage Vext_b1 is supplied.

(24) One of a source and a drain of the transistor M32 is connected to the power source which supplies the voltage V2. The other of the source and the drain of the transistor M32 is connected to an output terminal A gate of the transistor M32 is connected to one terminal of the capacitor C30.

(25) One of a source and a drain of the transistor M33 is connected to the output terminal. The other of the source and the drain of the transistor M33 is connected to a gate thereof.

(26) The other terminal of the capacitor C30 is connected to the power source which supplies the voltage V2.

(27) Next, a method for measuring current with the use of the element for characteristic evaluation illustrated in FIG. 3 will be described. First, an initial period in which a potential difference is applied to measure the off-state current will be described. In the initial period, the voltage Vext_b1 with which the transistor M31 is turned on is input to the gate of the transistor M31, so that the transistor M31 is turned on. Consequently, the voltage V1 is input to a node A which is a node connected to the other of the source and the drain of the transistor M30 (i.e., a node connected to the one of the source and the drain of the transistor M31, the one terminal of the capacitor C30, and the gate of the transistor M32). Here, the voltage V1 is high voltage. In addition, the transistor M30 is off.

(28) After that, the voltage Vext_b1 with which the transistor M31 is turned off is input to the gate of the transistor M31, so that the transistor M31 is turned off. After the transistor M31 is turned off, the voltage V1 is set to low. Here, the transistor M30 is still off. The voltage V2 as well as the voltage V1 is set to low.

(29) In the above manner, the initial period is completed. In the state where the initial period is completed, a potential difference is generated between the node A and the one of the source and the drain of the transistor M30. Further, a potential difference is generated between the node A and the other of the source and the drain of the transistor M31. Accordingly, electric charge slightly flows through the transistor M30 and the transistor M31. That is, off-state current is generated.

(30) Next, a measurement period of the off-state current will be described. In the measurement period, the voltage V1 and the voltage V2 are both fixed to low. In addition, the node A is in a floating state. As a result, electric charge flows through the transistor M30, and the amount of electric charge stored in the node A is changed as time passes. In other words, the potential of the node A is changed and output potential V.sub.out of the output terminal is also changed.

(31) Next, a method for calculating the off-state current on the basis of the obtained output potential V.sub.out will be described. A potential V.sub.A of the node A is expressed by Formula 1 as a function of the output potential V.sub.out.
[Formula 1]
V.sub.A=F(V.sub.out)(1)

(32) Electric charge Q.sub.A of the node A is expressed by Formula 2.
[Formula 2]
Q.sub.A=C.sub.AV.sub.A+const(2)
C.sub.A: capacitance connected to the node A (the sum of the capacitance of the capacitor C30 and the other capacitance).

(33) Current I.sub.A of the node A can be obtained by differentiating electric charge flowing to the node A (or electric charge flowing from the node A) with respect to time. Accordingly, the current I.sub.A of the node A is expressed by Formula 3.

(34) $\begin{matrix} [Formula 3] \\ I_{A} \frac{Q_{A}}{t} = \frac{C_{A} .Math. F (V_{out})}{t} & (3) \end{matrix}$

(35) In current measurement described below, the transistors M30 and M31 in the element for characteristic evaluation are each a transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for the channel formation region. In each of the transistors, W/L is 50/10 [m]. In addition, in the measurement systems 30 connected in parallel, respective capacitance values of the capacitors C30 are 100 fF, 1 pF, and 3 pF.

(36) The high voltage is set at 5 V, and the low voltage is set at 0 V. The voltage V1 is basically low in the measurement period; the voltage V1 is set to high for only 100 msec in every 10 sec to 300 sec because an output circuit needs to be operated at a timing of measuring the output potential V.sub.out. In addition, t in Formula 3 is approximately 30000 [sec].

(37) FIG. 4 shows the relation between elapsed time Time in the current measurement and the output potential V.sub.out. According to FIG. 4, the potential is changed as time passes.

(38) FIG. 5 shows the off-state current at room temperature (25 C.) calculated on the basis of the current measurement. Note that FIG. 5 shows the relation between source-drain voltage V and off-state current I. According to FIG. 5, the off-state current I is approximately 40 zA/m when the source-drain voltage is 4 V. In addition, the off-state current is less than or equal to 10 zA/m when the source-drain voltage is 3.1 V.

(39) FIG. 6 shows the off-state current in an environment at a temperature of 85 C., which is calculated on the basis of the current measurement. FIG. 6 shows the relation between the source-drain voltage V and the off-state current I in the environment at a temperature of 85 C. According to FIG. 6, the off-state current is less than or equal to 100 zA/m when the source-drain voltage is 3.1 V.

(40) <Configuration of Rectifier Circuit>

(41) A rectifier circuit illustrated in FIG. 1A includes a transistor M1, a terminal 10 to which an AC signal is input, a capacitor C1, and an output terminal 11 and has the following configuration. A gate of the transistor M1 and one of a source and a drain of the transistor M1 are electrically connected to the terminal 10 to which an AC signal is input. The other of the source and the drain of the transistor M1 and a first electrode of the capacitor C1 are electrically connected to the output terminal 11. A ground potential is electrically connected to a second electrode of the capacitor C1.

(42) The rectifier circuit rectifies an AC signal input to the terminal 10 and outputs a DC signal from the terminal 11. This rectifier circuit includes the capacitor C1 and the diode-connected transistor M1 in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region.

(43) Note that in FIGS. 1A and 1B, OS is written beside a circuit symbol that represents a transistor in order to show that the transistor is the one in which an oxide semiconductor is used for a channel formation region.

(44) A rectifier circuit illustrated in FIG. 1B includes a first transistor M3, a second transistor M2, the terminal 10 to which an AC signal is input, a first capacitor C2, a second capacitor C3, and the output terminal 11 and has the following configuration. A first electrode of the capacitor C2 is electrically connected to the terminal 10 to which an AC signal is input. One of a source and a drain of the transistor M3, a gate of the transistor M3, and one of a source and a drain of the transistor M2 are electrically connected to a second electrode of the capacitor C2. The other of the source and the drain of the transistor M3 and a first electrode of the capacitor C3 are electrically connected to the output terminal 11. A ground potential, a gate of the transistor M2, and the other of the source and the drain of the transistor M2 are electrically connected to a second electrode of the capacitor C3.

(45) The rectifier circuit rectifies an AC signal input to the terminal 10 and outputs a DC signal from the terminal 11. This rectifier circuit includes the capacitors C2 and C3 and the diode-connected transistors M2 and M3 in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for channel formation regions.

(46) FIG. 7 is a graph showing a diode characteristic of a diode-connected transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region. This graph shows that even when a reverse-bias voltage of 30 V is applied, a breakdown phenomenon does not occur and the transistor is not broken.

(47) A loss of power P in the rectifier circuit is expressed by Formula 4.
[Formula 4]
P=I.sup.2R.sub.DS(ON)(4)
I: current, R.sub.Ds(ON): on-state resistance of transistor.

(48) According to Formula 4, the higher the on-state resistance (the smaller the on-state current) of the transistor is, the more the loss of power in the rectifier circuit is.

(49) Here, drain current I.sub.DS of the transistor in a saturation region is expressed by Formula 5.

(50) $\begin{matrix} [Formula 5] \\ I_{DS} = \frac{{CW (V_{G} - V_{TH})}^{2}}{2 L} & (5) \end{matrix}$
: mobility, C: capacitance per unit area of gate oxide film, W: channel width, V.sub.G: gate voltage, V.sub.TH: threshold voltage, L: channel length.

(51) According to Formula 5, the following first to third conditions need to be satisfied in order to increase the on-state current of the transistor. The first condition is improvement in the mobility . The second condition is reduction in the channel length L. The third condition is increase in the channel width W.

(52) That is, increase in the channel width W and the on-state current of the transistor can be given as one of way for reducing the loss of power. However, since the value of the channel width W also correlates with the value of the off-state current, there is a limit on the value of the channel width W. As described above, when a transistor whose off-state current is large is used in a rectifier circuit, the possibility of dielectric breakdown due to a breakdown phenomenon or heat generation is increased.

(53) Here, the off-state current at room temperature of the transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for the channel formation region is less than or equal to 10 zA/m when the source-drain voltage is 3.1 V.

(54) It is assumed that the on-state current of the transistor is increased by three orders of magnitude by increasing the channel width W thereof, for example. In this case, the off-state current is also increased by three orders of magnitude; however, the off-state current is still less than or equal to 10.sup.18 A/m. This value is smaller than 10.sup.9 A/m, which is the off-state current of a transistor in which polysilicon is used for a channel formation region, and it can be said that the transistor in which the oxide semiconductor is used for the channel formation region is difficult to be broken.

(55) Accordingly, by providing the transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for the channel formation region in a rectifier circuit, a rectifier circuit in which the loss of power is small, that is, the rectification efficiency is excellent and dielectric breakdown is difficult to occur can be provided.

Embodiment 2

(56) An example of a method for manufacturing a transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region will be described with reference to FIGS. 8A to 8E.

(57) First, an insulating layer 101 is formed as a base film over a substrate 100. The insulating layer 101 is preferably formed while residual moisture is removed from a treatment chamber. This is to prevent hydrogen, water, a hydroxyl group, hydrate, or the like from being included in the insulating layer 101.

(58) Next, an oxide semiconductor layer is formed over the insulating layer 101 by a sputtering method. Before forming the oxide semiconductor layer, the substrate 100 provided with the insulating layer 101 is preferably pre-heated. This is to prevent hydrogen, water, and a hydroxyl group from being included in the oxide semiconductor layer as much as possible. Impurities such as hydrogen or water absorbed in the substrate 100 are removed and exhausted by the preheating.

(59) A metal oxide target including zinc oxide as a main component can be used as a target for the oxide semiconductor layer. For example, a target having a composition ratio of In.sub.2O.sub.3:Ga.sub.2O.sub.3:ZnO=1:1:1, that is, In:Ga:Zn=1:1:0.5 can be used. Other than this, a target having a composition ratio of In:Ga:Zn=1:1:1 or In:Ga:Zn=1:1:2 can be used.

(60) Further, a metal oxide such as InSnGaZnO, InSnZnO, InAlZnO, SnGaZnO, AlGaZnO, SnAlZnO, InZnO, SnZnO, AlZnO, ZnMgO, SnMgO, InMgO, InO, SnO, or ZnO can be used as a target.

(61) Further, a thin film expressed by InMO.sub.3(ZnO).sub.m (m>0 and m is not a natural number) may be used as the oxide semiconductor layer. Here, M is one or more metal elements selected from Ga, Al, Mn, and Co. For example, Ga, Ga and Al, Ga and Mn, or Ga and Co may be used as M.

(62) The formed oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 102 by a first photolithography process (see FIG. 8A). Then, in order to remove hydrogen, water, a hydroxyl group, and the like from the oxide semiconductor layer 102, the substrate is introduced into an electric furnace and heated. This heat treatment has an effect of dehydration or dehydrogenation of the oxide semiconductor layer 102.

(63) A temperature for performing the heat treatment is higher than or equal to 400 C. and lower than or equal to 750 C., preferably higher than or equal to 400 C. and lower than a strain point of the substrate. Further, the heat treatment is performed in an atmosphere that does not include water, hydrogen, or the like.

(64) After the heat treatment, it is preferable that the oxide semiconductor layer 102 be successively heated in an oxygen atmosphere or an atmosphere including nitrogen and oxygen (e.g., the volume ratio of nitrogen:oxygen=4:1). This is to repair oxygen deficiency, which occurs in the oxide semiconductor layer 102.

(65) Then, a first electrode 103a and a second electrode 103b are formed over the insulating layer 101 and the oxide semiconductor layer 102 (see FIG. 8B). The first electrode 103a functions as one of a source electrode and a drain electrode. The second electrode 103b functions as the other of the source electrode and the drain electrode.

(66) Next, a gate insulating layer 104 is formed over the insulating layer 101, the oxide semiconductor layer 102, the first electrode 103a, and the second electrode 103b (see FIG. 8C). Note that it is preferable that hydrogen be not included in an atmosphere in which the gate insulating layer 104 is formed.

(67) Next, openings 105a and 105b reaching the first electrode 103a and the second electrode 103b are formed by removing part of the gate insulating layer 104 (see FIG. 8D).

(68) Then, a gate electrode 106, a first wiring 107a, and a second wiring 107b are formed over the gate insulating layer 104 and the openings 105a and 105b (see FIG. 8E).

(69) In the above manner, the transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region can be manufactured.

Example 1

(70) FIG. 9A shows measurement data of AC voltage input to the half-wave rectifier circuit in FIG. 1A and output DC voltage obtained by rectifying the AC voltage.

(71) As for the size of the transistor M1 in FIG. 1A, W/L is 5000/5 [m]. The capacitance value of the capacitor C1 is 300 pF.

(72) A graph 90 is a graph of input AC voltage. The voltage amplitude is approximately 10 V. A graph 91 is a graph of output DC voltage. In the graph 91, ripples are small and an average value of 3.91 V is obtained.

(73) FIG. 9B shows measurement data of AC voltage input to the half-wave voltage doubler rectifier circuit in FIG. 1B and output DC voltage obtained by rectifying the AC voltage.

(74) As for the size of each of the transistors M2 and M3 in FIG. 1B, W/L is 5000/5 [m]. The capacitance values of the capacitors C2 and C3 are each 300 pF.

(75) A graph 92 is a graph of input AC voltage. The voltage amplitude is approximately 10 V. A graph 93 is a graph of output DC voltage. In the graph 93, ripples are small and an average value of 6.80 V is obtained.

(76) Thus, with a rectifier circuit including a transistor in which an oxide semiconductor that is purified and made electrically i-type (intrinsic) or substantially i-type (intrinsic) is used for a channel formation region, high-quality DC current in which the loss of power is small and ripples are reduced can be obtained. In other words, the rectification efficiency of the rectifier circuit can be improved.

(77) This application is based on Japanese Patent Application serial no. 2010-049159 filed with Japan Patent Office on Mar. 5, 2010, the entire contents of which are hereby incorporated by reference.

Rectifier circuit including transistor whose channel formation region includes oxide semiconductor

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H10D86/60

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H10D86/423

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Abstract

Claims

Description