ETCHED TRENCHES IN BOND MATERIALS FOR DIE SINGULATION, AND ASSOCIATED SYSTEMS AND METHODS

Abstract

Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially encapsulated in a dielectric material.

Claims

1. A method of processing dies, comprising: bonding a die material to a carrier substrate by forming intermetallic compounds between the die material and the carrier substrate, with the intermetallic compounds forming a bond material; forming a plurality of trenches by etching through the bond material that forms a bond between a carrier substrate and a plurality of dies including the die material, wherein individual dies have a first side attached to the bond material and a second side opposite the first side, and wherein individual trenches have lateral side portions and a bottom portion; and singulating the carrier substrate along the trenches to separate the dies.

2. The method of claim 1, further comprising: forming a plurality of mesas in the die material by etching dicing streets through the die material, with individual mesas comprising one or more SSTs.

3. The method of claim 2, wherein an individual SST includes at least one of an OLED, PLED, LED and laser diode.

4. The method of claim 2 wherein the bottom portions of the trenches are at least partially etched into the carrier substrate.

5. The method of claim 1, wherein singulating the carrier substrate is performed by a mechanical sawing process, a laser dicing process, a stealth dicing process, or a combination thereof.

6. The method of claim 1, wherein etching includes a wet etching process with an etchant that includes nitric acid.

7. The method of claim 1, wherein the bond material includes at least one of NiSn, CuSn and TiSi.

8. The method of claim 1, further comprising encapsulating the second sides of the plurality of dies and the side portions of the plurality of trenches with a protective material.

9. The method of claim 8, wherein the protective material comprises a dielectric polymer, a dielectric epoxy, or a combination thereof.

10. The method of claim 1, further comprising: forming openings in the protective material at the second sides of the plurality of dies; and forming electrical contacts in the openings in the protective material.

11. A method of forming SST dies, the method comprising: bonding a die material to a carrier substrate by forming intermetallic compounds between the die material and the carrier substrate, with the intermetallic compounds forming the bond material; forming a plurality of dicing streets between neighboring SST dies to expose a bond material at a second side of the SST dies, wherein the second side is opposite from a first side of the SST dies; etching the exposed bond material to form a plurality of trenches in the carrier substrate, wherein individual trenches have lateral side portions at least partially extending through the bond material and a bottom portion at least partially extending into the carrier substrate; and separating the SST dies by singulating the carrier substrate along the trenches.

12. The method of claim 11, further comprising: removing the growth substrate prior to forming the plurality of dicing streets, and wherein singulating the carrier substrate is performed by a mechanical sawing process.

13. The method of claim 11 wherein the contacts are N-contacts.

14. The method of claim 11, further comprising at least partially encapsulating the first side of the SST dies and the side portions of the trenches with a protective material.

15. The method of claim 14, wherein the protective material comprises a silicone-based material that is generally transparent to a wavelength of radiation configured to be emitted by the SST dies.

16. The method of claim 11, further comprising: forming a plurality of openings in the protective material to partially expose the first side of the SST dies; and forming a plurality of contacts in the openings.

17. A method of singulating SST dies on a substrate, comprising: bonding a carrier substrate and a semiconductor die material by forming intermetallic compounds between the die material and the carrier substrate, with the intermetallic compounds forming a bond material, the die material including a plurality of unsingulated SST dies; forming a plurality of dicing streets between neighboring SST dies by exposing the bond material between neighboring SST dies; etching through the exposed bond material at the dicing streets to form a plurality of trenches in the substrate, wherein individual trenches have lateral side portions at least partially extending through the bond material and a bottom portion at least partially extending into the carrier substrate; and singulating the carrier substrate along the trenches using a mechanical saw.

18. The method of claim 17 wherein the contacts are N-contacts.

19. The method of claim 17, further comprising at least partially encapsulating the SST dies and the side portions of the trenches with a protective material.

20. The method of claim 17, further comprising: forming a plurality of openings in the protective material to partially expose a first side of the SST dies; forming a plurality of contacts at the corresponding openings.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the principles of the present disclosure. Furthermore, in the drawings, like reference numerals designate corresponding parts throughout the several views.

[0012] FIG. 1A is a partially schematic, cross-sectional illustration of an SST device having a growth substrate in accordance with the prior art.

[0013] FIG. 1B is a partially schematic, cross-sectional illustration of an SST device having a carrier in accordance with the prior art.

[0014] FIG. 2A is a partially schematic, cross-sectional illustration of prior art SST wafer subassemblies.

[0015] FIG. 2B is a partially schematic, cross-sectional illustration of a prior art SST wafer after the subassemblies are joined.

[0016] FIG. 2C is a partially schematic, cross-sectional illustration of a prior art SST wafer assembly after the growth substrate is removed.

[0017] FIGS. 3A-3B are partially schematic illustrations of an SST singulation process in accordance with the prior art.

[0018] FIGS. 4A-4G are partially schematic, cross-sectional illustrations of SST wafer singulation processes in accordance with the presently disclosed technology.

[0019] FIG. 5 is a partially schematic, cross-sectional illustration of an SST die in accordance with an embodiment of the presently disclosed technology.

[0020] FIG. 6 is a partially schematic, cross-sectional illustration of an SST die in accordance with another embodiment of the presently disclosed technology.

DETAILED DESCRIPTION

[0021] Specific details of several embodiments of representative SST devices and associated methods of manufacturing SST devices are described below. The term SST generally refers to solid-state transducer devices that include a semiconductor material as an active medium to convert electrical energy into electromagnetic radiation in the visible, ultraviolet, infrared, and/or other spectra. For example, SSTs include solid-state light emitters (e.g., LEDs, laser diodes, etc.) and/or sources of emission other than electrical filaments, plasmas, or gases. LEDs include semiconductor LEDs (light emitting diodes), PLEDs (polymer light emitting diodes), OLEDs (organic light emitting diodes), and/or other types of solid state devices that convert electrical energy into electromagnetic radiation in a desired spectrum. In some embodiments, SSTs can include solid-state devices that convert electromagnetic radiation into electricity. Additionally, depending upon the context in which it is used, the term substrate can refer to a wafer-level substrate or to a singulated device-level substrate. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to FIGS. 4A-6.

[0022] Methods and devices for singulating SST dies from a wafer are disclosed. The disclosed methods and systems enable SST die singulation from a wafer by using a mechanical saw with improved process yields. The SST dies can be manufactured on a wafer having a bond material that connects a carrier substrate to a die material. Because the bond material may have high residual stresses after the wafers are manufactured, the bond material can be selectively removed by, for example, chemical etching thus creating exposed trenches in the carrier substrate. The trenches in the carrier substrate can reduce the incidence of die delamination when the SST dies are singulated from the wafer for at least one of several reasons. For example, the trenches have lower stress levels than the bond material, and are thus less likely to promote crack initiation. Additionally, should the cracks initiate, the presence of the trenches tends to contain the crack propagation within the outline of the trenches in the substrate. Consequently, in at least some embodiments, a mechanical saw can be used along the trenches etched into the carrier substrate to singulate the SST dies from the wafer in a relatively inexpensive yet high-yield process.

[0023] FIGS. 4A-4G illustrate several steps of a representative SST singulation process in accordance with embodiments of the presently disclosed technology. FIG. 4A illustrates a wafer 100 or other suitable substrate that includes a die material 130 bonded to a carrier substrate 121 using a bond material 120. The wafer 100 illustrated in FIG. 4A may be generally similar to the wafer 40 illustrated in FIG. 2C. Accordingly, the wafer 100 can be formed by bonding a growth substrate (carrying the die material 130) to the carrier substrate 121, and then removing the growth substrate. The die material 130 in FIG. 4A has a second semiconductor material 114, an active material 115 and a second semiconductor material 116 exposed for further processing. The carrier substrate 121 can be crystalline silicon or another suitable material. The bond material 120 can be composed of metal or metal alloy layers. For example, the bond material can have a sandwich arrangement with Sn in the middle and Ni above and below the Sn, e.g., Ni in contact with the carrier 120 and the die material 130. In other embodiments, other bond materials including, for example, CuSn and/or TiSi are used. In still further embodiments, other bonding materials known in the art are contemplated. In any of these embodiments, the bond material 120 can be under a high level of stress. The high stress level can be due to residual stresses, e.g., stress remaining after the bonding process and/or stresses induced by a CTE mismatch, e.g., by a mismatch between the coefficient of thermal expansion of the die material 130 and carrier substrate 121.

[0024] The die material 130 in accordance with a particular embodiment includes the first semiconductor material 114, the second semiconductor material 116, and the active region 115 between the first and second semiconductor materials 114, 116. In one embodiment, the first semiconductor material 114 is a P-type gallium nitride (GaN) material, the active region 115 is an indium gallium nitride (InGaN) material, and the second semiconductor material 116 is an N-type GaN material. In different embodiments, the semiconductor constituents of the die material 130 can include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), gallium(III) phosphide (GaP), zinc selenide (ZnSc), boron nitride (BN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum gallium indium nitride (AlGaInN), and/or another suitable semiconductor materials. In any of these embodiments, the combination of the first semiconductor material 114, the second semiconductor material 116 and the active region 115 operate to convert electrical energy to electromagnetic radiation, or vice versa.

[0025] In FIG. 4B, several dicing streets 140 have been formed in the wafer 100 by etching the die material 130. Many suitable etchants including, for example, nitric acid or hydrofluoric acid may be used to form the dicing streets 140 in a photolithographic mask process or another process. The width of and separation between the dicing streets 140 can be selected to produce SST dies 131 having the general shape of a mesa. Once the dicing streets 140 have been formed, the underlying bond material 120 is exposed, and is subjected to further processing as explained below.

[0026] In FIG. 4C, trenches 145 have been formed between neighboring SST dies 131. Selective metal etchants can be used to etch through the bond material 120 and any surrounding materials, e.g., barrier materials, seed materials, and/or adhesion materials (not shown in FIG. 4C). An example of a suitable etchant is a nitric acid wet etchant, which etches metals, but does not etch GaN-based materials. In other embodiments, multiple etchants are applied to the wafer 100 sequentially to remove multiple materials, e.g., materials that may be disposed over or on the carrier substrate 121, and/or may otherwise be positioned between the carrier substrate 121 and the dies 131. The trenches 145 can extend through the bond material 120. In some embodiments, the trenches 145 extend completely through the bond material 120 to at least expose the underlying carrier substrate 121. In further particular embodiments, the trenches 145 can extend partially into the carrier substrate 121, as illustrated in FIG. 4C. The layout of the trenches 145 illustrated in FIG. 4C generally follows the layout of the dicing streets 140 illustrated in FIG. 4B. After partially removing the bond material 120 to form the trenches 145, the dies 131 are supported in position relative to each other by the carrier substrate 121.

[0027] In FIG. 4D, an encapsulant or other suitable protective material 150 has been disposed over the dies 131 and in the trenches 145. The protective material 150 protects the dies 131 and other parts of the wafer 100 from environmental or electro/mechanical damage including, for example, environmental exposure that may cause electrical shorting. In some embodiments, the protective material 150 can be disposed to adhere primarily to the sides and not the bottoms of the trenches 145. In other embodiments, the protective material 150 can be disposed over all interior surfaces of the trenches 145 and then removed from the bottom surfaces. In still further embodiments the protective material 150 can remain at the bottoms of the trenches 145. The protective material 150 can be a dielectric material including, for example, one or more polymers and/or epoxies. The protective material 150 can be disposed using known techniques, for example potting, porosity scaling, liquid filling, or/and conformal coating. In at least some embodiments, the protective material 150 can be a highly transparent silicone-based material, which can be dispensed of injection-molded to dies, or pre-molded and then applied to dies to control whether the bottoms of the trenches 145 are covered.

[0028] Electrical contacts are formed to provide electrical communication with the dies 131. The contacts can include first contacts connected to the first semiconductor material 114 and second contacts connected to the second semiconductor material 116. In FIG. 4E, one or more openings 152 have been made in the protective material 150 to facilitate forming the contacts. The openings 152 are patterned to expose electrical pads (not shown) at the second semiconductor material 116 of the dies 131. Any of a number of suitable techniques may be used to form the openings 152 in the protective material 150 including, for example, photolithography with a positive or a negative mask, followed by etching.

[0029] In FIG. 4F, a pattern of second electrical contacts 155, e.g., N-contacts, has been formed on the dies 131 in contact with second semiconductor material 116 and in the openings 152 of the protective material 150. The second contacts 155 can be formed by, for example, electroless or electrolyte plating techniques, and/or other suitable processes. The second contacts 155 can comprise any of a variety of suitable materials including, for example, Cu, Al, Au and Ag. Corresponding first contacts, e.g., P-contacts (not shown in FIG. 4F) can be formed to connect to the first semiconductor material 114. For example, the first contacts can be formed from or connected to the bond material 120. The bond material 120 can be accessed from the side of the die opposite the second contacts 155, or through-wafer vias can be used to connect to the first semiconductor material 114 from the same side of the die 131 as the second contacts 155.

[0030] FIG. 4G illustrates a process for singulating the dies 131 from the wafer 100. In a particular embodiment, a mechanical saw 70 (shown schematically in FIG. 4G) is used to carry out the singulation process. Because the bond material 120 has been partially removed from the wafer 100 (as described above with respect to FIG. 4C), thus reducing the stress concentrations along trenches 145, the mechanical saw 70 can be used for the singulation process without an undue yield reduction. For example, due to the reduced stress concentration at the trenches 145, the incidence of the dies 131 delaminating from the carrier substrate 121 can be reduced, resulting in higher manufacturing yields.

[0031] Once the dies 131 have been singulated from the wafer or substrate 100, the dies 131 can be further processed before use. Additional processing can include packaging, testing and/or other routine operations associated with manufacturing SST dies.

[0032] One feature of embodiments of the presently disclosed technology discussed above is that they can reduce stress in the bond between a die and a carrier substrate. An advantage of the presently disclosed technology is that it can reduce yield losses due to delamination and/or other stress-induced defects that may result from the die singulation process. This in turn can make certain die singulation processes more economically feasible. For example, mechanical sawing, which can be relatively expensive due to low yield, can become relatively inexpensive when used in combination with the foregoing trench-forming processes. This in turn can reduce costs when compared with laser dicing, while still allowing the robust manufacturing performance associated with thicker carriers. Although the presently disclosed techniques can have particular applicability when used in conjunction with mechanical sawing processes for dicing, such techniques can have applicability to other dicing processes, including laser dicing. Such other processing, in addition to laser dicing, may include a sapphire based scribe and break process, which involves scribing a shallow scribe channel in the trenches between the dies to weaken the wafer along the scribe channels, followed by mechanically breaking the wafer along the scribe channels. Additionally, a two-step stealth dicing process may be used, where during the first step defects in the wafer are created along the trenches by focusing laser light beneath the surface of the trenches. An example of a suitable laser light source is a Nd:YAG laser having a wavelength of 1064 nm and pulsing frequency of about 100 kHz which causes of rapid melting and re-solidification of small volumes of material around the focus point of the laser beam. The defects in the wafer can help to create a preferred crack propagation path. In the second step of the stealth dicing process, the wafer is mechanically broken along the trenches.

[0033] FIG. 5 illustrates an embodiment of a singulated SST device 500 which can be produced by the die singulation process described with reference to FIGS. 4A-4G. The singulated SST device 500 has the die 131 attached with the carrier substrate 121 by the bond material 120. The active material 115 can emit or absorb electromagnetic radiation (in the visible spectrum or outside of it) when proper electrical connection is established through the N-contacts 155 and the associated P-contacts (not shown). Certain elements of known SST packaging techniques, for example, wire leads, reflectors, heat spreaders, etc., are not shown in the simplified representation of the singulated SST 500 of FIG. 5. The carrier substrate 121 can have an indentation 165 formed as a result of etching the bond material 120 and the carrier substrate 121. The protective material 150 can be disposed around the die 131 and bond material 120. In certain embodiments, the sides of the protective material may be generally vertical, thus not entirely filling the trench 145 and the indentation 165. Therefore, after the die singulation process is completed, the indentation 165 can remain in the carrier substrate 121. The indentation 165 is a segment of the trench 145 which is not covered by the protective material layer 150.

[0034] FIG. 6 illustrates another embodiment of a singulated SST device 600 that has been produced by the die singulation process as described with reference to FIGS. 4A-4G. In the embodiment illustrated in FIG. 6, the protective material 150 completely covers the surfaces of the trench 145. Therefore, following the die singulation process as shown in, for example, FIG. 4G, the protective material 150 follows the contour of the indentation 165 at the bottom 145 surface of the trench.

[0035] From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, different materials can be used for SST devices and/or the substrates in further embodiments. Furthermore, different semiconductor processing steps including, for example, several using etchants per processing step can be used. Additionally, the structures of the devices may differ from those shown in the Figures. For example, several dies 131 can be combined into one SST device or/and one package. In at least some embodiments, the above-described die singulation methods and systems are applicable to non-SST die including, for example, a general purpose logic integrated circuit or a memory chip. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein.