Thin-film transistor (TFT), manufacturing method thereof, array substrate and display device
09640553 ยท 2017-05-02
Assignee
Inventors
Cpc classification
H10D99/00
ELECTRICITY
H10D30/673
ELECTRICITY
International classification
H01L21/20
ELECTRICITY
H01L29/786
ELECTRICITY
H01L27/12
ELECTRICITY
Abstract
A thin-film transistor (TFT), a manufacturing method thereof, an array substrate and a display device are disclosed. The method for manufacturing the a TFT comprises the step of forming a gate electrode, a gate insulating layer, an active area, a source electrode and a drain electrode on a base substrate. The active area (4) is made of a ZnON material. When the gate insulating layer is formed, a material for forming the gate insulating layer is subjected to control treatment, so that a sub-threshold amplitude of the TFT is less than or equal to 0.5 mV/dec. The manufacturing method reduces the sub-threshold amplitude of the TFT and improves the semiconductor characteristic of the TFT.
Claims
1. A method for manufacturing a thin-film transistor (TFT), comprising the step of forming a gate electrode, a gate insulating layer, an active area, a source electrode and a drain electrode on a base substrate, wherein the active area is made from a ZnON material; and in the process that the gate insulating layer is formed, a material for forming the gate insulating layer is subjected to control treatment, so that a sub-threshold amplitude of the TFT is less than or equal to 0.5 mV/dec.
2. The manufacturing method according to claim 1, wherein the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and the second gate insulating layer is formed between the first gate insulating layer and the active area.
3. The manufacturing method according to claim 2, wherein a thickness of the first gate insulating layer is ranges from 1,500 to 2,000 ; and a thickness of the second gate insulating layer is ranges from 500 to 1,000 .
4. The manufacturing method according to claim 3, after the step of forming the active area and before the step of forming the source electrode and the drain electrode, further comprising: forming an etch barrier layer; and forming a first via hole and a second via hole in the etch barrier layer respectively corresponding to both ends of the active layer, wherein the source electrode is connected with the active area via the first via hole; and the drain electrode is connected with the active area via the second via hole.
5. The manufacturing method according to claim 2, after the step of forming the active area and before the step of forming the source electrode and the drain electrode, further comprising: forming an etch barrier layer; and forming a first via hole and a second via hole in the etch barrier layer respectively corresponding to both ends of the active layer, wherein the source electrode is connected with the active area via the first via hole; and the drain electrode is connected with the active area via the second via hole.
6. The manufacturing method according to claim 2, wherein the active area is formed over the gate electrode, or the gate electrode is formed over the active area.
7. The manufacturing method according to claim 1, wherein the step of performing control treatment on the material for forming the gate insulating layer when the gate insulating layer is formed includes: introducing gases SiH.sub.4 and NH.sub.3, and forming the gate insulating layer by deposition according to the gas volume flow ratio of SiH.sub.4:NH.sub.31:90.
8. The manufacturing method according to claim 6, wherein the thickness of the gate insulating layer ranges from 2,000 to 4,000 .
9. The manufacturing method according to claim 1, after the step of forming the active area and before the step of forming the source electrode and the drain electrode, further comprising: forming an etch barrier layer; and forming a first via hole and a second via hole in the etch barrier layer respectively corresponding to both ends of the active layer, wherein the source electrode is connected with the active area via the first via hole; and the drain electrode is connected with the active area via the second via hole.
10. The manufacturing method according to claim 1, wherein the active area is formed over the gate electrode, or the gate electrode is formed over the active area.
11. A thin film transistor (TFT) that is manufactured by the manufacturing method according to claim 1.
12. A display device comprising an array substrate comprising the thin film transistor (TFT) according to claim 11.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Simple description will be given below to the accompanying drawings of the embodiments to provide a more clear understanding of the technical proposals of the embodiments of the present invention. Obviously, the drawings described below only involve some embodiments of the present invention but are not intended to limit the present invention.
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REFERENCE NUMERALS
(8) 1. Base Substrate; 2. Gate Electrode; 3. Gate Insulating Layer; 31. First Gate Insulating Layer; 32. Second Gate Insulating Layer; 4. Active Area; 5. Source Electrode; 6. Drain Electrode; 7. Etch Barrier Layer; 8. First Via hole; 9. Second Via hole.
DETAILED DESCRIPTION
(9) For more clear understanding of the technical proposals of the present invention, further detailed description will be given below to the TFT, the manufacturing method thereof, the array substrate and the display device, provided by the present invention, with reference to the accompanying drawings and the preferred embodiments. Obviously, the preferred embodiments are only partial embodiments of the present invention but not all the embodiments. All the other embodiments obtained by those skilled in the art without creative efforts on the basis of the embodiments of the present invention illustrated shall fall within the scope of protection of the present invention.
Embodiment 1
(10) The embodiment provides a method for manufacturing a thin film transistor (TFT); as illustrated in
(11) The sub-threshold amplitude refers to the slope of the curve portion from OFF state to ON state in a semiconductor output characteristic curve. When the slope is smaller, the response speed of the TFT from the OFF state to the ON state is rapider, and correspondingly, the sub-threshold amplitude characteristic is better and the performances of the TFT are better. When the slope is larger, the response speed of the TFT from the OFF state to the ON state is slower, and correspondingly, the sub-threshold amplitude characteristic is poorer and the performances of the TFT are also poorer.
(12) It should be noted that the working state of the TFT refers to that the TFT is at a linear state and a saturation state.
(13) For instance, in the embodiment, the active area 4 is formed over the gate electrode 2, and the gate electrode 2, the gate insulating layer 3, the active area 4, the source electrode 5 and the drain electrode 6 are formed on the base substrate 1 in sequence, namely the TFT in the embodiment adopts a bottom-gate structure. For instance, the gate electrode 2, the active area 4, the source electrode 5 and the drain electrode 6 may be formed by the traditional patterning process. No further description will be given here.
(14) For instance, in the embodiment, the gate insulating layer 3 may include a first insulating layer 31 and a second gate insulating layer 32, and the second insulating layer 32 is formed between the first gate insulating layer 31 and the active area 4. When the gate insulating layer 3 is formed, a material for forming the gate insulating layer 3 is subjected to control treatment. One example of the control treatment method is described below.
(15) Gases SiN.sub.x, N.sub.2 and NH.sub.3 are introduced according to the gas volume flow rate of 140-180 sccm for SiN.sub.x, 1,750-2,250 sccm for N.sub.2 and 700-900 sccm for NH.sub.3 for deposition to form the first gate insulating layer 31; and gases SiN.sub.x, N.sub.2 and NH.sub.3 are introduced according to the gas volume flow rate of 140-180 sccm for SiN.sub.x, 3,500 sccm for N.sub.2 and 1,400 sccm for NH.sub.3 for deposition to form the second gate insulating layer 32. Herein, X is ranged from 1 to 4/3.
(16) For instance, the first gate insulating layer 31 and the second gate insulating layer 32 are formed by a chemical vapor deposition (CVD) method. The method includes: firstly, introducing gases N.sub.2 and NH.sub.3 into a CVD chamber according to the above gas volume flow rates; secondly, introducing gases SiN.sub.x, N.sub.2 and NH.sub.3 according to the above gas volume flow rates under the deposition atmosphere for the deposition of a SiN.sub.x layer; and finally, forming the first gate insulating layer 31 and the second gate insulating layer 32 with different nitrogen contents.
(17) As the second gate insulating layer 32 is tightly attached to the active area 4 and has comparatively higher nitrogen content, when the TFT is in the working state, the nitrogen in the second gate insulating layer 32 can be continuously supplemented to the active area 4 and be at effective conductive positions in the active area 4. The nitrogen at the effective conductive positions can further improve the mobility of NVs in the active area 4, namely further improving the mobility of carriers in the active area 4, so that the sub-threshold amplitude of the TFT can be reduced, and hence the semiconductor characteristic of the TFT can be improved.
(18) It should be noted that the effective conductive position refers to the position of an effective vacancy in the active area 4 made of a ZnON material. When the TFT is electrified, under the action of a gate electric field, the nitrogen at the effective vacancy position can be quickly expelled from the effective vacancy position, so that the effective vacancy position can be retained, and hence the active area 4 can quickly achieve semi-vacancy conductance. Therefore, the TFT can achieve rapid conduction under the electrified condition, namely be quickly developed from OFF state to ON state, and hence not only the sub-threshold amplitude of the TFT can be reduced but also the semiconductor characteristic of the TFT can be improved.
(19) For instance, the thickness of the first gate insulating layer 31 may be ranged from 1,500 A to 2,000 ; and the thickness of the second gate insulating layer 32 may be ranged from 500 to 1,000 . In this way, not only the gate insulating layer 3 between the gate electrode 2 and the active area 4 can have good insulation effect but also the nitrogen in the gate insulating layer 3 can be continuously supplemented to the active area 4 when the TFT is in the working state.
(20) For instance, in the embodiment, after the step of forming the active area 4 and before the step of forming the source electrode 5 and the drain electrode 6, the method may further comprise the step of forming an etch barrier layer 7. A first via hole 8 and a second via hole 9 are respectively formed in the etch barrier layer 7, corresponding to both ends of the active area 4. The source electrode 5 is connected with the active area 4 via the first via hole 8, and the drain electrode 6 is connected with the active area 4 via the second via hole 9. The etch barrier layer 7 can protect the active area 4 from being subjected to etching damage when the source electrode 5 and the drain electrode 6 are formed through etching.
(21) It should be noted that the etch barrier layer may be not formed between the active area 4 and the source electrode 5 and the drain electrode 6 as long as the active area 4 does not suffer from etching damage when the source electrode 5 and the drain electrode 6 are formed through etching.
Embodiment 2
(22) The embodiment provides a method for manufacturing a TFT. As different from the embodiment 1, the step of performing control treatment on the material for forming the gate insulating layer, when the gate insulating layer is formed, includes: introducing SiH.sub.4 and NH.sub.3, and forming the gate insulating layer by deposition according to the gas volume flow ratio of SiH.sub.4:NH.sub.31:90.
(23) For instance, in the embodiment, the thickness of the gate insulating layer may be ranged from 2,000 to 4,000 .
(24) As the traditional gate insulating layer is usually formed by deposition according to the gas volume flow ratio of SiH.sub.4:NH.sub.3=1:30, in the embodiment, the nitrogen content in the gate insulating layer can be greatly improved due to the gas volume flow ratio of SiH.sub.4:NH.sub.3. In this way, when the TFT is in the working state, the nitrogen in the gate insulating layer can be continuously supplemented to the active area and be at effective conductive positions in the active area. The nitrogen at the effective conductive positions greatly improves the mobility of NVs in the active area, namely greatly improving the mobility of carriers in the active area. Therefore, the sub-threshold amplitude of the TFT can be reduced and the semiconductor characteristic of the TFT can be improved.
(25) The manufacturing methods of other structures of the TFT in the embodiment are the same as those in the embodiment 1. No further description will be given here.
Embodiment 3
(26) The embodiment provides a method for manufacturing a TFT. As different from the embodiments 1 and 2, the control treatment on the material for forming the gate insulating layer when the gate insulating layer is formed is, for instance, described below:
(27) firstly, introducing gases SiN.sub.x, N.sub.2 and NH.sub.3 according to the gas volume flow rate of 140-180 sccm for SiN.sub.x, 1,750-2,250 sccm for N.sub.2 and 700-900 sccm for NH.sub.3 for deposition to form the gate insulating layer, in which X is ranged from 1 to 4/3; and secondly, ionizing NH.sub.3 and bombarding produced nitrogen ions to a surface of the gate insulating layer facing the active area.
(28) In general, the number of the nitrogen ions bombarded to the surface of the gate insulating layer can reach more than 10.sup.15/cm.sup.2, so that the nitrogen content in the gate insulating layer can be greatly improved. In this way, when the TFT is in the working state, the nitrogen in the gate insulating layer can be continuously supplemented to the active area and be at effective conductive positions in the active area. Thus, the nitrogen at the effective conductive positions greatly improves the mobility of NVs in the active area, namely greatly improving the mobility of carriers in the active area. Therefore, the sub-threshold amplitude of the TFT can be reduced and the semiconductor characteristic of the TFT can be improved.
(29) The manufacturing methods for other structures of the TFT in the embodiment are the same as those of the embodiment 1 or 2. No further description will be given here.
Embodiment 4
(30) The embodiment provides a method for manufacturing a TFT. As different from the embodiments 1 to 3, the gate electrode is formed over the active area, namely the TFT in the embodiment adopts a top-emission structure.
(31) The manufacturing methods of other structures of the TFT in the embodiment are the same as those of any one of embodiments 1 to 3. No further description will be given here.
(32) In the method for manufacturing the TFT, provided by the embodiments 1 to 4, the nitrogen content in the gate insulating layer is greatly improved by the control treatment on the material for forming the gate insulating layer when the gate insulating layer is formed. In this way, when the TFT is in the working state, the nitrogen in the gate insulating layer can be continuously supplemented to the active area and be at effective conductive positions in the active area. The nitrogen at the effective conductive positions greatly improves the mobility of NVs in the active area, namely greatly improving the mobility of carriers in the active area. Therefore, the sub-threshold amplitude of the TFT can be reduced and the semiconductor characteristic of the TFT can be improved.
Embodiment 5
(33) The embodiment provides a TFT, which is manufactured by the manufacturing method according to any one of embodiments 1 to 4.
(34) The sub-threshold amplitude of the TFT manufactured by the manufacturing method according to any one of embodiments 1 to 4 is less than or equal to 0.5 mV/dec. Compared with the conventional TFT, the sub-threshold amplitude thereof is greatly reduced and the semiconductor characteristic is also greatly improved.
Embodiment 6
(35) The embodiment provides an array substrate, which comprises any foregoing TFT provided by the embodiment 5.
(36) With any foregoing TFT provided by the embodiment 5, the performances of the array substrate can be further improved.
Embodiment 7
(37) The embodiment provides a display device, which comprises any foregoing array substrate provided by the embodiment 6.
(38) With any foregoing array substrate provided by the embodiment 6, the performances of the display device can be further improved.
(39) For instance, the display device provided by the embodiment of the present invention may be any product or component with display function such as a liquid crystal display (LCD) panel, an LCD TV, a display, an organic light-emitting diode (OLED) panel, an OLED TV, a mobile phone, a navigator and a watch.
(40) As the display device provided by the embodiment of the present invention adopts any foregoing array substrate, the performances of the display device can be further improved.
(41) The foregoing is only the preferred embodiments of the present invention and not intended to limit the scope of protection of the present invention. The scope of protection of the present invention should be defined by the appended claims.
(42) The application claims priority to the Chinese patent application No. 201410381849.8, filed Aug. 5, 2014, the disclosure of which is incorporated herein by reference as part of the application.