Method for fabricating semiconductor device

Abstract

A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Claims

1. A method for fabricating a semiconductor device, the method comprising: forming a structure on a substrate, the structure including alternately and repeatedly stacked semiconductor layers and sacrificial layers; forming a first mask on the structure; forming a first side wall of a fin by performing a first etching of the structure using the first mask; forming a second mask different from the first mask on the structure, the first mask being removed from the substrate after partially forming the second mask; and forming a second side wall of the fin by performing a second etching of the structure using the second mask.

2. The method for fabricating a semiconductor device as claimed in claim 1, further comprising removing the sacrificial layers of the structure, after forming the second side wall of the fin, such that a plurality of stacked and spaced apart semiconductor layers remain in the structure.

3. The method for fabricating a semiconductor device as claimed in claim 2, further comprising removing the second mask, after defining the plurality of stacked and spaced apart semiconductor layers.

4. The method for fabricating a semiconductor device as claimed in claim 1, wherein the semiconductor layers include Si, and the sacrificial layers include SiGe.

5. A method for fabricating a semiconductor device, the method comprising: forming a structure on a substrate, such that the structure includes alternately and repeatedly stacked semiconductor layers and sacrificial layers; forming a first mask on the structure; forming a first side wall of a fin by performing a first etching of the structure using the first mask; forming a second mask different from the first mask on the structure, the first mask remaining on the structure during at least partial formation of the second mask forming a second side wall of the fin by performing a second etching of the structure using the second mask; removing the sacrificial layers of the structure, such that a plurality of stacked semiconductor layers remains and is spaced apart from each other in the structure; and removing the second mask.

6. The method for fabricating a semiconductor device as claimed in claim 5, wherein: performing the first etching of the substrate includes forming a trench in the structure and forming the second mask includes forming a first portion that fills the trench and forming a second portion that projects above an upper surface of the structure.

7. The method for fabricating a semiconductor device as claimed in claim 6, wherein forming the second mask includes forming a width of the second portion wider than a width of the first portion.

8. The method for fabricating a semiconductor device as claimed in claim 6, wherein forming the second mask includes forming a side wall of the second portion in a spacer shape, a width of the spacer shape being equal to a width of the fin.

9. The method for fabricating a semiconductor device as claimed in claim 5, wherein the semiconductor layer is made of Si, and the sacrificial layer is made of SiGe.

10. The method for fabricating a semiconductor device as claimed in claim 5, wherein: the first side wall of the fin includes side walls of the alternately and repeatedly stacked semiconductor layers and sacrificial layers, and the second mask is adjacent to the side walls of the alternately and repeatedly stacked semiconductor layers and sacrificial layers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Features will become apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

(2) FIGS. 1 to 20 illustrate stages in a method for fabricating a semiconductor device according to an embodiment.

(3) FIG. 21 illustrates a stage in a method for fabricating a semiconductor device according to another embodiment.

(4) FIGS. 22 to 27 illustrate stages in a method for fabricating a semiconductor device according to still another embodiment.

(5) FIG. 28 illustrates a block diagram of an electronic system including a semiconductor device according to some embodiments.

(6) FIGS. 29 and 30 illustrate exemplary views of a semiconductor system to which a semiconductor device according to some embodiments can be applied.

DETAILED DESCRIPTION

(7) Advantages and features of embodiments and methods of accomplishing the same may be understood more readily by reference to the following detailed description and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and embodiments will only be defined by the appended claims. Thus, in some embodiments, well-known methods, procedures, components, and circuitry have not been described in detail to avoid unnecessarily obscuring aspects.

(8) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

(9) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes and/or comprising, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(10) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(11) Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings.

(12) FIGS. 1 to 20 illustrate views of intermediate steps explaining a method for fabricating a semiconductor device according to an embodiment. FIG. 13 is a cross-sectional view taken along line A-A in FIG. 12, and FIG. 14 is a cross-sectional view taken along line B-B in FIG. 12. FIG. 16 is a cross-sectional view taken along line A-A in FIG. 15, and FIG. 17 is a cross-sectional view taken along line B-B in FIG. 15. FIG. 17 is a cross-sectional view taken along line B-B in FIG. 15. FIG. 19 is a cross-sectional view taken along line A-A in FIG. 18, and FIG. 20 is a cross-sectional view taken along line B-B in FIG. 18.

(13) Referring to FIG. 1, a first mask 502 may be formed on a substrate 100. For example, the substrate 100 may be made of one or more semiconductor materials, e.g., at least one of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Further, the substrate 100 may be an SOI (Silicon On Insulator) substrate. Further, the substrate 100 may be provided by forming an epi-layer on a base substrate. The first mask 502 may be made of, e.g., one or more of an oxide film, a nitride film, an oxynitride film, and a metal film. In an embodiment, it is exemplified that the first mask 502 is a nitride film. The first mask 502 may have a structure in which two or more layers are stacked, but is not limited thereto.

(14) Then, a first side wall 117 of a fin (see F1 in FIG. 4) is formed by performing first etching of the substrate 100 using the first mask 502. That is, a trench 121 may be formed in the substrate 100 by performing the first etching of the substrate 100. The first etching may be anisotropic etching, and for example, dry etching.

(15) Referring to FIGS. 2 and 3, a second mask 512, which is different from the first mask 502, may be formed on the substrate 100. The second mask 512 may be made of a material that is different from that of the first mask 502. The second mask 512 may be made of, e.g., one or more of an oxide film, a nitride film, an oxynitride film, and a metal film. For example, if the first mask 502 is a nitride film, the second mask 512 may be an oxide film.

(16) In detail, referring to FIG. 2, in a state where the first mask 502 is formed on the substrate 100, an insulating material is formed, e.g., deposited, to fill the trench 121, e.g., and to cover the first side wall 117. Then, a first insulating film 511 may be formed through planarization, so that an upper surface of the first mask 502 is exposed. Then, the first mask 502 is removed. For example, if the first mask 502 is a nitride film, it may be removed using phosphoric acid. Then, referring to FIG. 3, a second insulating film 513 of a spacer shape may be formed on a side wall of the first insulating film 511 that projects above an upper surface 100a of the substrate 100 to complete the second mask 512.

(17) As shown herein, the second insulating film 513 has a spacer shape, but is not limited thereto. For example, the second insulating film 513 may include a first portion 512a that fills the trench 121 and a second portion 512b that projects above the upper surface 100a of the substrate 100. The first portion 512a refers to a portion of the first insulating film 511 that fills the trench 121, while the second portion 512b includes a portion of the first insulating film 511, which projects from the first portion 512a upward, and the second insulating film 513 with the spacer shape. A width W2 of the second portion 512b may be wider than a width W1 of the first portion 512a. This is because the second portion 512b includes the second insulating film 513 that is additionally formed, i.e., the second portion 512b extends laterally, e.g., along the X1 direction, beyond the first portion 512a to overlap both the first portion 512a and a part of the upper surface 100a of the substrate 100.

(18) Referring to FIG. 4, a second side wall 118 of the fin F1 is formed by performing second etching of the substrate 100 using the second mask 512. That is, the fin F1 may be completed, while being partially covered by the second mask 512. The fin F1 may be shaped to extend along a second direction Y1 and a third direction Z1.

(19) That is, a trench 122 may be formed in the substrate 100 by performing the second etching of the substrate 100. The second etching may be anisotropic etching, e.g., dry etching.

(20) By adjusting the width of the second insulating film 513, e.g., a width W4 of the second insulating film 513 that covers the upper surface 100a of the substrate 100, the width of the fin F1 along direction X1 may be adjusted. That is, as illustrated, a width W3 of the fin F1 may be equal to the width W4 of the second insulating film 513 of the spacer shape. If the width W4 of the second insulating film 513 is widened, the width W3 of the fin F1 is widened, while, if the width W4 of the second insulating film 513 is narrowed, the width W3 of the fin F1 is narrowed.

(21) Referring to FIG. 5A, the second mask 512 is removed to exposed the first and second side walls 117 and 118 of the fin F1. By way of summary and review of the procedure illustrated in FIGS. 1 to 5A, the first side wall 117 and the second side wall 118 of the fin F1 are formed by separate etching processes. By forming the fin F1 via separate etching processes, i.e., by etching twice as described above, it is possible to implement the fin F1 with a high aspect ratio. If the fin is formed by performing an etching process once, it may be difficult to form a fin with a very narrow width (e.g., a fin having a width of about 20 nm to about 30 nm) due to erosion of a hard mask that is used in the etching process. This is because a hard mask with a very narrow width is rapidly eroded due to a lateral etching effect.

(22) However, in the method for fabricating the semiconductor device according to an embodiment, since the first side wall 117 and the second side wall 118 of the fin F1 are formed through separate etching processes, the first mask 502 and the second mask 512 are sufficiently thick, and thus the first mask 502 and the second mask 512 are not easily eroded. Accordingly, the fin F1 has a very narrow width, e.g., a width of about 20 nm to about 30 nm, by a simplified process.

(23) For example, a first shape of the first side wall 117 and a second shape of the second side wall 118 may be different from each other. This is because the first side wall 117 and the second side wall 118 are formed through different etching processes. For example, a first slope of the first side wall 117 and a second slope of the second side wall 118 may be different from each other.

(24) Further, as illustrated in FIG. 5B, a first bottom surface 100b of the substrate 100 may be connected to the first side wall 117, and a second bottom surface 100c of the substrate 100 may be connected to the second side wall 118. A first height H1 of the first side wall 117, which is measured from the first bottom surface 100b, may be different from a second height 142 of the second side wall 118, which is measured from the second bottom surface 100c.

(25) Further, as illustrated in FIG. 5C, a connection shape 97 between the first bottom surface 100b and the first side wall 117 may be different from a connection shape 98 between the second bottom surface 100c and the second side wall 118. For example, the first bottom surface 100b and the first side wall 117 may be connected at a gentle angle, and the second bottom surface 100c and the second side wall 118 may be connected at a steep angle. However, the connection shapes are not limited thereto.

(26) Next, referring to FIG. 6, an isolation film 100 may be formed to fill the trench 121. The isolation film 110 may be formed of a material that includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

(27) For example, referring to FIG. 7, an upper portion of the fin F1 may be exposed through recessing an upper portion of the isolation film 110. The recessing process may include a selective etching process.

(28) In another example, a part of the fin F1 that projects above the isolation film 110 may be formed by an epi process. In detail, after the isolation film 110 is formed, a part of the fin F1 may be formed through performing the epi process, in which the upper surface of the fin F1 that is exposed by the isolation film 110 is processed as a seed, without the recessing process.

(29) Further, doping for adjustment of a threshold voltage may be performed with respect to the fin F1. If the fin transistor is an NMOS transistor, the impurity may be boron (B). If the fin transistor is a PMOS transistor, the impurity may be phosphorous (P) or arsenic (As).

(30) Referring to FIG. 8, a dummy gate insulating film 141 and a dummy gate electrode 143, which extend in a first direction X1 to cross the fin F1, may be formed by performing an etching process using a mask pattern 2104. For example, the dummy gate insulating film 141 may be a silicon oxide film, and the dummy gate electrode 143 may be made of poly silicon.

(31) Referring to FIG. 9, a first spacer 151 may be formed on a side wall of the dummy gate electrode 143 and on a side wall of the fin F1. For example, after an insulating film is formed on the resultant material, on which the dummy gate electrode 143 is formed, the first spacer 151 may be formed by performing an etch back process. The first spacer 151 may expose an upper surface of the mask pattern 2104 and the upper surface of the fin F1. The first spacer 151 may be a silicon nitride film or a silicon oxynitride film.

(32) Referring to FIG. 10, an interlayer insulating film 155 may be formed on the resultant material, on which the first spacer 151 is formed. The interlayer insulating film 155 may be a silicon oxide film.

(33) Then, the interlayer insulating film 155 may be planarized until the upper surface of the dummy gate electrode 143 is exposed. As a result, the mask pattern 2104 is removed, and the upper surface of the dummy gate electrode 143 is exposed.

(34) Referring to FIG. 11, the dummy gate insulating film 141 and the dummy gate electrode 143 are removed. As the dummy gate insulating film 141 and the dummy gate electrode 143 are removed, a trench 123 that exposes the isolation film 110 is formed.

(35) Referring to FIGS. 12 to 14, a gate insulating film 145 and a gate electrode 147 are formed in the trench 123.

(36) The gate insulating film 145 may include a high-k material having a higher dielectric constant than that of a silicon oxide film. For example, the gate insulating film 145 may include HfO.sub.2, ZrO.sub.2, and/or Ta.sub.2O.sub.5. The gate insulating film 145 may be substantially conformally formed along the side wall and the lower surface of the trench 123.

(37) The gate electrode 147 may include metal layers MG1 and MG2. As illustrated in FIGS. 12-14, the gate electrode 147 may include two or more stacked metal layers MG1 and MG2. The first metal layer MG1 serves to adjust a work function, and the second metal layer MG2 serves to fill a space that is formed by the first metal layer MG1. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, and TaC. For example, the second metal layer MG2 may include W or Al. However, embodiments are not limited to the described above and the gate electrode 147 may be made of Si or SiGe, rather than metal.

(38) Referring to FIGS. 15 to 17, a recess 125 is formed in the fin F1 on both sides of the gate electrode 147.

(39) The recess 125 may be formed in the fin F1 on both sides of the gate electrode 147. A side wall of the recess 125 is inclined, and the recess 125 is shaped to be widened as it goes away from the substrate 100. As illustrated in FIG. 15, the width of the recess 125 along the X1 direction may be wider than the width of the fin F1 along the X1 direction.

(40) Referring to FIGS. 18 to 20, a source/drain 161 is formed in the recess 125. For example, the source/drain 161 may be in the shape of an elevated source/drain. That is, an upper surface of the source/drain 161 may be higher than a lower surface of the interlayer insulating film 155.

(41) For example, if the fin transistor 101 is a PMOS transistor, the source/drain 161 may include a compressive stress material. For example, the compressive stress material may be a material having a large lattice constant in comparison to Si, e.g., the compressive stress material may be SiGe. The compressive stress material may improve mobility of carriers in a channel region by applying compressive stress to the fin F1.

(42) In another example, if the fin transistor 101 is an NMOS transistor, the source/drain 161 may be the same material as the substrate 100 or a tensile stress material. For example, if the substrate 100 is made of Si, the source/drain 161 may be Si, or a material having a smaller lattice constant than that of Si, e.g., e.g., SiC.

(43) Further, the source/drain 161 may be formed by an epi process. Further, depending on whether the fin transistor 101 is a PMOS or NMOS transistor, the material of the source/drain 161 may differ. Further, if needed, impurities may be in-situ doped in the epi process.

(44) FIG. 21 illustrates a view of an intermediate stage explaining a method for fabricating a semiconductor device according to another embodiment. The stages as illustrated in FIGS. 1 to 20 may be the same as those in the method for fabricating a semiconductor device according to the embodiment of FIG. 21. After the stage of FIG. 20, as illustrated in FIG. 21, a stress film 169 may be formed on the fin transistor 102.

(45) The stress film 169 may be, e.g., a SiN film. Whether the SiN film provides a tensile stress or a compressive stress is determined according to a ratio of NH bonding to SiH bonding in the SiN film. For example, if the ratio of NH bonding to SiH bonding is about 1 to 5, the SiN film may provide a tensile stress, whereas, if the ratio of NH bonding to SiH bonding is about 5 to 20, the SiN film may provide a compressive stress. By adjusting the stress using the stress film 169, the amount of current of the fin transistor 102 may be adjusted.

(46) FIGS. 22 to 27 illustrate views of intermediate stages explaining a method for fabricating a semiconductor device according to still another embodiment. Explanation of portions that are substantially the same as the portions explained using FIGS. 1 to 20 will be omitted. The fabricating method of FIGS. 1 to 20 refers to a method for fabricating a fin transistor, while the fabricating method of FIGS. 22 to 27 refers to a method for fabricating a gate all around transistor 103.

(47) Referring to FIG. 22, a structure 113, in which semiconductor layers 112 and sacrificial layers 111 are stacked alternately and repeatedly, may be formed on the substrate 100. The semiconductor layer 112 may be made of Si and the sacrificial layer 111 may be made of SiGe, but are not limited thereto. The number of alternate repetitions of the semiconductor layers 112 and the sacrificial layers 111 may differ depending on the number of nanowires (see 110 in FIG. 26) to be formed thereafter.

(48) Then, a first mask 501 may be formed on the structure 113. The first mask 501 may be made of, e.g., one or more of an oxide film, a nitride film, an oxynitride film, and a metal film. Then, the first side wall 117 of a fin (F2 in FIG. 25) is formed by performing first etching of the structure 113. That is, a trench 121 may be formed in the substrate 100 by performing the first etching of the substrate 100.

(49) Referring to FIGS. 23 and 24, a second mask 512 may be formed on the structure 113. The second mask 512 may be made of a material that is different from that of the first mask 501. For example, if the first mask 501 is a nitride film, the second mask 512 may be an oxide film.

(50) As described above, and as shown in FIG. 23, in a state where the first mask 501 is formed on the substrate 100, an insulating material is formed enough to fill the trench 121. Then, the first insulating film 511 is formed through planarization so that an upper surface of the first mask 501 is exposed. Then, the first mask 501 is removed. For example, if the first mask 501 is a nitride film, it may be removed using phosphoric acid. Then, referring to FIG. 24, the second insulating film 513 of a spacer shape is formed on a side wall of the first insulating film 511 that projects above the upper surface 100a of the substrate 100 to complete the second mask 512. Therefore, the second insulating film 513 is in a spacer shape, but is not limited thereto.

(51) Referring to FIG. 25, the second side wall 118 of the fin F2 is formed by performing second etching of the structure 113. That is, the fin F2 is completed. The fin F2 may be shaped to extend in a second direction Y1 and to project in a third direction Z1.

(52) Referring to FIG. 26, the sacrificial layers 111 of the structure 113 are removed, and a plurality of semiconductor layers 112, which are stacked to be spaced apart from each other, remain. Here, the remaining semiconductor layers 112 correspond to nanowires 119. That is, the semiconductor layers 112 correspond to the channel region of the gate all around transistor.

(53) Here, the sacrificial layers 111 may be removed using chemical dry etching. For example, by combining CF.sub.4 gas, O.sub.2 gas, and N.sub.2 gas and properly adjusting pressure and temperature, the etching rate of the sacrificial layer 111 (i.e., SiGe) to the semiconductor layer 112 (i.e., Si) can be heightened.

(54) Further, when the sacrificial layers 111 are removed, the second mask 512 supports the plurality of remaining semiconductor layers 112 (i.e., nanowires 119). Accordingly, the nanowires 119 in thin long shapes are not damaged during the process. That is, stability of the process of fabricating nanowires 119 can be heightened.

(55) Referring to FIG. 27, the second mask 512 is removed. In FIG. 27, the source/drain 161 that is connected to the nanowires 119 is also illustrated. Then, a gate 147 is formed to cross the nanowires 119. As illustrated, the gate 147 may be formed to surround the nanowires 119.

(56) FIG. 28 illustrates a block diagram of an electronic system including a semiconductor device according to some embodiments.

(57) Referring to FIG. 28, an electronic system 1100 according to an embodiment may include a controller 1110, an input/output (I/O) device 1120, a memory 1130, an interface 1140, and a bus 1150. The controller 1110, the I/O device 1120, the memory 1130, and/or the interface 1140 may be coupled to one another through the bus 1150. The bus 1150 corresponds to paths through which data is transferred.

(58) The controller 1110 may include, e.g., at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements that can perform similar functions. The I/O device 1120 may include, e.g., a keypad, a keyboard, and a display device. The memory 1130 may store data and/or commands. The interface 1140 may function to transfer the data to a communication network or receive the data from the communication network. The interface 1140 may be of a wired or wireless type. For example, the interface 1140 may include an antenna or a wire/wireless transceiver. Although not illustrated, the electronic system 1100 may further include a high-speed DRAM and/or SRAM as an operating memory for improving the operation of the controller 1110. A fin field-effect transistor according to embodiments may be provided inside the memory 1130 or may be provided as a part of the controller 1110 and the I/O device 1120.

(59) The electronic system 1100 may be applied, e.g., to a PDA (Personal Digital Assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or all electronic devices that can transmit and/or receive information in wireless environments.

(60) FIGS. 29 and 30 illustrate exemplary views of a semiconductor system to which the semiconductor device according to some embodiments can be applied. FIG. 29 illustrates a tablet PC, and FIG. 30 illustrates a notebook PC. At least one of the semiconductor devices 101, 102, and 103 according to embodiments may be used in the tablet PC or the notebook PC. It is apparent to those of skilled in the art that the semiconductor device according to some embodiments of the present inventive concept can be applied even to other integrated circuit devices that have not been exemplified.

(61) Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.