Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.

An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

Semiconductor device and fabrication method are provided. The method for forming the semiconductor device includes providing a substrate; forming a dielectric layer on the substrate; forming a through hole in the dielectric layer, the through hole exposing a portion of a top surface of the substrate; performing a surface treatment process on the dielectric layer of sidewalls of the through hole; and filling a metal layer in the through hole.

The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.