Silicon carbide semiconductor device and method for manufacturing same

Abstract

A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300 C. or more and 1500 C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

Claims

1. A silicon carbide semiconductor device comprising: a silicon carbide substrate; an oxide film arranged in contact with said silicon carbide substrate; a gate electrode arranged in contact with said oxide film such that said gate oxide film is interposed between said gate electrode and said silicon carbide substrate; and a first electrode and a second electrode arranged in contact with said silicon carbide substrate, said first electrode and said second electrode being configured such that a current flowing between said first electrode and said second electrode can be controlled by a gate voltage applied to said gate electrode, the difference between a first threshold voltage of said silicon carbide semiconductor device that is measured for the first time and a second threshold voltage of said silicon carbide semiconductor device that is measured after stress has been applied to said silicon carbide semiconductor device continuously for 1000 hours is within 0.2 V, the application of said stress being applying said gate voltage of 45 kHz varying from 5 V to +15 V to said gate electrode, with the voltage of said first electrode being 0 V and the voltage of said second electrode being 0 V, nitrogen atoms or phosphorus atoms being present in an interface region between said gate oxide film and said silicon carbide substrate.

2. The silicon carbide semiconductor device according to claim 1, wherein the difference between said first threshold voltage and a third threshold voltage that is measured after a lapse of any period of time of up to 1000 hours after the start of the application of said stress to said silicon carbide semiconductor device is within 0.2 V.

3. The silicon carbide semiconductor device according to claim 1, wherein said stress is applied at a temperature of 150 C.

4. The silicon carbide semiconductor device according to claim 1, wherein the difference between said first threshold voltage and said second threshold voltage is within 0.2 V when said stress is applied either at room temperature or at a temperature of 150 C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic cross-sectional view showing the structure of a silicon carbide semiconductor device according to one embodiment of the present invention.

(2) FIG. 2 is a schematic diagram for illustrating traps formed at an interface between a silicon carbide semiconductor substrate and a silicon dioxide layer.

(3) FIG. 3 is a schematic diagram for illustrating a state where electrons are captured in the traps.

(4) FIG. 4 shows relation between a gate voltage and a drain current.

(5) FIG. 5 shows relation between a gate voltage and a drain current.

(6) FIG. 6 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention.

(7) FIG. 7 is a schematic cross-sectional view schematically showing a first step of the method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention.

(8) FIG. 8 is a schematic cross-sectional view schematically showing a second step of the method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention.

(9) FIG. 9 is a schematic cross-sectional view schematically showing a third step of the method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention.

(10) FIG. 10 is a schematic diagram showing relation between temperature and time in an annealing step.

(11) FIG. 11 is a schematic diagram showing relation between temperature and time in an annealing step.

(12) FIG. 12 is a schematic diagram showing relation between temperature and time in an annealing step.

(13) FIG. 13 is a schematic cross-sectional view schematically showing the structure of a MOS diode to examine interface state density.

(14) FIG. 14 shows relation between the interface state density and E.sub.c-E.

(15) FIG. 15 shows relation between an amount of variation in threshold voltage and a stress application period.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(16) The embodiments of the present invention will be described hereinafter with reference to the drawings, in which the same or corresponding components are designated by the same reference numerals, and description thereof will not be repeated. Regarding crystallographic descriptions in the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, an individual plane is represented by ( ) and a group plane is represented by { }. In addition, although a negative index is crystallographically indicated by putting (bar) above a numeral, it is indicated by putting a negative sign before the numeral in the present specification. Furthermore, angles are described using a system having an omni-directional angle of 360 degrees.

(17) Referring to FIG. 1, a MOSFET 100 which is a silicon carbide semiconductor device in this embodiment mainly includes a silicon carbide substrate 10, a gate oxide film 91, a gate electrode 93, a source contact electrode 92 (first electrode), and a drain electrode 96 (second electrode).

(18) Silicon carbide substrate 10 is made of hexagonal silicon carbide of polytype 4H, for example. Silicon carbide substrate 10 includes a main surface 3A which is the (0001) plane, for example. Main surface 3A may have an off angle of about 8 relative to the (0001) plane, for example, and may be the (0-33-8) plane. Preferably, main surface 3A macroscopically has an off angle of 6210 relative to the {000-1} plane.

(19) Silicon carbide substrate 10 includes a substrate 1 made of silicon carbide of n conductivity type (first conductivity type), a buffer layer 2 made of silicon carbide of n conductivity type, a drift layer 3 made of silicon carbide of n conductivity type, a pair of p type body regions 4 of p conductivity type (second conductivity type), n.sup.+ regions 5 of n conductivity type, and p.sup.+ regions 6 of p conductivity type.

(20) Buffer layer 2 is formed on one main surface 1A of substrate 1, and is of n conductivity type by containing an n type impurity. Drift layer 3 is formed on buffer layer 2, and is of n conductivity type by containing an n type impurity. The n type impurity contained in drift layer 3 is nitrogen (N), for example, and is contained in a concentration (density) lower than that of the n type impurity contained in buffer layer 2. The nitrogen concentration in drift layer 3 is about 510.sup.15 cm.sup.3, for example. Buffer layer 2 and drift layer 3 constitute an epitaxially grown layer formed on one main surface 1A of substrate 1.

(21) P type body regions 4 of the pair are formed separately from each other in the epitaxially grown layer, and are of p conductivity type by containing a p type impurity (impurity of p conductivity type). The p type impurity contained in p type body regions 4 is aluminum (Al) or boron (B), for example. The aluminum or boron concentration in p type body regions 4 is about 110.sup.17 cm.sup.3, for example.

(22) Each of n.sup.+ regions 5 is formed within each of p type body regions 4 of the pair to include main surface 3A and to be surrounded by p type body region 4. N.sup.+ regions 5 contain an n type impurity, for example, phosphorus (P), in a concentration (density) higher than that of the n type impurity contained in drift layer 3. The phosphorus concentration in n.sup.+ regions 5 is about 110.sup.20 cm.sup.3, for example.

(23) Each of p.sup.+ regions 6 is formed within each of p type body regions 4 of the pair to include main surface 3A, to be surrounded by p type body region 4, and to be adjacent to each of n.sup.+ regions 5. P.sup.+ regions 6 contain a p type impurity, for example, Al, in a concentration (density) higher than that of the p type impurity contained in p type body regions 4. The Al concentration in p.sup.+ regions 6 is about 110.sup.20 cm.sup.3, for example.

(24) Gate oxide film 91 is arranged on and in contact with silicon carbide substrate 10. Gate oxide film 91 is formed on main surface 3A of the epitaxially grown layer to extend from an upper surface of one of n.sup.+ regions 5 to an upper surface of the other n.sup.+ region 5, and is made of silicon dioxide, for example.

(25) Gate electrode 93 is arranged in contact with gate oxide film 91 to extend from the upper surface of one of n.sup.+ regions 5 to the upper surface of the other n.sup.+ region 5. Gate electrode 93 is arranged in contact with gate oxide film 91 such that gate oxide film 91 is interposed between gate electrode 93 and silicon carbide substrate 10. Gate electrode 93 is made of a conductor such as polysilicon or Al doped with an impurity.

(26) Source contact electrode 92 is arranged in contact with n.sup.+ regions 5, p.sup.+ regions 6 and gate oxide film 91. Source contact electrode 92 is made of a material such as NiSi (nickel silicide), which is capable of making ohmic contact with n.sup.+ regions 5.

(27) Drain electrode 96 is formed in contact with a main surface of substrate 1 opposite to the side on which drift layer 3 is formed. Drain electrode 96 is made of a material such as NiSi which is capable of making ohmic contact with n type substrate 1, and is electrically connected to substrate 1.

(28) Source contact electrode 92 (first electrode) and drain electrode 96 (second electrode) are configured such that a current flowing between source contact electrode 92 and drain electrode 96 can be controlled by a gate voltage applied to gate electrode 93.

(29) An interlayer insulating film 94 is formed to be in contact with gate oxide film 91 and to surround gate electrode 93. Interlayer insulating film 94 is made of silicon dioxide which is an insulator, for example.

(30) A source line 95 surrounds interlayer insulating film 94 and extends to an upper surface of source contact electrode 92 on main surface 3A of drift layer 3. Source line 95 is made of a conductor such as Al, and is electrically connected to n.sup.+ regions 5 via source contact electrode 92.

(31) The operation of MOSFET 100 is now described. Referring to FIG. 1, when gate electrode 93 has a voltage lower than a threshold voltage, i.e., in an off state, even if a voltage is applied to drain electrode 96, a pn junction between p type body region 4 and drift layer 3 located immediately below gate oxide film 91 is reverse biased, resulting in a non-conducting state. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to gate electrode 93, an inversion layer is formed in a channel region near a location at which p type body region 4 makes contact with gate oxide film 91. As a result, n.sup.+ regions 5 and drift layer 3 are electrically connected to each other, causing a current to flow between source line 95 and drain electrode 96.

(32) The difference between a first threshold voltage of MOSFET 100 that is measured for the first time for MOSFET 100 according to this embodiment and a second threshold voltage of MOSFET 100 that is measured after stress has been applied to MOSFET 100 continuously for 1000 hours is within 0.2 V. Here, the application of the stress is to apply a gate voltage of 45 kHz varying from 5 V to +15 V to gate electrode 93, with the source voltage of source contact electrode 92 (first electrode) being 0 V and the drain voltage of drain electrode 96 (second electrode) being 0 V. The duty ratio is set to 1:1, for example.

(33) Preferably, the difference between the first threshold voltage and a third threshold voltage that is measured after a lapse of any period of time of up to 1000 hours after the start of the stress application to MOSFET 100 is within 0.2 V.

(34) The stress may be applied to MOSFET 100 at room temperature, for example, or at a temperature of 150 C., for example. Preferably, the difference between the first threshold voltage and the second threshold voltage is within 0.2 V when the stress is applied either at room temperature or at a temperature of 150 C.

(35) Referring now to FIGS. 7 to 12, an example of a method for manufacturing MOSFET 100 in the first embodiment is described.

(36) In the method for manufacturing MOSFET 100 in this embodiment, a silicon carbide substrate preparation step is performed. The silicon carbide substrate preparation step includes a base substrate preparation step (S110: FIG. 6), an epitaxial growth step (S120: FIG. 6), and an ion implantation step (S130: FIG. 6).

(37) Referring first to FIG. 7, in the step (S110: FIG. 6), base substrate 1 made of single-crystal silicon carbide is prepared. Next, in the step (S120: FIG. 6), an epitaxial growth step is performed. In this step (S120), buffer layer 2 and drift layer 3 both made of silicon carbide are successively formed by epitaxial growth on one main surface 1A of base substrate 1.

(38) Next, in the step (S130: FIG. 6), an ion implantation step is performed. In this step (S130), referring to FIG. 8, ion implantation for forming p type body regions 4 is performed first. Specifically, Al (aluminum) ions, for example, are implanted into drift layer 3 to form p type body regions 4. Then, ion implantation for forming n.sup.+ regions 5 is performed. Specifically, P (phosphorus) ions, for example, are implanted into p type body regions 4 to form n.sup.+ regions 5 in p type body regions 4. Then, ion implantation for forming p.sup.+ regions 6 is performed. Specifically, Al ions, for example, are implanted into p type body regions 4 to form p.sup.+ regions 6 in p type body regions 4. These ion implantations can be performed by forming a mask layer, which is made of silicon dioxide and has an opening in a desired region where the ion implantations are to be performed, in the main surface of drift layer 3, for example.

(39) Thus, silicon carbide substrate 10 including base substrate 1 made of silicon carbide of n conductivity type (first conductivity type), buffer layer 2 made of silicon carbide of n conductivity type, drift layer 3 made of silicon carbide of n conductivity type, p type body regions 4 of p conductivity type (second conductivity type), n.sup.+ regions 5 of n conductivity type, and p.sup.+ regions 6 of p conductivity type is prepared. Main surface 3A of silicon carbide substrate 10 is the (0001) plane having an off angle of 8, for example.

(40) Next, in a step (S140: FIG. 6), an activation annealing step is performed. In this step (S140), heat treatment is performed by heating silicon carbide substrate 10 to about 1700 C., for example, in an atmosphere of inert gas such as argon, and holding the substrate for about 30 minutes. Thus, the impurities implanted in the step (S130) are activated.

(41) Next, in a step (S150: FIG. 6), a first heating step is performed. In this step (S150), heat treatment is performed by heating silicon carbide substrate 10 to about 1200 C. or more and about 1300 C. or less, for example, in an atmosphere of oxygen in a concentration of 100%, for example, and holding the substrate for about 60 minutes. Preferably, silicon carbide substrate 10 is heated to about 1300 C. or more and about 1500 C. or less. Thus, gate oxide film 91 made of silicon dioxide is formed on and in contact with silicon carbide substrate 10.

(42) Next, in a step (S160: FIG. 6), a second heating step is performed. In this step (S160), gas containing nitrogen atoms or phosphorus atoms is used as an atmospheric gas. Examples of the gas containing nitrogen atoms include nitrogen monoxide, dinitrogen monoxide, nitrogen dioxide and ammonia. Examples of the gas containing phosphorus atoms include phosphoryl chloride (POCl.sub.3). In this step (S160), silicon carbide substrate 10 is held for one hour, for example, at a temperature of 1300 C. or more and 1500 C. or less in the aforementioned atmospheric gas. By such heat treatment, the nitrogen atoms or phosphorus atoms are captured in traps 8 present in an interface region between gate oxide film 91 and drift layer 3 (see FIGS. 2 and 3). Thus, the formation of an interface state in the interface region between gate oxide film 91 and drift layer 3 is suppressed.

(43) Next, in a step (S170: FIG. 6), a third heating step is performed. In this step (S170), inert gas such as argon or nitrogen (first inert gas) is employed as an atmospheric gas, and heat treatment is performed by heating silicon carbide substrate 10 in this atmospheric gas. In this step (S170), silicon carbide substrate 10 is held for about one hour at a temperature of 1100 C. or more and 1500 C. or less. Preferably, silicon carbide substrate 10 is held at a temperature of 1300 C. or more and 1500 C. or less.

(44) More specifically, the step (S150) to the step (S170) can be performed using temperature profiles such as shown in FIGS. 10 to 12, for example. In FIGS. 10 to 12, the horizontal axis represents a heat treatment period, and the vertical axis represents a heat treatment temperature of silicon carbide substrate 10. In FIGS. 10 to 12, a step between time T1 and time T2 corresponds to the first heating step, a step between time T3 and time T4 corresponds to the second heating step, and a step between time T5 and time T6 corresponds to the third heating step.

(45) Referring to FIG. 10, between time T0 and T1, the temperature of silicon carbide substrate 10 is raised in a nitrogen atmosphere. Silicon carbide substrate 10 is then held at a temperature of less than 1300 C., for example, in an oxygen atmosphere. Subsequently, between time T2 and T3, the temperature of silicon carbide substrate 10 is raised to 1300 C., for example, in an argon gas atmosphere. Preferably, after the first heating step, the oxygen gas is replaced by argon gas (second inert gas) while the temperature of silicon carbide substrate 10 is maintained at a temperature of less than 1300 C., and then silicon carbide substrate 10 is heated to a temperature of 1300 C. or more and 1500 C. or less.

(46) Next, nitrogen monoxide gas is introduced in the furnace, and silicon carbide substrate 10 is heated to a temperature of 1300 C. or more and 1500 C. or less (e.g., about 1350 C.) in a nitrogen monoxide gas atmosphere, and held for a predetermined period of time. Then, the nitrogen monoxide gas in the furnace is replaced by argon gas. Silicon carbide substrate 10 is held at a temperature of 1300 C. or less, for example, in the argon gas atmosphere.

(47) Referring to FIG. 11, in the second heating step (between time T3 and time T4) and the third heating step (between time T5 and time T6), it is preferable to maintain the temperature of silicon carbide substrate 10 at a temperature of about 1300 C. or more and about 1500 C. or less. More preferably, in the second heating step (between time T3 and time T4) and the third heating step (between time T5 and time T6), the temperature of silicon carbide substrate 10 is maintained at a constant temperature of about 1300 C. or more and about 1500 C. or less (e.g., about 1350 C.) for a predetermined period of time. According to this method, there is no need to vary the temperature in the furnace between the second heating step and the third heating step, thereby reducing the total annealing period.

(48) Referring to FIG. 12, in the first heating step (between time T1 and time T2), the second heating step (between time T3 and time T4) and the third heating step (between time T5 and time T6), it is preferable to maintain the temperature of silicon carbide substrate 10 at a temperature of about 1300 C. or more and about 1500 C. or less. More preferably, in the first heating step (between time T1 and time T2), the second heating step (between time T3 and time T4) and the third heating step (between time T5 and time T6), the temperature of silicon carbide substrate 10 is maintained at a constant temperature of about 1300 C. or more and about 1500 C. or less (e.g., about 1350 C.) for a predetermined period of time. According to this method, there is no need to vary the temperature in the furnace between the first heating step and the second heating step and between the second heating step and the third heating step, thereby further reducing the total annealing period.

(49) Next, in a step (S180), an electrode formation step is performed. Referring to FIG. 1, in this step (S180), first, gate electrode 93 made of polysilicon which is a conductor doped with a high concentration of impurity is formed by CVD, photolithography and etching, for example. Then, interlayer insulating film 94 made of silicon dioxide which is an insulator is formed by CVD, for example, to surround gate electrode 93. Then, interlayer insulating film 94 and gate oxide film 91 in a region where source contact electrode 92 is to be formed is removed by photolithography and etching. Then, a nickel (Ni) film formed by evaporation, for example, is heated and silicidized to form source contact electrode 92 and drain electrode 96. Then, source line 95 made of Al which is a conductor is formed on main surface 3A by evaporation, for example, to surround interlayer insulating film 94 and extend to the upper surfaces of n.sup.+ regions 5 and source contact electrode 92. Following the above procedure, MOSFET 100 according to this embodiment is completed.

(50) Although the first conductivity type has been described as n type and the second conductivity type as p type in this embodiment, the present invention is not limited to such form. For example, the first conductivity type may be p type and the second conductivity type may be n type.

(51) In addition, although a vertical MOSFET has been described as an example of the silicon carbide semiconductor device in this embodiment, the present invention is not limited to such form. For example, the silicon carbide semiconductor device may be a lateral MOSFET. Alternatively, the MOSFET may be of planar type or trench type. Still alternatively, the silicon carbide semiconductor device may be an IGBT.

(52) The function and effect in this embodiment are now described.

(53) According to the method for manufacturing MOSFET 100 in this embodiment, after the first heating step, the second heating step of heating silicon carbide substrate 10 to a temperature of 1300 C. or more and 1500 C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed. By heating silicon carbide substrate 10 to 1300 C. or more in the atmosphere of gas containing nitrogen atoms or phosphorus atoms, the density of traps formed at an interface between silicon carbide substrate 10 and gate oxide film 91 can be effectively reduced. Therefore, MOSFET 100 in which threshold voltage variation is small can be obtained. Moreover, since the heating temperature is 1500 C. or less, the softening of silicon carbide substrate 10 can be suppressed.

(54) Moreover, according to the method for manufacturing MOSFET 100 in this embodiment, in the third heating step, silicon carbide substrate 10 is heated to 1300 C. or more and 1500 C. or less. By heating silicon carbide substrate 10 to 1300 C. or more, the redundant gas containing nitrogen atoms or phosphorus atoms that has been introduced in gate oxide film 93 can be efficiently diffused to the outside from gate oxide film 93. As a result, the threshold voltage can be shifted to the positive side, thereby making MOSFET 100 of normally off type. Moreover, since the heating temperature is 1500 C. or less, the softening of silicon carbide substrate 10 can be suppressed.

(55) Furthermore, according to the method for manufacturing MOSFET 100 in this embodiment, in the first heating step, silicon carbide substrate 10 is heated to 1300 C. or more and 1500 C. or less. The trap density can be minimized when the temperature of silicon carbide substrate 10 is 1300 C. or more. In addition, plane orientation anisotropy of oxidation rate of silicon carbide substrate 10 is reduced, thereby reducing the roughness of the silicon dioxide layer. Moreover, since the heating temperature is 1500 C. or less, the softening of silicon carbide substrate 10 can be suppressed.

(56) Furthermore, according to the method for manufacturing MOSFET 100 in this embodiment, the oxygen is replaced by argon after the first heating step and before the second heating step. Thus, the oxygen can be effectively removed, whereby the oxidation of silicon carbide substrate 10 with remaining oxygen can be suppressed.

(57) Furthermore, according to the method for manufacturing MOSFET 100 in this embodiment, the first inert gas is one of argon gas, helium gas and nitrogen gas. Thus, the gas containing nitrogen atoms or phosphorus atoms that has been introduced in gate oxide film 91 in the second step can be effectively diffused to the outside of gate oxide film 91.

(58) Furthermore, according to the method for manufacturing MOSFET 100 in this embodiment, the gas containing nitrogen atoms is one of nitrogen monoxide, dinitrogen monoxide, nitrogen dioxide and ammonia. Thus, the density of traps formed between silicon carbide substrate 10 and gate oxide film 91 can be effectively reduced.

(59) Furthermore, according to the method for manufacturing MOSFET 100 in this embodiment, the gas containing phosphorus atoms is phosphoryl chloride (POCl.sub.3). Thus, the density of traps formed between silicon carbide substrate 10 and gate oxide film 91 can be effectively reduced.

(60) According to MOSFET 100 in this embodiment, the difference between the first threshold voltage of MOSFET 100 that is measured for the first time and the second threshold voltage of MOSFET 100 that is measured after the stress has been applied to MOSFET 100 continuously for 1000 hours is within 0.2 V. Thus, MOSFET 100 in which threshold voltage variation is small can be obtained.

(61) Furthermore, according to MOSFET 100 in this embodiment, the difference between the first threshold voltage and the third threshold voltage that is measured after a lapse of any period of time of up to 1000 hours after the start of the stress application to MOSFET 100 is within 0.2 V. Thus, MOSFET 100 in which threshold voltage variation is small after the lapse of any period of time of up to 1000 hours can be obtained.

(62) Furthermore, according to MOSFET 100 in this embodiment, the stress is applied at a temperature of 150 C. Thus, MOSFET 100 in which threshold voltage variation is small at a high temperature of about 150 C. can be obtained.

(63) Furthermore, according to MOSFET 100 in this embodiment, the difference between the first threshold voltage and the second threshold voltage is within 0.2 V when the stress is applied either at room temperature or at a temperature of 150 C. Thus, MOSFET 100 in which threshold voltage variation is small both at a high temperature of about 150 C. and at room temperature can be obtained.

Example 1

(64) In this example, relation between the interface state density (trap density) and the oxidation temperature of silicon carbide substrate 10 was examined. First, four types of MOS diodes were prepared for the examination of the interface state density. As shown in FIG. 13, each MOS diode included a silicon carbide substrate 13 having the (0-33-8) plane as a main surface, a silicon dioxide layer 12 formed on silicon carbide substrate 13, and a gate electrode 11 formed on silicon dioxide layer 12.

(65) These four types of MOS diodes were subjected to the first heating step, the second heating step and the third heating step in accordance with the method described in the embodiment. For the MOS diodes of Comparative Example 1 and Comparative Example 2, the temperature in the first heating step (oxidation step) was set to 1100 C. and 1200 C., respectively. For the MOS diodes of Present Invention Example 1 and Present Invention Example 2, the temperature in the first heating step (oxidation step) was set to 1300 C. and 1350 C., respectively. The interface state density was measured with the High-Low method described in Japanese Patent Laying-Open No. 2009-158933.

(66) Referring to FIG. 14, the results of the relation between the interface state density and the oxidation temperature is described. In FIG. 14, the vertical axis represents the interface state density, and the horizontal axis represents a value of energy (E.sub.c-E) relative to the conduction band.

(67) As shown in FIG. 14, it was confirmed that the interface state density tends to decrease as E.sub.c-E increases under all oxidation conditions. It was also confirmed that the interface state density tends to decrease as the oxidation temperature (temperature of silicon carbide substrate 10 in the first heating step) increases. In addition, it was confirmed that the interface state density is saturated at an oxidation temperature of about 1300 C., and that the interface state density does not greatly decrease if the oxidation temperature is further increased.

Example 2

(68) In this example, relation between annealing conditions and an amount of variation in threshold voltage was examined. First, a MOSFET according to Comparative Example 3 and a MOSFET according to Present Invention Example 3 were prepared. The MOSFETs according to Comparative Example 3 and Present Invention Example 3 were manufactured in accordance with the method described in the embodiment except for the following points. That is, the (0001) Si plane was employed for main surface 3A of silicon carbide substrate 10. The epitaxial film had a concentration of 7.510.sup.15 cm.sup.3. Gate oxide film 91 had a thickness of 45 nm. Gate electrode 93 was made of polysilicon. P type body regions 4 had an impurity concentration of 510.sup.17 cm.sup.3.

(69) A gate oxidation step, a nitriding step and an argon annealing step in the process of manufacturing the MOSFET of Comparative Example 3 were performed under the following conditions. That is, in the gate oxidation step (first heating step), silicon carbide substrate 10 was held for 60 minutes at a temperature of 1200 C. or more and 1300 C. or less in an atmosphere of 100% oxygen. In the nitriding step (second heating step), silicon carbide substrate 10 was held for 60 minutes at a temperature of 1100 C. or more and 1200 C. or less in an atmosphere of 100% nitrogen monoxide. In the argon annealing step (third heating step), silicon carbide substrate 10 was held for 60 minutes at a temperature of 1100 C. or more and 1200 C. or less in an atmosphere of 100% argon.

(70) A gate oxidation step, a nitriding step and an argon annealing step in the process of manufacturing the MOSFET of Present Invention Example 3 were performed under the following conditions. That is, in the gate oxidation step (first heating step), silicon carbide substrate 10 was held for 60 minutes at a temperature of 1300 C. or more and 1400 C. or less in an atmosphere of 100% oxygen. In the nitriding step (second heating step), silicon carbide substrate 10 was held for 60 minutes at a temperature of 1300 C. or more and 1400 C. or less in an atmosphere of 100% nitrogen monoxide. In the argon annealing step (third heating step), silicon carbide substrate 10 was held for 60 minutes at a temperature of 1300 C. or more and 1400 C. or less in an atmosphere of 100% argon.

(71) Stress was applied to the MOSFETs of Comparative Example 3 and Present Invention Example 3, to measure a stress application period and the amount of variation in threshold voltage. The amount of variation in threshold voltage is a value obtained by subtracting the threshold voltage before the stress application from the threshold voltage after the stress application. As the stress application, a gate voltage of 5 V to +5 V was applied to the gate electrode at a frequency of about 45 kHz, with the source voltage and the drain voltage being set to 0 V. The duty ratio was set to 1:1. The stress application period was set to up to 1000 hours.

(72) Referring to FIG. 15, the relation between the amount of variation in threshold voltage (vertical axis) and the stress application period (horizontal axis) is described. Circle marks represent data in Comparative Example 3, and triangle marks represent data in Present Invention Example 3. Open marks represent data when the stress was applied at room temperature, and filled marks represent data when the stress was applied at 150 C.

(73) As shown in FIG. 15, the amount of variation in threshold voltage of the MOSFET according to Present Invention Example 3 was smaller than the amount of variation in threshold voltage of the MOSFET according to Comparative Example 3. Moreover, in both Present Invention Example 3 and Comparative Example 3, the amount of variation in threshold voltage was smaller when the stress was applied at 150 C. than when the stress was applied at room temperature. Furthermore, it was confirmed that the amount of variation in threshold voltage of the MOSFET according to Present Invention Example 3 was 0.2 V or less when the stress application period was any period of time of 1000 hours or less.

(74) Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.