METHOD AND APPARATUS FOR DELAY-FREE OPERATION OF A CONTROL DEVICE

Abstract

A method for operating a control device, in which in a first operating mode of the control device the first processor core is operated predominantly locally with the first flash memory, and the second processor core is operated predominantly locally with the second flash memory, in a second operating mode of the control device the first processor core and the second processor core are operated with the first flash memory, and in which in a third operating mode of the control device the first processor core and the second processor core are operated with the second flash memory.

Claims

1. A method for operating a control device having a first processor core, a second processor core, a first flash memory, and a second flash memory, the method comprising: operating, in a first operating mode of the control device, the first processor core predominantly locally with the first flash memory, and operating the second processor core predominantly locally with the second flash memory; and operating, in a second operating mode of the control device the first processor core and the second processor core predominantly or exclusively with the first flash memory, so that the second flash memory is reprogrammable in the meanwhile.

2. The method of claim 1, wherein in a third operating mode of the control device the first processor core and the second processor core are operated with the second flash memory.

3. The method of claim 2, wherein as a function of the operating modes, the first processor core and the second processor core are shifted at times into wait states.

4. The method of claim 1, wherein the operating mode is modified when the control device is restarted.

5. The method of claim 4, wherein after starting, an address image of the control device is selectably modified or retained.

6. The method of claim 4, wherein the control device controls an engine of a motor vehicle, and wherein the control device is started with the engine.

7. The method of claim 1, wherein updating is accomplished via an over-the-air interface.

8. A computer readable medium having a computer program, which is executable by a processor, comprising: a program code arrangement having program code for operating a control device having a first processor core, a second processor core, a first flash memory, and a second flash memory, by performing the following: operating, in a first operating mode of the control device, the first processor core predominantly locally with the first flash memory, and operating the second processor core predominantly locally with the second flash memory; and operating, in a second operating mode of the control device the first processor core and the second processor core predominantly or exclusively with the first flash memory, so that the second flash memory is reprogrammable in the meanwhile.

9. The computer readable medium of claim 8, wherein in a third operating mode of the control device the first processor core and the second processor core are operated with the second flash memory.

10. An apparatus for operating a control device having a first processor core, a second processor core, a first flash memory, and a second flash memory, comprising: an operating arrangement configured to perform the following: operating, in a first operating mode of the control device, the first processor core predominantly locally with the first flash memory, and operating the second processor core predominantly locally with the second flash memory; and operating, in a second operating mode of the control device the first processor core and the second processor core predominantly or exclusively with the first flash memory, so that the second flash memory is reprogrammable in the meanwhile.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 schematically shows a control device in a first operating state.

[0011] FIG. 2 shows the control device in a second operating state.

[0012] FIG. 3 shows the control device in a third operating state.

DETAILED DESCRIPTION

[0013] FIG. 1 shows the intended first operating mode 11 of a vehicle control device according to an embodiment of the invention. Control device 21, 22, 31, 32 is equipped in the present case with a first processor core 21, a second processor core 22, a first flash memory 31, and a second flash memory 32. First processor core 21 is operated locally with first flash memory 31, and second processor core 22 is operated locally with second flash memory 32. First flash memory 31 and second flash memory 32 are in the same program state, which corresponds to a predefined memory image.

[0014] As illustrated by FIG. 2, control device 21, 22, 31, 32 is now, with the engine running, shifted into a second operating mode 12 in order to update the second flash memory. In this second operating mode 12, both first processor core 21 and second processor core 22 are operated with first flash memory 31 and with its first memory image 41. Second flash memory 32 can thus be erased during operation of the engine, and second memory image 42 can be reprogrammed via the over-the-air (OTA) interface of the vehicle.

[0015] Lastly, FIG. 3 shows a third operating mode 13 of control device 21, 22, 31, 32. In this state first processor core 21 and second processor core 22 are operated with second flash memory 32. Both first processor core 21 and second processor core 22 therefore work with second memory image 42. In this third operating mode 13, first memory image 41 can therefore be reprogrammed.

[0016] This method 11, 12, 13 can be implemented in control device 21, 22, 31, 32, for example, in software or in hardware or in a mixed form made up of software and hardware.