Abstract
A semiconductor device includes a fin-shaped silicon layer on a silicon substrate, and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, where a pillar diameter of the pillar-shaped silicon layer is equal to a fin width of the fin-shaped silicon layer, and where the pillar diameter and the fin width parallel to the surface. A first diffusion layer is in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer, and a second diffusion layer is in an upper portion of the pillar-shaped silicon layer. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and a contact is on the second diffusion layer.
Claims
1. A semiconductor device comprising: a fin-shaped silicon layer on a surface of a silicon substrate, the fin-shaped silicon layer having a longitudinal axis extending in a first direction parallel to the surface; a first insulating film around the fin-shaped silicon layer; a pillar-shaped silicon layer on the fin-shaped silicon layer, a pillar diameter of the pillar-shaped silicon layer being equal to a fin width of the fin-shaped silicon layer, the pillar diameter and the fin width parallel to the surface; a first diffusion layer in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer; a second diffusion layer in an upper portion of the pillar-shaped silicon layer; a silicide in an upper portion of the first diffusion layer in the upper portion of the fin-shaped silicon layer; a gate insulating film around the pillar-shaped silicon layer; a metal gate electrode around the gate insulating film; a metal gate wiring connected to the metal gate electrode, the metal gate wiring having a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer; and a contact on the second diffusion layer in the upper portion of the pillar-shaped silicon layer so as to make direct contact with the second diffusion layer.
2. The semiconductor device of claim 1, wherein the gate insulating film separates the metal gate electrode from the first diffusion layer in the upper portion of the fin-shaped silicon layer.
3. The semiconductor device of claim 2, wherein the gate insulating film contacts the first insulating film and separates the metal gate wiring from the first insulating film.
4. The semiconductor device of claim 1, wherein an upper surface of the first insulating film is on a same lateral plane with an upper surface of the first diffusion layer in the upper portion of the fin-shaped silicon layer, the lateral plane parallel to the surface.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1(a) is a plan view of a semiconductor device according to the present invention, FIG. 1(b) is a sectional view taken along line X-X in FIG. 1(a), and FIG. 1(c) is a sectional view taken along line Y-Y in FIG. 1(a).
(2) FIG. 2(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 2(b) is a sectional view taken along line X-X in FIG. 2(a), and FIG. 2(c) is a sectional view taken along line Y-Y in FIG. 2(a).
(3) FIG. 3(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 3(b) is a sectional view taken along line X-X in FIG. 3(a), and FIG. 3(c) is a sectional view taken along line Y-Y in FIG. 3(a).
(4) FIG. 4(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 4(b) is a sectional view taken along line X-X in FIG. 4(a), and FIG. 4(c) is a sectional view taken along line Y-Y in FIG. 4(a).
(5) FIG. 5(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 5(b) is a sectional view taken along line X-X in FIG. 5(a), and FIG. 5(c) is a sectional view taken along line Y-Y in FIG. 5(a).
(6) FIG. 6(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 6(b) is a sectional view taken along line X-X in FIG. 6(a), and FIG. 6(c) is a sectional view taken along line Y-Y in FIG. 6(a).
(7) FIG. 7(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 7(b) is a sectional view taken along line X-X in FIG. 7(a), and FIG. 7(c) is a sectional view taken along line Y-Y in FIG. 7(a).
(8) FIG. 8(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 8(b) is a sectional view taken along line X-X in FIG. 8(a), and FIG. 8(c) is a sectional view taken along line Y-Y in FIG. 8(a).
(9) FIG. 9(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 9(b) is a sectional view taken along line X-X in FIG. 9(a), and FIG. 9(c) is a sectional view taken along line Y-Y in FIG. 9(a).
(10) FIG. 10(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 10(b) is a sectional view taken along line X-X in FIG. 10(a), and FIG. 10(c) is a sectional view taken along line Y-Y in FIG. 10(a).
(11) FIG. 11(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 11(b) is a sectional view taken along line X-X in FIG. 11(a), and FIG. 11(c) is a sectional view taken along line Y-Y in FIG. 11(a).
(12) FIG. 12(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 12(b) is a sectional view taken along line X-X in FIG. 12(a), and FIG. 12(c) is a sectional view taken along line Y-Y in FIG. 12(a).
(13) FIG. 13(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 13(b) is a sectional view taken along line X-X in FIG. 13(a), and FIG. 13(c) is a sectional view taken along line Y-Y in FIG. 13(a).
(14) FIG. 14(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 14(b) is a sectional view taken along line X-X in FIG. 14(a), and FIG. 14(c) is a sectional view taken along line Y-Y in FIG. 14(a).
(15) FIG. 15(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 15(b) is a sectional view taken along line X-X in FIG. 15(a), and FIG. 15(c) is a sectional view taken along line Y-Y in FIG. 15(a).
(16) FIG. 16(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 16(b) is a sectional view taken along line X-X in FIG. 16(a), and FIG. 16(c) is a sectional view taken along line Y-Y in FIG. 16(a).
(17) FIG. 17(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 17(b) is a sectional view taken along line X-X in FIG. 17(a), and FIG. 17(c) is a sectional view taken along line Y-Y in FIG. 17(a).
(18) FIG. 18(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 18(b) is a sectional view taken along line X-X in FIG. 18(a), and FIG. 18(c) is a sectional view taken along line Y-Y in FIG. 18(a).
(19) FIG. 19(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 19(b) is a sectional view taken along line X-X in FIG. 19(a), and FIG. 19(c) is a sectional view taken along line Y-Y in FIG. 19(a).
(20) FIG. 20(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 20(b) is a sectional view taken along line X-X in FIG. 20(a), and FIG. 20(c) is a sectional view taken along line Y-Y in FIG. 20(a).
(21) FIG. 21(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 21(b) is a sectional view taken along line X-X in FIG. 21(a), and FIG. 21(c) is a sectional view taken along line Y-Y in FIG. 21(a).
(22) FIG. 22(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 22(b) is a sectional view taken along line X-X in FIG. 22(a), and FIG. 22(c) is a sectional view taken along line Y-Y in FIG. 22(a).
(23) FIG. 23(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 23(b) is a sectional view taken along line X-X in FIG. 23(a), and FIG. 23(c) is a sectional view taken along line Y-Y in FIG. 23(a).
(24) FIG. 24(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 24(b) is a sectional view taken along line X-X in FIG. 24(a), and FIG. 24(c) is a sectional view taken along line Y-Y in FIG. 24(a).
(25) FIG. 25(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 25(b) is a sectional view taken along line X-X in FIG. 25(a), and FIG. 25(c) is a sectional view taken along line Y-Y in FIG. 25(a).
(26) FIG. 26(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 26(b) is a sectional view taken along line X-X in FIG. 26(a), and FIG. 26(c) is a sectional view taken along line Y-Y in FIG. 26(a).
(27) FIG. 27(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 27(b) is a sectional view taken along line X-X in FIG. 27(a), and FIG. 27(c) is a sectional view taken along line Y-Y in FIG. 27(a).
(28) FIG. 28(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 28(b) is a sectional view taken along line X-X in FIG. 28(a), and FIG. 28(c) is a sectional view taken along line Y-Y in FIG. 28(a).
(29) FIG. 29(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 29(b) is a sectional view taken along line X-X in FIG. 29(a), and FIG. 29(c) is a sectional view taken along line Y-Y in FIG. 29(a).
(30) FIG. 30(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 30(b) is a sectional view taken along line X-X in FIG. 30(a), and FIG. 30(c) is a sectional view taken along line Y-Y in FIG. 30(a).
(31) FIG. 31(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 31(b) is a sectional view taken along line X-X in FIG. 31(a), and FIG. 31(c) is a sectional view taken along line Y-Y in FIG. 31(a).
(32) FIG. 32(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 32(b) is a sectional view taken along line X-X in FIG. 32(a), and FIG. 32(c) is a sectional view taken along line Y-Y in FIG. 32(a).
(33) FIG. 33(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 33(b) is a sectional view taken along line X-X in FIG. 33(a), and FIG. 33(c) is a sectional view taken along line Y-Y in FIG. 33(a).
(34) FIG. 34(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 34(b) is a sectional view taken along line X-X in FIG. 34(a), and FIG. 34(c) is a sectional view taken along line Y-Y in FIG. 34(a).
(35) FIG. 35(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 35(b) is a sectional view taken along line X-X in FIG. 35(a), and FIG. 35(c) is a sectional view taken along line Y-Y in FIG. 35(a).
(36) FIG. 36(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 36(b) is a sectional view taken along line X-X in FIG. 36(a), and FIG. 36(c) is a sectional view taken along line Y-Y in FIG. 36(a).
(37) FIG. 37(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 37(b) is a sectional view taken along line X-X in FIG. 37(a), and FIG. 37(c) is a sectional view taken along line Y-Y in FIG. 37(a).
(38) FIG. 38(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 38(b) is a sectional view taken along line X-X in FIG. 38(a), and FIG. 38(c) is a sectional view taken along line Y-Y in FIG. 38(a).
(39) FIG. 39(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 39(b) is a sectional view taken along line X-X in FIG. 39(a), and FIG. 39(c) is a sectional view taken along line Y-Y in FIG. 39(a).
(40) FIG. 40(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 40(b) is a sectional view taken along line X-X in FIG. 40(a), and FIG. 40(c) is a sectional view taken along line Y-Y in FIG. 40(a).
(41) FIG. 41(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 41(b) is a sectional view taken along line X-X in FIG. 41(a), and FIG. 41(c) is a sectional view taken along line Y-Y in FIG. 41(a).
(42) FIG. 42(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 42(b) is a sectional view taken along line X-X in FIG. 42(a), and FIG. 42(c) is a sectional view taken along line Y-Y in FIG. 42(a).
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(43) A manufacturing process for forming a SGT structure according to an embodiment of the present invention is described below with reference to FIGS. 2 to 42.
(44) First, a manufacturing method for forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer is described. As shown in FIG. 2, a first resist 102 is formed for forming a fin-shaped silicon layer on a silicon substrate 101.
(45) As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-shaped silicon layer 103. Although, in this case, the fin-shaped silicon layer is formed using the resist as a mask, a hard mask such as an oxide film or a nitride film may be used.
(46) As shown in FIG. 4, the first resist 102 is removed.
(47) As shown in FIG. 5, a first insulating film 104 is deposited around the fin-shaped silicon layer 103. As the first insulating film, an oxide film formed by high-density plasma, or an oxide film formed by low-pressure chemical vapor deposition may be used.
(48) As shown in FIG. 6, the first insulating film 104 is etched back to expose an upper portion of the fin-shaped silicon layer 103. The steps up to this step are the same as in the method for forming a fin-shaped silicon layer of Japanese Unexamined Patent Application Publication No. 2-188966.
(49) As shown in FIG. 7, a second resist 105 is formed so as to be perpendicular to the fin-shaped silicon layer 103. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes a pillar-shaped silicon layer. Since a linear resist can be used, the resist is unlikely to fall after patterning, thereby realizing a stable process.
(50) As shown in FIG. 8, the fin-shaped silicon layer 103 is etched. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes the pillar-shaped silicon layer 106. Therefore, the width of the pillar-shaped silicon layer 106 is equal to the width of the fin-shaped silicon layer. As a result, a structure is formed, in which the pillar-shaped silicon layer 106 is formed in an upper portion of the fin-shaped silicon layer 103, and the first insulating film 104 is formed around the fin-shaped silicon layer 103.
(51) As shown in FIG. 9, the second resist 105 is removed.
(52) Next, a description is given of a manufacturing method for forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer in order to use a gate-last process. As shown in FIG. 10, a second oxide film 107 is deposited, and a first nitride film 108 is formed. Since an upper portion of the pillar-shaped silicon layer is subsequently covered with a gate insulating film and a polysilicon gate electrode, a diffusion layer is formed in an upper portion of the pillar-shaped silicon layer before covering of the pillar-shaped silicon layer.
(53) As shown in FIG. 11, the first nitride film 108 is etched to be left as a wide wall.
(54) As shown in FIG. 12, impurities such as arsenic, phosphorus, or boron are implanted to form a diffusion layer 110 in an upper portion of the pillar-shaped silicon layer, and diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103.
(55) As shown in FIG. 13, the first nitride film 108 and the second oxide film 107 are removed.
(56) As shown in FIG. 14, heat treatment is performed. The diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103 are brought into contact with each other to form a diffusion layer 112. As described above, in order to use the gate-last process, the diffusion layers 110 and 112 are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer.
(57) Next, a description is given of a manufacturing method for forming a polysilicon gate electrode and a polysilicon gate wiring using polysilicon in order to use the gate-last process. In order to use the gate-last process, an interlayer insulating film is deposited, and then the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent an upper portion of the pillar-shaped silicon layer from being exposed by chemical mechanical polishing.
(58) As shown in FIG. 15, a gate insulating film 113 is formed, and polysilicon 114 is deposited and then planarized. After planarization, the upper surface of the polysilicon is higher than the gate insulating film 113 disposed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. As a result, when in order to use the gate-last process, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after the interlayer insulating film is deposited, the upper portion of the pillar-shaped silicon layer is not exposed by chemical mechanical polishing.
(59) In addition, a second nitride film 115 is deposited. The second nitride film is one which inhibits the formation of silicide in upper portions of the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed in an upper portion of the fin-shaped silicon layer.
(60) As shown in FIG. 16, a third resist 116 is formed for forming the polysilicon gate electrode and the polysilicon gate wiring. A portion corresponding to gate wiring is preferably perpendicular to the fin-shaped silicon layer 103. This is because a parasitic capacitance between the gate wiring and the substrate is decreased.
(61) As shown in FIG. 17, the second nitride film 115 is etched.
(62) As shown in FIG. 18, the polysilicon 114 is etched to form a polysilicon gate electrode 114a and a polysilicon gate wiring 114b.
(63) As shown in FIG. 19, the gate insulating film 113 is etched.
(64) As shown in FIG. 20, the third resist 116 is removed.
(65) The manufacturing method for forming the polysilicon gate electrode and the polysilicon gate wiring using polysilicon in order to use the gate-last process is described above. After the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are formed, the upper surface of polysilicon is higher than the gate insulating film 113 on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106.
(66) Next, a manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described. The silicide is not formed in upper portions of the polysilicon gate electrode 114a and the polysilicon gate wiring 114b and in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. When the silicide is formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, the manufacturing process is enlarged.
(67) As shown in FIG. 21, a third nitride film 117 is deposited.
(68) As shown in FIG. 22, the third nitride film 117 is etched to be left as a side wall.
(69) As shown in FIG. 23, a metal such as nickel or cobalt is deposited to form silicide 118 in an upper portion of the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103. At this time, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are covered with the third nitride film 117 and the second nitride film 115, and the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 is covered with the gate insulating film 113, the polysilicon gate electrode 114a, and the polysilicon gate wiring 114b, and thus silicide is not formed in the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the diffusion layer 110.
(70) The manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described above.
(71) Next, a gate-last manufacturing method is described, in which the polysilicon gate electrode and the polysilicon wiring are exposed by chemical mechanical polishing after an interlayer insulting film is deposited, the polysilicon gate electrode and the polysilicon wiring are etched, and then a metal is deposited.
(72) As shown in FIG. 24, a fourth nitride film 140 is deposited for protecting the silicide 118.
(73) As shown in FIG. 25, an interlayer insulating film 119 is deposited and then planarized by chemical mechanical polishing.
(74) As shown in FIG. 26, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are exposed by chemical mechanical polishing.
(75) As shown in FIG. 27, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are etched. Wet etching is preferred.
(76) As shown in FIG. 28, a metal 120 is deposited and then planarized to fill, with the metal 120, a portion from which the polysilicon gate electrode 114a and the polysilicon gate wiring 114b have been removed. Atomic layer deposition is preferably used.
(77) As shown in FIG. 29, the metal 120 is etched to expose the gate insulating film 113 formed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. Consequently, a metal gate electrode 120a and a metal gate wiring 120b are formed. The gate-last manufacturing method is described above, in which after the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and then a metal is deposited.
(78) Next, a manufacturing method for forming a contact is described. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, a contact is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. As shown in FIG. 30, an interlayer insulating film 121 is deposited and then planarized.
(79) As shown in FIG. 31, a fourth resist 122 is formed for forming a contact hole on the pillar-shaped silicon layer 106.
(80) As shown in FIG. 32, the interlayer insulating film 121 is etched to form a contact hole 123.
(81) As shown in FIG. 33, the fourth resist 122 is removed.
(82) As shown in FIG. 34, a fifth resist 124 is formed for forming contact holes on the metal gate wiring 120b and on the fin-shaped silicon layer 103.
(83) As shown in FIG. 35, the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126.
(84) As shown in FIG. 36, the fifth resist 124 is removed.
(85) As shown in FIG. 37, the nitride film 140 and the gate insulating film 113 is etched to expose the silicide 118 and the diffusion layer 110.
(86) As shown in FIG. 38, a metal is deposited to form contacts 143, 127, and 128. The manufacturing method for forming contacts is described above. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, the contact 127 is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106.
(87) Next, a manufacturing method for forming a metal wiring layer is described.
(88) As shown in FIG. 39, a metal 129 is deposited.
(89) As shown in FIG. 40, sixth resists 130, 131, and 132 are formed for forming the metal wiring.
(90) As shown in FIG. 41, the metal 129 is etched to metal wirings 133, 134, and 135.
(91) As shown in FIG. 42, the sixth resists 130, 131, and 132 are removed.
(92) The manufacturing method for forming metal wiring layers is described above.
(93) The result of the above-described manufacturing method is shown in FIG. 1.
(94) The resulting structure includes: the fin-shaped silicon layer 103 formed on the substrate 101; the first insulating film 104 formed around the fin-shaped silicon layer 103; the pillar-shaped silicon layer 106 formed on the fin-shaped silicon layer 103, the width of the pillar-shaped silicon layer 106 being equal to the width of the fin-shaped silicon layer 103; the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103 and a lower portion of the pillar-shaped silicon layer 106; the diffusion layer 110 formed in an upper portion of the pillar-shaped silicon layer 106; the silicide 118 formed in an upper portion of the diffusion layer 112 in an upper portion of the fin-shaped silicon layer 103; the gate insulating film 113 formed around the pillar-shaped silicon layer 106; the metal gate electrode 120a formed around the gate insulating film; the metal gate wiring 120b connected to the metal gate electrode 120a and extending in a direction perpendicular to the fin-shaped silicon layer 103; and the contact 127 formed on the diffusion layer 110, the diffusion layer 110 and the contact 127 being in direct contact with each other.
(95) As described above, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate and provide a SGT manufacturing method using a gate-last process and a resulting SGT structure.
