Dielectric ceramic composition and electronic device using the same

Abstract

A dielectric ceramic composition includes a main component comprising (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3, where 0.005x0.5 and 0.3y1.0; a first subcomponent comprising an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn; and a second subcomponent comprising SiO.sub.2.

Claims

1. A dielectric ceramic composition comprising: a main component comprising (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3, where 0.03x0.5 and 0.3y0.7; a first subcomponent comprising an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn; and a second subcomponent comprising SiO.sub.2.

2. The dielectric ceramic composition of claim 1, wherein the first subcomponent is an oxide or a carbonate of an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn.

3. The dielectric ceramic composition of claim 1, wherein the first subcomponent is MnO.sub.2 or MnCO.sub.3.

4. The dielectric ceramic composition of claim 1, wherein the content of the first subcomponent in the dielectric ceramic composition is 0.1-5.0 atomic percent.

5. The dielectric ceramic composition of claim 1, wherein the content of SiO.sub.2 in the second subcomponent is 0.1-5.0 atomic percent.

6. An electrical device comprising the dielectric ceramic composition of claim 1.

7. The electrical device of claim 6, wherein the electrical device is one selected from the group consisting of a multi-layered ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor, and a positive temperature coefficient resistor (PTCR).

8. A dielectric ceramic composition comprising (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3, where 0.03x0.5 and 0.3y0.7, having a room temperature permittivity of 1500 or more, a temperature coefficient of capacitance at 150 C. between 15% and +15%, and a withstand voltage at 150 C. of 50 V/m or more.

9. The dielectric ceramic composition of claim 8, wherein the room temperature permittivity is 2000 or more.

10. The dielectric ceramic composition of claim 8, wherein the temperature coefficient of capacitance at 150 C. is between 10% and +10%.

11. The dielectric ceramic composition of claim 8, wherein the withstand voltage at 150 C. is 60 V/m or more.

12. An electrical device comprising the dielectric ceramic composition of claim 2.

13. The electrical device of claim 12, wherein the electrical device is one selected from the group consisting of a multi-layered ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor, and a positive temperature coefficient resistor (PTCR).

14. An electrical device comprising the dielectric ceramic composition of claim 3.

15. The electrical device of claim 14, wherein the electrical device is one selected from the group consisting of a multi-layered ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor, and a positive temperature coefficient resistor (PTCR).

16. An electrical device comprising the dielectric ceramic composition of claim 4.

17. The electrical device of claim 16, wherein the electrical device is one selected from the group consisting of a multi-layered ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor, and a positive temperature coefficient resistor (PTCR).

18. An electrical device comprising the dielectric ceramic composition of claim 5.

19. The electrical device of claim 18, wherein the electrical device is one selected from the group consisting of a multi-layered ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor, and a positive temperature coefficient resistor (PTCR).

Description

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

(1) Hereinafter, the present inventive concept will be explained in more detail.

(2) The present disclosure relates to a dielectric ceramic composition which provides thermal properties up to 150 C. and satisfies X8R properties for reliability.

(3) BaTiO.sub.3 may form the main component of high capacitance Ni-MLCC (multi-layer ceramic capacitor) having a Curie temperature (T.sub.C) of about 125 C. The permittivity of BaTiO.sub.3 drops sharply above this temperature. Thus, there is a demand for developing a composition having thermal properties up to 150 C. to be within 15% of the X8R standard.

(4) For example, it has been reported in JP Patent Publication Nos. 2002-255639 and 2005-263508 that addition of an excess amount of rare-earth elements to BaTiO.sub.3 alleviates the extent of the decrease of the permittivity at temperatures higher than the Curie temperature, or appropriate amounts of CaZrO.sub.3 to BaTiO.sub.3 may be added to increase the Curie temperature so that the temperature coefficient of capacitance (TCC) at a high temperature can be improved. However, Yoon et al., J. Mater. Res., 22[9]2539 (2007) discloses that when an excess amount of rare-earth elements is used, a second phase of pyrochlore is generated to deteriorate the reliability. Furthermore, when an excess amount of rare-earth elements is added or CaZrO.sub.3 is added to BaTiO.sub.3, which has a Curie temperature of 125 C., it may satisfy X8R properties but may not be enough to obtain TCC properties at a high temperature.

(5) Alternatively, powder having a high Curie temperature may be used to improve TCC properties at a high temperature. When Ca is used as the A-cation of the ABO.sub.3 Perovskite structure, the Curie temperature increases and the Ca-added BaTiO.sub.3 (BCT) powder increases the TCC properties at a high temperature. Thus, this material may be used as an X8R material, as has been reported in Yoon et al., J. Mater. Res., 25[11]2135 (2010). When BaTiO.sub.3 is prepared by calcination in the air using the solid state method, Pb has also been known to increase the Curie temperature in addition to Ca. However, Pb is a noxious material, and it may volatilize easily during the sintering process under the reduced atmosphere like that used to prepare a Ni-multi-layered ceramic capacitor.

(6) Accordingly, the present disclosure provides a dielectric ceramic composition which is able to exhibit the permittivity of 1500 or above and excellent insulation resistance and X8R thermal properties after being prepared as a sintered compound through mixing BaTiO.sub.3 and (Na, K)NbO.sub.3 in an appropriate ratio or forming a solid solution thereof, adding a small amount of SiO.sub.2 and MnO.sub.2 and sintering the mixture. Thus, even though CaZrO.sub.3 or an excess amount of rare-earth elements is not added, it provides X8R properties and better TCC properties at a high temperature, compared to the conventional BaTiO.sub.3.

(7) According to an aspect of the present inventive concept, a dielectric ceramic composition comprises a main component of (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3(0.005x0.5, 0.3y1.0) which is a solid solution of a first main component BaTiO.sub.3 and a second main component (Na.sub.1-yK.sub.y)NbO.sub.3, a first subcomponent comprising an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn, and a second subcomponent comprising SiO.sub.2 or a glass-forming material comprising SiO.sub.2.

(8) The range of x and y is based on the composition and experimental results in Table 1 and Table 2 according to examples of the present inventive concept.

(9) The dielectric ceramic composition comprises a main component prepared by mixing a first main component BaTiO.sub.3 and a second main component (Na, K)NbO.sub.3, and additives comprising an oxide or a carbonate of a variable-valence acceptor as a first subcomponent and SiO.sub.2 as a second subcomponent. The prepared main component may be powder with a particle size of 1.0 m or less.

(10) In an embodiment, the first subcomponent may be an oxide or a carbonate of an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn. In certain embodiments, the first subcomponent may be MnO.sub.2 or MnCO.sub.3.

(11) In an embodiment, the content of the first subcomponent in the dielectric ceramic composition may be 0.1-5.0 at %.

(12) In an embodiment, the content of SiO.sub.2 in the second subcomponent may be 0.1-5.0 at %.

(13) Exemplary ranges of each component are shown in the results in Table 1 and Table 2.

(14) According to another aspect of the present inventive concept, an electrical device comprises a dielectric material prepared by using the dielectric ceramic composition.

(15) In certain embodiments, the electrical device may be at least one selected from the group consisting of a multi-layered ceramic capacitor, a piezoelectric element, a chip inductor, a chip varistor, a chip resistor and a positive temperature coefficient resistor (PTCR).

(16) In particular, the dielectric ceramic composition of the present inventive concept may be used for multilayer dielectric material products and internal electrode layers, for example, products in which Ni internal electrode layers and dielectric material layers are alternatively laminated. Since the dielectric material layer having a very thin thickness adversely affects the reliability due to lower numbers of crystal grains existing within the layer, the thickness of a dielectric material layer may be 0.1 m or above after sintering.

EXAMPLES

(17) A mixed solid solution powder of (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3, which forms the main powder, was prepared using the solid state method. Starting materials were BaCO.sub.3, TiO.sub.2, Na.sub.2O, K.sub.2O, and Nb.sub.2O.sub.5. BaCO.sub.3 and TiO.sub.2 were mixed with a ball mill and calcinated at 900-1000 C. to provide BaTiO.sub.3 powder having an average particle size of 300 nm. Similarly, Na.sub.2O, K.sub.2O, and Nb.sub.2O.sub.5 were mixed with a ball mill and calcinated at 800-900 C. to provide (Na.sub.0.5K.sub.0.5)NbO.sub.3 powder having an average particle size of 300 nm. All main components in the composition shown in Table 1 were dispersed and mixed in ethanol. The mixture was calcined at 950-1050 C. in the air to provide a main powder having an average particle size of 300 nm. Subcomponents MnO.sub.2 and SiO.sub.2 powder in the composition shown in Table 1 were added to the main powder. The main powder including main components and subcomponents was mixed and dispersed with a zirconia ball in ethanol/toluene and then a dispersing agent and a binder were added thereto and the mixture was ball-milled for 2 hours. The prepared slurry was used to prepare a molded sheet using a doctor blade type coater.

(18) A Ni internal electrode was printed on the prepared cast sheet. Top and bottom covers were prepared by laminating cover sheets with 25 layers and 21 printed dielectric active sheets were laminated and pressed to provide a bar. The bar was cut into chips of 3.2 mm1.6 mm size by a cutter. The 3216-sized multi-layered ceramic capacitor (MLCC) chip was baked-out and sintered in the reducing atmosphere of 0.1% H.sub.2/99.9% N.sub.2 (H.sub.2O/H.sub.2/N.sub.2 atmosphere) at 1200-1300 C. for 2 hours, and then heat-treated at 1000 C. under N.sub.2 atmosphere for 3 hours. The sintered chip was prepared with Cu paste for a termination process and an electrode sintering process to provide an external electrode.

(19) TABLE-US-00001 TABLE 1 Mole ratio of each main component Mole of each additive per (1 x)BaTiO.sub.3 + 100 mole (1 x)BT-xNKN x(Na.sub.1yK.sub.y)NbO.sub.3:(1 x)BT-xNKN main component 1.sup.st main 2nd main 1st 2.sup.nd Ex- component component subcom- subcom- am- BaTiO.sub.3 (Na.sub.1yKy)NbO.sub.3 ponent ponent ple (1 x) (x) y MnO.sub.2 SiO.sub.2 1 1.000 0.000 0.500 0.50 0.50 2 0.995 0.005 0.500 0.50 0.50 3 0.990 0.010 0.500 0.50 0.50 4 0.980 0.020 0.500 0.50 0.50 5 0.970 0.030 0.500 0.50 0.50 6 0.950 0.050 0.500 0.50 0.50 7 0.900 0.100 0.500 0.50 0.50 8 0.800 0.200 0.500 0.50 0.50 9 0.700 0.300 0.500 0.50 0.50 10 0.600 0.400 0.500 0.50 0.50 11 0.500 0.500 0.500 0.50 0.50 12 0.400 0.600 0.500 0.50 0.50 13 0.950 0.050 0.500 0.00 0.50 14 0.950 0.050 0.500 0.10 0.50 15 0.950 0.050 0.500 0.30 0.50 16 0.950 0.050 0.500 1.00 0.50 17 0.950 0.050 0.500 2.00 0.50 18 0.950 0.050 0.500 5.00 0.50 19 0.950 0.050 0.500 7.00 0.50 20 0.950 0.050 0.500 0.50 0.00 21 0.950 0.050 0.500 0.50 0.10 22 0.950 0.050 0.500 0.50 1.00 23 0.950 0.050 0.500 0.50 2.00 24 0.950 0.050 0.500 0.50 5.00 25 0.950 0.050 0.500 0.00 7.00 26 0.950 0.050 0.200 0.50 0.50 27 0.950 0.050 0.300 0.50 0.50 28 0.950 0.050 0.700 0.50 0.50 29 0.950 0.050 1.000 0.50 0.50

(20) As shown in Table 2, the prototype multi-layered ceramic capacitor samples were measured to determine capacitance, DF, insulation resistance, TCC, resistance degradation with voltage-step up at 150 C. RT (room temperature) electrostatic capacitance and dielectric loss of the multi-layered ceramic capacitor chip were determined under conditions of 1 kHz, AC 0.2 V/m by using a LCR meter. Permittivity of the dielectric material of the multi-layered ceramic capacitor chip was calculated from the electrostatic capacitance, dielectric material thickness, internal electrode area, and number of layers of the multi-layered ceramic capacitor chip.

(21) Samples each were taken and RT insulation resistance (IR) was determined after 60 seconds while DC 10 V/m was applied to the samples. Changes in electrostatic capacitance with temperature were determined from 55 C. to 150 C.

(22) High-temperature IR step-up tests were performed at 150 C. with increasing voltage step by 5 V/m to determine the resistance degradation. The duration for each step was 10 min and resistance was determined every 5 seconds. High-temperature withstand voltages were obtained from the high-temperature IR step-up test. To determine high-temperature withstand voltage, an increasing voltage step of DC 5 V/m at 150 C. for 10 minutes was applied to a 3216 size chip of the 20-layered dielectric material having 7 m thickness after sintering. The high-temperature withstand voltage is a voltage for IR to withstand 10.sup.5 or above.

(23) Table 2 shows properties of prototype multi-layered ceramic capacitor chips corresponding to the compositions in Table 1.

(24) TABLE-US-00002 TABLE 2 Electrical properties of the proto-type MLCC samples (permittivity/DF measurement condition: AC 0.2 V/um, 1 kHz) (Resistivity measurement condition at room temperature: DC 10 V/um) Temp RT (150 C.) Sintering specific withstand temperature RT resistance TCC(%) TCC(%) TCC(%) voltage(V/ Exam. ( C.) permittivity DF(%) (Ohm-cm) (55 C.) (125 C.) (150 C.) um)* Result 1 1250.0 3156.0 3.520 8.221E+12 11.7% 12.4% 35.2% 70 X 2 1250.0 2766.0 3.685 8.564E+12 12.2% 11.2% 15.0% 70 3 1250.0 2751.0 3.580 8.623E+12 12.4% 10.4% 14.5% 70 4 1250.0 2548.0 3.470 9.630E+12 12.5% 9.5% 13.5% 75 5 1250.0 2477.0 3.410 1.023E+13 12.8% 9.1% 12.8% 70 6 1250.0 2348.0 3.260 1.174E+13 13.2% 8.8% 11.8% 65 7 1250.0 2247.0 3.100 1.210E+13 13.4% 8.5% 10.6% 65 8 1250.0 2197.0 2.980 1.256E+13 13.5% 8.8% 10.2% 65 9 1250.0 1948.0 2.840 1.326E+13 9.5% 6.2% 9.8% 5 10 1250.0 1757.0 2.640 1.335E+13 9.2% 5.8% 9.6% 0 11 1250.0 1548.0 2.480 1.458E+13 8.8% 5.6% 9.5% 5 12 1250.0 1284.0 1.820 4.568E+13 7.8% 5.1% 9.2% 5 X 13 1250.0 21868.0 126.500 8.480E+07 5 X 14 1250.0 2568.0 4.280 5.120E+11 13.1% 9.5% 12.5% 50 15 1250.0 2437.0 4.020 7.480E+12 12.9% 9.4% 11.7% 55 16 1250.0 2296.0 2.350 8.308E+12 12.8% 2.4% 9.8% 65 17 1250.0 1868.0 2.260 6.335E+11 11.6% 2.3% 8.5% 65 18 1250.0 1567.0 2.170 2.407E+11 11.2% 2.1% 8.4% 60 19 1250.0 1365.0 1.930 7.408E+10 10.4% 1.9% 7.7% 55 X 20 1300.0 2532.0 3.990 5.688E+12 13.7% 7.9% 10.1% 45 X 21 1270.0 2417.0 3.840 6.408E+12 13.6% 7.8% 11.5% 55 22 240.0 2323.0 3.120 1.245E+13 12.8% 8.4% 11.7% 60 23 1250.0 2284.0 2.990 1.070E+13 11.8% 8.6% 12.2% 55 24 1270.0 2187.0 2.970 1.123E+13 11.7% 7.4% 11.7% 50 25 1290.0 2048.0 2.880 8.887E+12 11.4% 7.6% 11.6% 40 X 26 1250.0 1645.0 2.830 6.208E+12 11.8% 12.5% 9.9% 35 X 27 1250.0 1948.0 3.030 8.450E+12 12.3% 11.1% 12.7% 55 28 1250.0 2046.0 1.870 8.550E+12 10.7% 10.5% 15.0% 55 29 1250.0 1852.0 1.8 9.523E+12 9.7% 6.2% 9.9% 50 Wherein, X refers to unqualified, refers to qualified.

(25) y=0.5 in the second main component (Na.sub.1-yK.sub.y)NbO.sub.3 and the content of the first subcomponent MnO.sub.2 and the second subcomponent SiO.sub.2 are 0.5 at % and 0.5 at %, respectively, based on the main powder (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3 in Examples 1-12, according to Table 1. Properties of the prototype chip according to the content of BT of the first main component, 1-x, and the content of (Na.sub.1-yK.sub.y)NbO.sub.3 of the second main component, x, are listed in Table 2. As the x content increases from 0 (Example 1) to 0.6 (Example 12), the permittivity gradually decreases. When the x content is 0 (Example 1), the permittivity is 3156 which is very high but TCC (150 C.) deviates from 15% range of the X8R standard as 35.2%. On the other hand, when the x content is 0.6 (Example 12), the RT permittivity rapidly decreases to less than 1500.

(26) Samples of Examples 2-11 have the RT permittivity of 1500 or above and high-temperature withstand voltage of 50 V/m or above, and satisfy TCC (150 C.) of 15% of the X8R thermal property. Thus, an appropriate x range may be 0.005x0.5.

(27) y=0.5 in the second main component (Na.sub.1-yK.sub.y)NbO.sub.3, the content x of (Na.sub.1-yK.sub.y)NbO.sub.3 is 0.05, and SiO.sub.2 content of the second subcomponent is 0.5 at %, based on the main powder (1-x)BaTiO.sub.3-x(Na.sub.1-y K.sub.y)NbO.sub.3 in Examples 13-19 according to Table 1. Properties of the prototype chip with the MnO.sub.2 content of the first subcomponent are listed in Table 2. When the content of Mn is 0 (Example 13), the RT specific resistance is 8.480E7 which is very low, while when the content of Mn is 0.1 or above (Example 14), it shows insulation properties of 1E11 or above. As the content of Mn increases, the permittivity and the RT specific resistance continuously decrease so that when the content of Mn increases to 7 at % (Example 19), the permittivity decreases to 1365 which is below 1500 and the RT specific resistance decreases to less than 1E11.

(28) Samples of Example 14-18 show desired properties of the permittivity, the high-temperature withstand voltage, and TCC properties so that the content of Mn may be 0.1-5.0 at %.

(29) y=0.5 in the second main component (Na.sub.1-yK.sub.y)NbO.sub.3, the content x of (Na.sub.1-yK.sub.y)NbO.sub.3 is 0.05, and MnO.sub.2 content of the first subcomponent is 0.5 at %, based on the main powder (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3 in Examples 20-25 according to Table 1. Properties of the prototype chip with the SiO.sub.2 content of the second subcomponent are listed in Table 2. When the content of SiO.sub.2 is 0 (Example 20), the sintering temperature increases to about 1300 C., while as the content of SiO.sub.2 increases (Examples 21-24), the sinterability is improved. When the content of SiO.sub.2 is 7 at % (Example 25), there is no improvement in the sinterability anymore and the high-temperature withstand voltage is deteriorated to less than 50 V/m. According to the results of the permittivity, the high-temperature withstand voltage, TCC properties, and the sinterability from Examples 20-25, the content of SiO.sub.2 may be 0.1-5.0 at %.

(30) x=0.05 in the second main component (Na.sub.1-yK.sub.y)NbO.sub.3 and the content of the first subcomponent MnO.sub.2 and the second subcomponent SiO.sub.2 are 0.5 at % and 0.5 at %, respectively, based on the main powder (1-x)BaTiO.sub.3-x(Na.sub.1-yK.sub.y)NbO.sub.3 in Examples 26-29, according to Table 1. Properties of the prototype chip according to K content, y, and Na content, 1-y, of the second main component (Na.sub.1-yK.sub.y)NbO.sub.3 are listed in Table 2. When the K content, y, in the second main component (Na.sub.1-yK.sub.y)NbO.sub.3 is decreased from 0.3 (Example 27) to 0.2 (Example 26) (from 0.5), the permittivity decreases and the high temperature voltage proof property is deteriorated. When y=0.2 (Example 26), the high-temperature withstand voltage becomes less than 50 V/m. On the other hand, when the K content, y, is increased from 0.7 (Example 28) to 1.0 (Example 29) (from 0.5), the permittivity and the high-temperature withstand voltage are somewhat decreased but the permittivity, the high-temperature withstand voltage, and the TCC properties satisfy the target properties of the present inventive concept. According to the results of the permittivity, the high-temperature withstand voltage, and the RT specific resistance from Examples 26-29, the K content y may be 0.3y1.0.

(31) The present inventive concept relates to a dielectric ceramic composition and an electrical device using the same and, more particularly, to a dielectric ceramic composition and an electrical device using the same which satisfies X5R, X7R, and X8R properties specified in the EIA standard. According to the present inventive concept, properties such as an increase in the Curie temperature and permittivity at a high temperature can be provided without adding Pb, which is harmful to the environment, to a parent material. In addition, X8R thermal property and voltage proof property may be satisfied.

(32) The spirit of the present inventive concept has been described by way of example hereinabove, and the present inventive concept may be variously modified, altered, and substituted by those skilled in the art to which the present inventive concept pertains without departing from essential features of the present inventive concept. Accordingly, the exemplary embodiments disclosed in the present inventive concept and the accompanying drawings do not limit but describe the spirit of the present inventive concept, and the scope of the present inventive concept is not limited by the exemplary embodiments and accompanying drawings. The scope of the present inventive concept should be interpreted by the following claims and it should be interpreted that all spirits equivalent to the following claims fall within the scope of the present inventive concept.