Manufacturing method of graphene modulated high-K oxide and metal gate MOS device

Abstract

A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeO.sub.x on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved. The fluorinated graphene can enable the graphene to become a high-quality insulator on the basis of keeping the excellent property of the graphene, so that the influence thereof on the electrical property of the Ge-based device is reduced. By adopting the ozone plasmas to treat the Ge-based graphene and then by adopting the atomic layer deposition technology, an ultrathin Hf-based high-k gate dielectric layer can be obtained.

Claims

1. A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, characterized in that the manufacturing method at least comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate, the graphene thin film is used as a passivation layer to inhibit the formation of instable oxide GeOx in the Ge-based substrate and to stop mutual diffusion between the high-k gate dielectric and the Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form a fluorinated graphene insulating thin layer; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; 4) forming a metal electrode on the surface of the high-k gate dielectric.

2. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that the manufacturing method further comprises the following steps: 5) removing part of the metal electrode, the high-k gate dielectric and the fluorinated graphene to form a gate structure of the MOS device; 6) forming a source region and a drain region through an ion implantation technology; 7) manufacturing a source region electrode and a drain region electrode.

3. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that the step 1 comprises the following steps: 1-1) growing the graphene thin film on the metal substrate; 1-2) transferring the graphene thin film onto the Ge-based substrate; 1-3) annealing to enhance the bonding of the graphene thin film and the Ge-based substrate.

4. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that, in the step 1, a chemical vapor deposition method is adopted to grow the graphene thin film in situ on the surface of the Ge-based substrate.

5. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that, in the step 2, XeF.sub.2 gas is adopted to conduct plasma fluorination treatment to the graphene thin film.

6. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that the material of the high-k gate dielectric is an Hf-based dielectric.

7. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that, in the step 4, a physical vapor deposition method is adopted to form the metal electrode, wherein the metal electrode is a Pt electrode.

8. The manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device according to claim 1, characterized in that, after the step 4, the manufacturing method further comprises a step of annealing in an N.sub.2 and O.sub.2 atmosphere and conducting interface diffusion and electrical property testing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1a to FIG. 2b respectively show a structural schematic view represented by the step 1 of the manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device of the present invention.

(2) FIG. 3 to FIG. 4 respectively show a structural schematic view represented by the step 2 of the manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device of the present invention.

(3) FIG. 5 to FIG. 6 respectively show a structural schematic view represented by the step 3 of the manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device of the present invention.

(4) FIG. 7 to FIG. 8 respectively show a structural schematic view represented by the step 4 of the manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device of the present invention.

(5) FIG. 9 shows a structural schematic view represented by the steps 5-7 of the manufacturing method of the graphene modulated high-k oxide and metal gate Ge-based MOS device of the present invention.

DESCRIPTION OF REFERENCE NUMBERS OF ELEMENTS

(6) 101 Ge-based substrate 102 Graphene thin film 103 PMMA base 104 CH.sub.4 105 H.sub.2 106 Fluorinated grapheme 107 High-k gate dielectric 108 Metal electrode 109 Source region 110 Drain region 111 Source region electrode 112 Drain region electrode

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(7) The implementation mode of the present invention is described below through specific embodiments. One skilled in the art can easily understand other advantages and effects of the present invention according to the contents disclosed by the description. The present invention can be implemented or applied through other different specific implementation modes, various details in the description can also be based on different viewpoints and applications, various modifications or changes can be made without departing from the spirit of the present invention.

(8) Please refer to FIG. 1a to FIG. 9. It is to be noted that the views provided in this embodiment are only exemplary to describe the basic concept of the present invention, thus the drawings only show components related to the present invention and are not drawn according to component number, shape and size during actual implementation, the form, number and proportion of each component during actual implementation can be changed freely, and the layout form of the components may be more complex.

(9) As shown in FIG. 1a to FIG. 9, the present invention provides a manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which at least comprises the following steps:

(10) As shown in FIG. 1a to FIG. 2b, the method begins with step 1) introducing a graphene thin film 102 on a Ge-based substrate 101.

(11) As shown in FIG. 1a to FIG. 1b, in one specific implementation process, the step 1 comprises the following steps:

(12) The process begins with step 1-1) growing the graphene thin film 102 on the metal substrate.

(13) As an example, the metal substrate is a substrate formed of copper or nickel, etc.

(14) Then the process goes into step 1-2) transferring the graphene thin film 102 onto the Ge-based substrate 101.

(15) As an example, firstly the graphene thin film 102 which grows on the metal substrate is transferred to a PMMA base 103, then the graphene thin film 102 is attached onto the surface of the Ge-based substrate 101 through the PMMA base 103, and thereafter, the PMMA base 103 is washed and removed by adopting acetone solution.

(16) Finally the process goes into step 1-3) annealing to enhance the bonding of the graphene thin film 102 and the Ge-based substrate 101.

(17) As shown in FIG. 2a to FIG. 2b, in another specific implementation process, in the step 1, a chemical vapor deposition method is adopted to grow the graphene thin film 102 in situ on the surface of the Ge-based substrate 101.

(18) As an example, by using H.sub.2 105 and CH.sub.4 104 as reaction gases, the chemical vapor deposition method is adopted to grow the graphene thin film 102 in situ on the surface of the Ge-based substrate 101 at low temperature.

(19) The graphene thin film 102 can be used as a passivation layer to inhibit the formation of instable oxide GeO.sub.x in the Ge-based substrate and to stop mutual diffusion between the high-k gate dielectric 107 and the Ge-based substrate 101 in future.

(20) As shown in FIG. 3 to FIG. 4, then the process goes into step 2) conducting fluorination treatment to the graphene thin film 102 to form a fluorinated graphene 106 insulating thin layer.

(21) As an example, the graphene thin film 102 is placed in plasma equipment, and ionized XeF.sub.2 gas is adopted to conduct plasma fluorination treatment to the graphene thin film 102 to form the fluorinated graphene 106 insulating thin layer.

(22) The fluorinated graphene 106 can enable the graphene to become a high-quality insulator on the basis of keeping relevant excellent property of the graphene, and the influence of the graphene on the electrical property of a Ge channel material can be reduced by conducting fluorination treatment to the graphene by adopting plasmas.

(23) As shown in FIG. 5 to FIG. 6, then the process goes into step 3) activating the surface of the fluorinated graphene 106 by adopting ozone plasmas, and then forming a high-k gate dielectric 107 on the surface of the fluorinated graphene 106 through an atomic layer deposition technology.

(24) As an example, the material of the high-k gate dielectric 107 is a Hf-based dielectric. In this embodiment, the material of the high-k gate dielectric 107 is HfO.sub.2. Of course, in other embodiments, the high-k gate dielectric 107 can also be HfON, HfAlO, HfAlON, HfTaO, HfTaON, HfSiO, HfSiON, HfLaO or HfLaON, etc.

(25) Since the graphene is a two-dimensional material, it is difficult to deposit a high-quality metal oxide layer thereon by adopting the atomic layer deposition (ALD) technology. However, by adopting ozone plasma surface activation technology, dangling bonds can be produced on the surface of the graphene, so that necessary conditions are provided for subsequent ALD precursor surface adsorption to obtain a high-quality ultrathin high-k gate dielectric 107 layer.

(26) As shown in FIG. 7 to FIG. 8, finally the process goes into step 4) forming a metal electrode 108 on the surface of the high-k gate dielectric 107.

(27) As an example, the physical vapor deposition technology is adopted to form the metal electrode 108, and the metal electrode 108 is a Pt electrode. Of course, the metal electrode 108 can also be a substrate of other metals such as Au, Ti and etc.

(28) As an example, after the step 4, the manufacturing method further comprises a step of annealing in an N.sub.2 and O.sub.2 atmosphere and conducting interface diffusion and electrical property testing. This step can be used for researching on the diffusion behavior and relevant electrical properties of the Hf-based high-k oxide and metal gate and Ge interface. Specifically, after conventional MOS process annealing is adopted, a high resolution transmission electron microscopy can be adopted to characterize a sample interface state, XPS is adopted to conduct deep analysis and research on the distribution situation of elements on the interface before and after annealing, etc.

(29) As shown in FIG. 8, a fluorinated graphene 106 thin film 102 is added in the interface between the high-k oxide and metal gate and the Ge-based substrate 101, so that mutual diffusion of interface atoms can be stopped and the interface property of an HfO.sub.2/Ge stacked structure can be modulated. At the same time, by utilizing the two-dimensional material feature of the graphene, the EOT of the dielectric layer of the MOS device can be effectively controlled.

(30) As shown in FIG. 9, as an example, after the Ge-based substrate 101/fluorinated graphene 106/high-k oxide and metal gate stacked structure is formed, the manufacturing method further comprises steps of forming the MOS device by adopting a conventional MOS technology, and specifically further comprises the following steps:

(31) The process begins with step 5) removing part of the metal electrode 108, the high-k gate dielectric 107 and the fluorinated graphene 106 to form a gate structure of the MOS device.

(32) As an example, a dry etching technology is adopted to form the gate structure.

(33) Then the process goes into step 6) forming a source region 109 and a drain region 110 of the MOS device through an ion implantation technology.

(34) As an example, firstly a lightly doped drain (LDD) can be formed through the ion implantation technology and an annealing technology.

(35) As an example, protective side wall structures such as silicone oxide and silicon nitride can be formed on the side walls of the gate structure.

(36) As an example, the MOS device can be a PMOS, NMOS or CMOS device. Different types of MOS devices can be realized through different types of ion implantation.

(37) Finally the process goes into step 7) manufacturing a source region electrode 111 and a drain region electrode 112.

(38) As an example, the source region electrode 111 and the drain region electrode 112 can be formed through a direct sputtering or electroplating technology and metal germanide can also be formed through annealing after deposition and be used as electrodes.

(39) To sum up, the present invention provides the manufacturing method of the graphene modulated high-k oxide metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film 101 on a Ge-based substrate 102; 2) conducting fluorination treatment to the graphene thin film 102 to form fluorinated graphene 106; 3) activating the surface of the fluorinated graphene 106 by adopting ozone plasmas, and then forming a high-k gate dielectric 107 on the surface of the fluorinated graphene 106 through an atomic layer deposition technology; 4) forming a metal electrode 108 on the surface of the high-k gate dielectric 107. The present invention has the following beneficial effects: 1) since the graphene is used as a passivation layer to inhibit the production of a GeO.sub.x intermediate layer, to stop mutual diffusion of interface atoms and to modulate the interface property of a HfO.sub.2/Ge stacked structure, and the two-dimensional material property of graphene is utilized, the EOT of the dielectric layer of the MOS device is effectively controlled; 2) the excellent property of HfO.sub.2 as a dielectric material and the ultrahigh mobility feature of Ge as a substrate material are integrated; and 3) since graphene is transitioned from a conductor to an insulator by conducting fluorination treatment to graphene, the influence of the graphene passivation layer on the channel property is reduced; and by adopting ozone plasmas to treat the Ge-based graphene, necessary conditions are provided for the growth of ultrathin HfO.sub.2. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has a great industrial application value.

(40) The above-mentioned embodiments are only exemplary to describe the principle and the effect of the present invention but not to limit the present invention. Those familiar with the art can make modifications or changes to the above-mentioned embodiments without departing from the spirit and the scope of the present invention. Therefore, all equivalent modifications or changes made by those of common knowledge in the art without departing from the spirit and the technical idea disclosed by the present invention shall still be covered by the claims of the present invention.