SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Abstract

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

Claims

1. A semiconductor device, comprising: a substrate; an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate; two source/drain regions disposed on the oxide semiconductor layer; a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; and a second insulating layer disposed between the oxide semiconductor layer and the source/drain regions, wherein each source/drain region is vertically aligned with the oxide semiconductor layer and the second insulating layer.

2. (canceled)

3. The semiconductor device according to claim 2, wherein the second insulating layer comprises an oxide semiconductor material different from that of the oxide semiconductor layer.

4. The semiconductor device according to claim 2, wherein the second insulating layer has a thickness smaller than that of the oxide semiconductor layer.

5. The semiconductor device according to claim 2, wherein the second insulating layer and the oxide semiconductor layer comprise indium gallium zinc oxide (InGaZnO), InGaO.sub.2, InZnO.sub.2, GaInO, ZnInO, or GaZnO.

6-7. (canceled)

8. The semiconductor device according to claim 1, further comprising: a second gate electrode disposed below the oxide semiconductor layer and overlapped the oxide semiconductor layer.

9. The semiconductor device according to claim 8, further comprising: a third insulating layer disposed between the oxide semiconductor layer and the second gate electrode, wherein the third insulating layer comprises a oxide semiconductor material different from the oxide semiconductor layer.

10. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a monolayer structure or a multilayer structure.

11. (canceled)

12. A method for forming a semiconductor device, comprising: providing a substrate having a first insulating layer formed thereon; forming an oxide semiconductor layer on the first insulating layer; forming two source/drain regions on the oxide semiconductor layer; forming a bottom oxide layer covering the source/drain regions; forming high-k dielectric layer on the bottom oxide layer; and performing a oxygen treatment on the high-k dielectric layer in the presence of a gas containing an oxygen element.

13. The method for forming a semiconductor device according to claim 12, further comprising: forming a second insulating layer between the oxide semiconductor layer and the source/drain regions, wherein the second insulating layer comprises a oxide semiconductor material different from the oxide semiconductor layer.

14. The method for forming a semiconductor device according to claim 13, wherein the second insulating layer and the oxide semiconductor layer comprise indium gallium zinc oxide (InGaZnO), InGaO.sub.2, InZnO.sub.2, GaInO, ZnInO, or GaZnO.

15. The method for forming a semiconductor device according to claim 12, further comprising: forming a top oxide layer on the high-k dielectric layer, wherein the bottom oxide layer, the high-k dielectric layer and the top oxide layer consists a sandwiched gate dielectric structure; and forming a first gate electrode between the source/drain regions and on the sandwiched gate dielectric structure, wherein the first gate electrode is vertically aligned with the top oxide layer and the high-k dielectric layer.

16. The method for forming a semiconductor device according to claim 15, wherein the forming of the sandwiched gate dielectric structure and the first gate electrode comprises: sequentially forming a high-k dielectric material layer and an oxide layer covered on the bottom oxide layer; forming a gate layer on the oxide layer; and simultaneously patterning the high-k dielectric material layer, the oxide layer and the gate layer, to form the first gate electrode, the high-k dielectric layer and the top oxide layer.

17. The method for forming a semiconductor device according to claim 12, further comprising: forming a second gate electrode below the oxide semiconductor layer, wherein the second gate electrode overlaps the oxide semiconductor layer.

18. The method for forming a semiconductor device according to claim 12, wherein the oxygen treatment is performed by supplying 100% O.sub.2 gas under 400 C.

19. The method for forming a semiconductor device according to claim 12, further comprising: forming a first contact structure electrically connected to the source/drain regions.

20. The method for forming a semiconductor device according to claim 15, further comprising: forming a second contact structure electrically connected to the first gate electrode.

21. A semiconductor device, comprising: a substrate; an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate; two source/drain regions disposed on the oxide semiconductor layer; a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; a top oxide layer disposed on the high-k dielectric layer, wherein the bottom oxide layer, the high-k dielectric layer and the top oxide layer consists of a sandwiched gate dielectric structure; and a first gate electrode disposed between the two source/drain regions and on the sandwiched gate dielectric structure, wherein the first gate electrode overlaps the oxide semiconductor layer, and the top oxide layer and the high-k dielectric layer are vertically aligned with the first gate electrode.

22. A semiconductor device, comprising: a substrate; an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate; two source/drain regions disposed on the oxide semiconductor layer; a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; and two via plugs electrically connected to the two source/drain regions respectively, wherein the via plugs do not contact the high-k dielectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 to FIG. 7 show schematic diagrams of the method for forming a semiconductor structure according to one embodiment of the present invention.

[0013] FIG. 8 to FIG. 9 show schematic diagrams of the method for forming a semiconductor structure according to another embodiment of the present invention.

DETAILED DESCRIPTION

[0014] To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

[0015] Please refer to FIG. 1 to FIG. 7, showing schematic diagrams of the method for forming a semiconductor structure according to one embodiment of the present invention. First, a substrate 300 is provided and an insulation layer 302 and an insulation layer 304 are formed sequentially on the substrate 300. The substrate 300 can be any component that can serve as a base for forming devices. In one embodiment, the substrate 300 can comprise a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a single crystal silicon substrate, a single crystal silicon germanium substrate, an amorphous silicon substrate, or a silicon on insulator (SOI), but it is not limited thereto. In one embodiment, one or more than one insulation layer (not shown) can be disposed between the substrate 300 and the insulation layer 302, and a metal interconnection system (not shown), an electronic device (not shown) such as metal oxide semiconductor (MOS), a photo-diode, a passive components such as an inductor, a capacitor or a resistor, can be formed in said insulation layer.

[0016] The insulation layer 302 or the insulation layer 304 may be a single layer or has a multi-layered structure, and the material thereof may be a low-k dielectric material such as silicon dioxide (SiO.sub.2), or a high-k dielectric material, preferably a rare earth metal oxide such as hafnium oxide (HfO.sub.2), but is not limited thereto. Generally speaking, a conductive layer can be formed in the insulation layer 302 and its material preferably is metal such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), cadmium (Cd), a nitride thereof, an oxide thereof, alloys thereof, or a combination thereof. Said conductive layer can have a pattern for being as a back gate electrode 340, as shown in FIG. 1.

[0017] In addition, an oxide semiconductor (OS) material layer 306 and a conductive material layer 310 are disposed on the substrate 300, sequentially stacking one the insulation layer 302 and the insulation layer 304. The OS material layer 318 may be a single layer or have a multilayered structure, wherein each may contain the same or different materials, e.g., indium gallium zinc oxide (InGaZnO), indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide, cadmium oxide, hafnium oxide (HfO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO) or indium gallium aluminum oxide (InGaAlO), and is not limited thereto. Preferably, it contains C-axis aligned crystal InGaZn (CAAC-InGaZnO), that exhibits high carrier mobility and low leakage current and can serves as a channel layer of the bottom gate electrode 340. It is understood for one skilled in the art that the OS material layer 318 may have other material or may have multi layers, wherein each layer has the same or different material, which is not limited to above embodiment.

[0018] In one embodiment, an insulation layer 308 can be formed on the OS material layer 306, as shown in FIG. 1. It is worth noting that the insulation layer 308 is preferably composed an oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO), indium gallium oxide (IGaO), indium zinc oxide (IZO), indium zinc oxide (IZO), and is not limited thereoto. Preferably, the material of the OS in the insulation layer 308 is different that of the OS material layer 306, and a thickness of the insulation layer 308 is less than that of the OS material layer 306, but is not limited thereto. By doing this, the insulation layer 308 can serve as a barrier layer.

[0019] Next, the OS material layer 306 and the conductive material layer 310 are patterned to form a patterned OS layer 316 and a patterned conductive layer 320. The patterning process may be carried out by one single photo-etching-process (PEP) or a plurality of PEPs. In one embodiment with the insulation layer 308, the OS material layer 306, the insulation layer 308 and the conductive material layer 310 can be patterned simultaneously wherein the insulation layer 304 is used as an etch stop layer. Accordingly, the sidewall of the patterned OS layer 316, the sidewall of the patterned insulation layer 318 and the sidewall of the patterned conductive layer 320 are vertically aligned with each other. As shown in FIG. 2, it is noted that the patterned OS layer 316 is disposed correspondingly to the bottom gate electrode 340, preferably, a projection of the bottom gate electrode 340 along a vertical direction of the substrate 300 is disposed at a center of the patterned OS layer 316.

[0020] Next, the patterned conductive layer 324 is patterned again to form two separate parts, preferably two source/drain regions (S/D region) 330 with the same width, wherein a part of the OS layer 316 or the insulation layer 318 is exposed by the two S/D regions 330. On the other hand, as described above, the outer sidewalls of the S/D region 330 are vertically aligned with the sidewall of the OS layer 316 and the sidewalls of the insulation layer 318. The patterning process may be carried out by one single PEP or a plurality of PEPs.

[0021] Thereafter, a dielectric layer is formed comprehensively on the substrate 300 and the S/D regions 330, in which it may be one single layer or have a multi-layered structure. Preferably, the dielectric layer includes a low-k dielectric material such as SiO.sub.2, serving as a bottom oxide layer 322. Next, as shown in FIG. 4, a high-k dielectric layer 324 is formed conformally on the bottom oxide layer 322. In one embodiment, the material of the high-k dielectric layer 324 is metal oxide, preferably a rare earth metal oxide such as includes hafnium oxide (HfO.sub.2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta.sub.2O.sub.5), zirconium oxide (ZrO.sub.2), zirconium silicon oxide (ZrSiO.sub.4), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate (PbZr.sub.xTi.sub.1-xO.sub.3, PZT, barium strontium titanate (Ba.sub.xSr.sub.1-xTiO.sub.3, BST) and is not limited thereto. It is noted that the bottom oxide layer 322 directly contacts the S/D regions and the exposed OS layer 318 for protect the sidewall of the S/D regions 330 after patterning as well as the exposed OS layer 318. As shown in FIG. 4, when there is no insulation layer 318, the bottom oxide layer 322 directly contacts the S/D region 330 and the exposed OS layer 316.

[0022] Subsequently, a thermal and oxygen ambience treatment P is performed on the high-k dielectric layer 324. The oxygen atom in the high-k dielectric layer 324 can be released during the thermal process, and the high-k dielectric layer 324 can be tuned by the oxygen ambience treatment, so as to avoid the oxygen vacancy phenomenon. In one embodiment, the thermal and oxygen ambience treatment P includes supplying gas containing O.sub.2 under 300 C. to 500 C., preferably 100% O.sub.2 gas under 400 C. It is understood for one skilled in the art that the thermal and oxygen ambience treatment P can also be performed by other process, and is not limited to the above steps. In another embodiment, the thermal process and the oxygen treatment can be performed in sequence, for example, a thermal process with 300 C. to 500 C. is performed firstly, and the oxygen treatment such as annealing process, rapid thermal annealing process or plasma treatment can be performed.

[0023] Subsequently, as shown in FIG. 5, a gate dielectric material layer 326 and a gate material layer 328 are formed conformally on the substrate 300. In one embodiment, the gate dielectric material layer 326 may be silicon dioxide layer or a high-k dielectric layer. The gate material layer 328 comprises a variety of conductive material, e.g., a metal layer comprising gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), cadmium (Cd), a nitride thereof, an oxide thereof, alloys thereof, or a combination thereof.

[0024] Next, the gate dielectric material layer 328, the gate material layer 326 and the below high-k dielectric layer 324 are patterned to respectively form a top gate electrode 338, a top oxide layer 336 and a high-k dielectric layer 334. It is noted that the top oxide layer 336, the high-k dielectric layer 334, and the below bottom oxide layer 322 together form a sandwich gate dielectric structure, serving as a gate dielectric layer of the top gate electrode 338. In the sandwich gate dielectric structure, only the sidewall of the top oxide layer 336 and the sidewall of the high-k dielectric layer 334 are vertically aligned with a sidewall of the top gate electrode 338, while the bottom oxide layer 322 completely covers the below substrate 300 and the S/D region 330, as shown in FIG. 6. Besides, it is noted that the method of forming the sandwich gate dielectric layer is not limited to above embodiment, and in another embodiment, depending on the design requirements, only the gate material layer 328 is patterned, or only the gate material layer 328 and the gate dielectric material layer 326 are patterned, or all the gate material layer 328, the gate dielectric material layer 326, the high-k dielectric layer 324 and the below bottom oxide layer 322 are patterned, therefore forming different sandwich gate dielectric structures (not shown).

[0025] Subsequently, a dielectric layer 342 is formed on the base 300 for covering the bottom oxide layer 322, the top gate electrode 338 and other structures. A plurality of via plugs 344, 346 are formed in the dielectric layer 342 to electrically connect the S/D region 326 and the top gate electrode 340, respectively. In the present embodiment, the via plug 344 penetrates through the bottom oxide layer 322 to electrically connect the S/D region 330.

[0026] In one embodiment, the via plug 344 may comprise an outer barrier layer such as titanium nitride (TiN), and an inside metal layer such as tungsten (not shown), but is not so limited. In one preferred embodiment, the plug trench (not shown) of the via plugs 344, 346 are formed by using double patterning lithography or multiple patterning process. In other words, a photolithography-etch-photolithography-etch (2P2E) process is carried out with multi steps thereto form the plug trench accessing to the top electrode 338 and the S/D region 330 so as to form the via plugs 344, 346 respectively, as shown in FIG. 7.

[0027] After the above steps, a semiconductor structure of the present invention is therefore obtained. As shown in FIG. 7, the semiconductor structure of the present invention includes a substrate 300, an insulation layer 304 on the substrate 300, two S/D regions 330, a bottom gate electrode below the insulation layer 304 and the top gate electrode above the insulation layer 304. The semiconductor structure of the present invention therefore has a dual gate transistor structure, for example, a C-axis aligned crystal OS MOSFET (CAAC-OS MOSFET), wherein the bottom gate electrode structure comprises the bottom gate electrode 340 in the insulation layer 302 and the OS layer 316 serving as a channel layer, and the bottom gate electrode at least partially overlaps with the OS layer 316. On the other hand, the top gate electrode structure comprises the top gate electrode 338 disposed on the insulation layer and between the two S/D regions 330, the OS layer 316 serving as a channel layer, and a sandwich gate dielectric structure, and the top gate electrode 338 at least partially overlaps with the OS layer 316. In one embodiment, the sandwich gate dielectric structure includes the bottom oxide 322, the high-k dielectric layer 334 and the top oxide layer 336.

[0028] According to the above description, the present invention also provides a method for forming a semiconductor structure. It is one salient feature that an additional thermal and oxygen ambience treatment on the high-k dielectric layer. The oxygen atom in the high-k dielectric layer can be released during the thermal process, and the high-k dielectric layer can be tuned by the oxygen ambience treatment, so as to avoid the oxygen vacancy phenomenon. In addition, only the sidewall of the top oxide layer 336 and the sidewall of the high-k dielectric layer 334 are vertically aligned with a sidewall of the top gate electrode 338, while the bottom oxide layer 322 completely covers the below substrate 300 and the S/D region 330. By doing this, when forming the via plugs in the subsequent steps, the bottom oxide layer can protect the below S/D region and the OS layer from damage, thereby upgrading the device performance.

[0029] To one skilled in the art, it is understood that the semiconductor structure can also be formed by other method and is not limited to above embodiment. Thus, the following context will show other embodiment of the method for forming a semiconductor structure. In simplify the description, the below description only shows the different components or steps while omitting the similar steps or components. Besides, similar components will be given the same reference number in order to make each embodiment clear.

[0030] Please refer to FIG. 8 and FIG. 9, showing a schematic diagram of a method for forming a semiconductor structure according to one embodiments of the present invention, wherein the initial steps of this embodiment are similar to the previous embodiment. After forming substrate 300, the insulation layer 302, the OS material layer 306 and the conductive material layer 310, another insulation layer 358 can be formed on the OS material layer 306 and the bottom gate electrode 340, as shown in FIG. 8. In one embodiment, the insulation layer 358 includes indium gallium zinc oxide (InGaZnO), indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide, cadmium oxide, hafnium oxide (HfO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO) or indium gallium aluminum oxide (InGaAlO), and is not limited thereto. The material of the insulation layer 358 is different that of the OS material layer 306, and a thickness of the insulation layer 358 is less than that of the OS material layer 306, but is not limited thereto. By doing this, the insulation layer 358 can serve as a barrier layer.

[0031] Subsequently, the steps shown in FIG. 2 to FIG. 9 can be carried out. In the final structure, as shown in FIG. 9, the semiconductor structure also comprises the substrate 300, the insulation layer 304 on the substrate 300, the S/D region 330, a bottom gate electrode below the insulation layer 304 and the top gate electrode above the insulation layer 304.

[0032] According to the above description, the present invention also provides a method for forming a semiconductor structure according to another embodiment. It is featured that another insulation layer is formed between the OS material layer and the bottom gate electrode and can be serve as a protective layer. By doing this, the OS layer can be protected from damage in the subsequent steps.

[0033] In summary, the present invention provides a semiconductor structure. The manufacturing steps thereof comprise an additional thermal and oxygen ambience treatment so as to improve the quality of the OS layer serving as a channel and therefore upgrading the device performance.

[0034] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.