Abstract
An evaluation and control unit (100) for a broadband lambda probe (200) and a method for operating the same are disclosed. The evaluation and control unit (100) comprises pins (RE, IPE, APE, MES) connectable to electrical wires (201, 202, 203, 204) of electrochemical cells (210, 211) of the broadband lambda probe (200), a controller (103), a ASIC reference potential source (102), wherein the ASIC reference potential source (102) is operable by means of the controller (103), a switch assembly (104) connected to each of the pins (RE, I PE, APE, MES), wherein the switch assembly (104) comprises a first transistor (T.sub.Wire) and a second transistor (T.sub.ECU), wherein the switch reference potential source (105) is connected to a gate side of the first and second transistors (T.sub.Wire, T.sub.ECU), wherein the controller (103) is configured to vary the switch reference potential (V.sub.SW) applied to the gate side of the first and second transistors (T.sub.Wire, T.sub.ECU), wherein the switch assembly (104) is configured to allow a limiting current flowing to the drain side of the first transistor (T.sub.Wire) from the ASIC reference potential if the potential at the gate side of the first and second transistors (T.sub.Wire, T.sub.ECU) is at a predetermined voltage between values of an open and closed switch.
Claims
1. Evaluation and control unit for a gas sensor, comprising: pins connectable to electrical wires of electrochemical cells of the gas sensor, a controller, an ASIC reference source, wherein the ASIC reference source is operable by means of the controller, a switch assembly connected to each of the pins, wherein the switch assembly comprises at least a first transistor, wherein a switch reference source is connected to a gate side of the first transistor and the ASIC reference source is connected to the source side of the first transistor, wherein the controller is configured to vary a switch reference potential applied to the gate side of the first transistor, wherein the switch assembly is configured to allow a limited current flowing to the drain side of the first transistor from the ASIC reference source if the potential at the gate side of the first transistor is at a predetermined voltage between values of an open and closed switch over the potential at the source side of the first transistor.
2. Evaluation and control unit according to claim 1, wherein the controller is configured to switch the ASIC reference potential provided by the ASIC reference source to a value larger than the ground of the controller while the switch assembly is in an open state.
3. Evaluation and control unit according claim 2, wherein the controller is configured to put the first transistor in a linear mode by varying the switch reference potential in relation to a source potential of the first transistor.
4. Evaluation and control unit according to claim 1, further comprising at least one comparator, wherein the controller is configured put the switch assembly in an open state if a short circuit to ground is detected by the comparator.
5. Evaluation and control unit according to claim 4, wherein the comparator is configured to detect a short circuit to ground presence or absence at one of the pins if the ASIC reference potential is raised and a potential at that pin exceeds a comparator threshold.
6. Evaluation and control unit according to claim 1, wherein the switch assembly further comprises a second transistor, wherein the switch reference source is connected to a gate side of the second transistor and the ASIC reference source is connected to the source side of the second transistor.
7. Method for operating an evaluation and control unit according to any preceding claim 1, comprising the following steps: varying the switch reference potential applied to the gate side of the first transistor, allowing a limited current flowing to the drain side of the first transistor from the ASIC reference source if the potential at the gate side of the first transistor at a predetermined voltage between values of an open and closed switch over the potential at the source side of the first transistor.
8. Method according to claim 7, further comprising switching the ASIC reference potential to a value larger than the ground of the controller while the switch assembly is in an open state.
9. Method according to claim 8, further comprising putting the first transistor in a linear mode by varying the switch reference potential in relation to a source potential of the first transistor.
10. Method according to claim 7, further comprising detecting a short circuit to ground by means of at least one comparator and putting the switch assembly in an open state if the short circuit to ground at one of the pins is detected.
11. Method according to claim 7, further comprising raising the ASIC reference potential and detecting a potential at one of the pins, wherein a short circuit to ground presence or absence is detected.
12. Computer program configured to carry out each of the steps of the method according to claim 7.
13. Electronic storage device, on which a computer program according to claim 12 is stored.
14. Electronic controller, comprising a storage device according to claim 13.
15. Evaluation and control unit according to claim 1, wherein the gas sensor is a broadband lambda probe.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0061] Further optional features and embodiments will be disclosed in more detail in the subsequent description of embodiments, preferably in conjunction with the dependent claims. Therein, the respective optional features may be realized in an isolated fashion as well as in any arbitrary feasible combination, as the skilled person will realize. The scope of the invention is not restricted by the preferred embodiments. The embodiments are schematically depicted in the Figures. Therein, identical reference numbers in these Figures refer to identical or functionally comparable elements.
[0062] In the Figures:
[0063] FIG. 1 shows an evaluation and operation unit,
[0064] FIGS. 2A to 2C show a switch assembly of the evaluation and operation unit according to a first embodiment in different states,
[0065] FIG. 3 shows a flow diagram of a method of the present invention,
[0066] FIG. 4 shows a switch assembly according to a second embodiment and
[0067] FIG. 5 shows a switch assembly according to a third embodiment.
DETAILED DESCRIPTION
[0068] FIG. 1 shows an exemplary embodiment of the evaluation and operation unit 100. The evaluation and operation unit 100 is configured to operate a gas sensor 200 such as a wide band lambda sensor or probe. Basically, the evaluation and operation unit 100 may be applied to any kind of gas sensor such as a NOx-sensor. The evaluation and operation unit 100 is connected by four pins RE, IPE, APE, MES to the electrical wires 201, 202, 203, 204 of electrochemical cells 210, 211 of the gas sensor 200. The electrochemical cells may be a Nernst cell 210 and a pump cell 211. The wires 201, 202, 203, 204 connect the electrochemical cells 210, 211 and a compensation resistor 212 of the gas sensor 200. Depending on the sensor configuration, the used wires may be different, e.g. two cell sensor with 210 and 211 and without the resistor 212, wire 204 is not present or one cell sensor with 211 without both 210 and 212 the wires 201 and 204 are not present. Other combinations are possible as well. The evaluation and operation unit 100 is exemplified by an ASIC reference source 102 to which each of the pins RE, IPE, APE, MES can individually be connected through switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES respectively via an optional resistor 101 by means of a controller 103. The ASIC reference source 102 is operable by means of the controller 103. The ASIC reference source 102 may be a potential source. Alternatively, the ASIC reference source 102 may be a current source. Each of the switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES may be realized as a switch assembly 104 as will be described in further detail below.
[0069] FIGS. 2A to 2C shows a switch assembly 104 of the evaluation and operation unit 100 according to a first embodiment in different states. The switch assembly 104 is connected to each of the pins RE, IPE, APE, MES. In other words, a separate switch assembly 104 is associated with each of the pins RE, IPE, APE, MES. The switch assembly 104 comprises a first transistor T.sub.Wire and a second transistor T.sub.ECU. Particularly, the drain side of the first transistor T.sub.Wire is connected to the pins RE, IPE, APE, MES. In detail, the switch assemblies 104 are realized by diodes or transistors depending on the used semiconductor technology. In order to prevent a current flow in both directions typically two transistors T.sub.Wire, T.sub.ECU are present. This is achieved by orienting the first transistor T.sub.Wire and the second transistor T.sub.ECU are in opposing directions, meaning that the parasitic diodes of the transistor are looking in opposite ways. Thereby, a current flowing between the right side, such as cables and pins, and the left side, such as the measurement system, with respect to the illustrations of FIGS. 2A to 2C may be effectively stopped up to very high absolute voltages between the pin and the ECU ground, i.e. the ground potential of the controller 103. A switch reference source 105 is connected to a gate side of the first and second transistors T.sub.Wire, T.sub.ECU. The switch reference source 105 may be a potential source. Alternatively, the switch reference source 105 may be a current source. The controller 103 is configured to vary the switch reference potential V.sub.SW applied to the gate side of the first and second transistors T.sub.Wire, T.sub.ECU. Particularly, the switch assembly 104 is configured to allow a limited current flowing through the first transistor T.sub.Wire from the ASIC reference source 102 if the potential at the gate side of the first and second transistors T.sub.Wire, T.sub.ECU is at a predetermined voltage between values of an open and closed for switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, and Swt.sub.MES over the potential at the source side of the first transistor T.sub.Wire. Particularly, the controller 103 is configured to set the ASIC reference potential provided by the ASIC reference source 102 to a value larger than the ground of the controller 103 while the switch assembly 104 is in an open state shown in FIG. 2B. The controller 103 is further configured to put the first transistor T.sub.Wire in a linear mode provided by the ASIC reference source 102 in relation to a source potential of the first transistor T.sub.Wire. The evaluation and control unit 100 further comprises at least one comparator (not shown in detail). The controller 103 is configured put the switch assembly 104 in the open state if a short circuit to ground presence or absence is detected by the comparator. The comparator is configured to detect a short circuit to ground at one of the pins RE, IPE, APE, MES if the ASIC reference potential is raised and a potential at that pin RE, IPE, APE, MES exceeds a comparator threshold. The operation of the switch assembly 104 will be described in further detail below with reference to FIGS. 2A to 2C.
[0070] As mentioned before, the switch assembly inside an ASIC of the evaluation and operation unit 100 consists of two transistors T.sub.Wire and T.sub.ECU with a common source. The function of the switch assembly 104 is determined by the switch Swt.sub.V which is normally in a closed state shown in FIG. 2A. In order to set the gate-source voltage of the transistors T.sub.Wire and T.sub.ECU to zero and the switch assembly 104 to open state, switch Swt.sub.C is closed when Swt.sub.V is open as shown in FIG. 2B. Diodes D.sub.GND, D.sub.Wire or D.sub.ECU are intrinsic parasitic diodes of the transistors T.sub.Wire and T.sub.ECU. In some semiconductor technologies some of the diodes might not be present. Forward current through diodes D.sub.GND, D.sub.Wire or D.sub.ECU have to be avoided. This is realized by opening Swt.sub.V and closing switch Swt.sub.C. In the proposed structure of the switch assembly 104, with switch Swt.sub.GND, the transistor T.sub.Wire is put into the linear mode, where it is high ohmic but conducting, enabling current to flow from the source side to the drain side of the transistor T.sub.Wire but limiting it as shown in FIG. 2C. Particularly, in applying a common gate potential V.sub.SW below ECU ground to the transistors T.sub.Wire and T.sub.ECU, the total switch formed by the two transistors between the ASIC reference potential and the pin, starts conducting as shown in FIG. 2A, in contrast to when the gates of the transistors are not connected to any potential, as shown in FIG. 2B. This invention additional inserts the possibility to connect the gates of the transistors T.sub.Wire and T.sub.ECU to a different potential, e.g. ECU ground GND, as shown in FIG. 2C. If the potential at the ECU side of the first transistor T.sub.Wire, i.e. source of the transistor, is larger than the gate potential of the T.sub.Wire, e.g. ECU ground, and both are larger than the external voltage at the drain of the first transistor T.sub.Wire, then the first transistor T.sub.Wire is put into linear mode. In this mode, it is neither fully conducting nor fully open, but acts as a resistance, e.g. with 6 kΩ. This means, it allows a current through the transistor, which is much smaller than it would be in the conducting state. This enables charging or discharging external structures like capacitors with time. In effect, the external voltage at the drain of the transistor can rise up to the newly introduced potential at the source of the transistor, e.g. the ECU ground. Additionally, since in this mode an internal ECU voltage is put at the source of the transistors T.sub.Wire, T.sub.ECU, no harmful voltages appear. Thus, the internal ECU circuitry is still protected.
[0071] The evaluation and operation unit 100 including the specific switch assembly 104 as described above allows treating the, generally temporary, effects of short circuit to ground. The evaluation and operation unit 100, including the specific switch assembly 104, allows raising the voltage at an ECU pin (RE, IPE, APE, MES), if the connection resistance to a fixed voltage source is not too low. The switch assembly 104 is based on current hardware protection structure and does not hinder to pin-point the short circuit to the corresponding wire. The achievement of raising the voltage only affected by coupling effects of short circuits is measureable. With the described structure, further quantitative measurements are allowed once the needed time has passed e.g. with built-in ADC inside the chip. The structure is to be applied to the wide band lambda evaluation circuitry, in order to allow measurements in the case of a short circuit of a wire to a voltage below ECU ground. In conclusion, a pin-pointing of a short circuit to ground is possible.
[0072] The method for operating the evaluation and control unit 100 will be described in further detail with reference to FIG. 3. The method can be applied to short circuit to ground diagnosis, exemplified by the following steps. In the first diagnosis step D1S1, a short circuit is detected by additional comparators not shown in FIG. 1: The method starts with a first diagnosis part at a step D1S1. If the potential at the pin RE, IPE, APE or MES is below a threshold, e.g. ECU ground, which is detectable by the comparator, it is concluded that a short circuit to ground is present. In the other case, it is deduced that no short circuit is present in step D1S2 and the first diagnosis step D1S1 is periodically repeated.
[0073] In case a short circuit to ground is found to be present, the switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES are then opened, i.e. put in the state shown in FIG. 2B, for protection reasons. In this state, the evaluation and operation unit 100 waits until the system has sufficiently cooled down in step D1S3.
[0074] In a second diagnosis part, the internal reference potential V.sub.SW is switched to a potential well above ECU ground while the switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES are still opened in step D2S1. In the following step D2S2, the switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES are then put into linear mode, i.e. the state shown in FIG. 2C. Conclusively, all pins RE, IPE, APE, MES which are not directly connected to the short circuit potential will rise, due to the resistances inside the wide band lambda sensor 200. For instance, if wire 201 is shorted to ground, the voltage at pin RE will remain on the short circuit potential while the pins IPE, APE and MES will rise to ECU ground if the sensor resistances are large enough, i.e. if the sensor is cold enough (cf. step D1S3). Alternatively, this step D2S2 can be applied to each pin RE, IPE, APE, MES separately.
[0075] After the pin potential is raised, the additional comparators can then be re-evaluated in step D2S3. If the potential at the pin RE, IPE, APE or MES has sufficiently risen, e.g. for all pins except the RE pin, the comparators will not show a voltage too low any more. Concluding, the protection to these specific pins RE, IPE, APE, MES are not necessary anymore. In this case the switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES of these pins RE, IPE, APE, MES might be closed, i.e. the state shown in FIG. 2A, in order to obtain additional data to characterize the short circuit in step D2S4.
[0076] The next step D2S5 concludes if the pin RE, IPE, APE or MES is uniquely identified. If so, this pin RE, IPE, APE or MES has been pin-pointed to in step D2S6. Whether the pin RE, IPE, APE or MES is unique, can be determined by e.g. by the measurement data of the closed switches Swt.sub.RE, Swt.sub.IPE, Swt.sub.APE, Swt.sub.MES, e.g. in which direction the pin potential grows or where no data could be retrieved. If the pin was not uniquely identified, the system can be allowed to further cool down as in step D1S3 and/or allowed to take more time for charging/discharging as in step D2S2.
[0077] The suggested method can be demonstrated by applying fault patterns to a product while studying the pin voltages at the sensor lines. In case of the used method the voltage at the ECU pin where the fault pattern is not applied is raised. Insight into its data sheet can assure its circuitry, too.
[0078] FIG. 4 shows a switch assembly 104 according to a second embodiment. Hereinafter, only the differences from the first embodiment will be described and like constructional members are indicated by like reference numerals. A basic idea of the switch assembly 104 of the second embodiment is that if there is no requirements that a pin voltage can rise higher than the supply voltage Vsply, it is not mandatory to have the second transistor T.sub.ECU. As shown in FIG. 4, the switch reference source 105 is connected to a gate side of the first transistor T.sub.Wire and the ASIC reference source 102 is connected to the source side of the first transistor T.sub.Wire. Particularly, the switch Swt.sub.V is located between the switch reference source 105 and gate side of the first transistor T.sub.Wire while switch Swt.sub.GND is arranged in parallel to the switch Swt.sub.V. The switch Swt.sub.C can be omitted.
[0079] FIG. 5 shows a switch assembly according to a third embodiment. Hereinafter, only the differences from the first embodiment will be described and like constructional members are indicated by like reference numerals. In certain technologies, it is not mandatory to use two transistors. They can be merged into one transistor indicated as the first transistor T.sub.Wire with floating bulk that can be connected either to the left or to the right depending on which voltage is higher. As shown in FIG. 5, the switch reference source 105 is connected to a gate side of the first transistor T.sub.Wire and the ASIC reference source 102 is connected to the source side of the first transistor T.sub.Wire. Particularly, the switch Swt.sub.V is located between the switch reference source 105 and gate side of the first transistor T.sub.Wire while switch Swt.sub.GND is arranged in parallel to the switch Swt.sub.V. The switch Swt.sub.C can be omitted. Further, a left switch Swt.sub.l and a right switch Swt.sub.r are shown which are connected in series with one another and are arranged in parallel to the first transistor T.sub.Wire. FIG. 5 also shows the arrangement of the left switch Swt.sub.l and the right switch Swt.sub.r in parallel with respect to diodes D.sub.GND, D.sub.Wire or D.sub.ECU.
