Periodic communication method between at least one first system and at least one second system by means of a full-duplex synchronous serial link

Abstract

The invention relates to a periodic communication method between at least one first system (2) and at least one second system (3) by means of a full-duplex synchronous serial link (4), wherein, during a communication period, data are exchanged between the first system (2) and the second system (3), including: at least one message from the first system (2) to the second system (3), at least one message from the second system (3) to the first system (2) and a clock signal, the clock signal being routed by the link (4) over a time interval, the amplitude of which is less than the communication period, the message from the first system (2) to the second system (3) and the message from the second system (3) to the first system (2) both being routed by the link (4) over said time interval.

Claims

1. A periodic communication method between at least one first system and at least one second system by a full-duplex synchronous serial link, a method in which, during one communication period, data are exchanged between the first system and the second system comprising: at least one message from the first system to the second system at least one message from the second system to the first system and a clock signal, the clock signal being routed via the link over a time interval, wherein an amplitude of the clock signal is less than the communication period, the message from the first system to the second system and the message from the second system to the first system both being routed via the link over said time interval, and a communication period comprising the following steps: (i) measurement of values of at least one electrical or mechanical quantity within a device interacting with the first system, (ii) routing via the link to the second system of these values sent by the first system, (iii) processing by the second system of the values received and generation of resultant values, (iv) routing via the link to the first system of these resultant values sent by the second system, and (v) processing by the first system of these resultant values and application of these resultant values in the device.

2. The method as claimed in claim 1, wherein the resultant values are determined in such a manner as to regulate said mechanical or electrical quantity or quantities and are applied during the step (v) to the device for this purpose.

3. The method as claimed in claim 1, wherein the step (iii) for processing by the second system of the values received and for generation of resultant values has a duration which is shorter than or equal to the duration corresponding to the difference between the communication period and the amplitude of the time interval for routing the clock signal.

4. The method as claimed in claim 1, wherein each message sent by the first system firstly comprises secondary data then primary data, and wherein each message sent by the second system firstly comprises primary data then secondary data, the link not routing simultaneously the primary data sent by the first system to the second system and the primary data sent by the second system to the first system.

5. The method as claimed in claim 4, wherein: during the step (ii), the values sent by the first system are routed in the form of the primary data, and during the step (iv), the resultant values sent by the second system are routed in the form of the primary data.

6. The method as claimed in claim 1, wherein the device comprises electronic switches, and the resultant values are duty cycle values for the electronic switches.

7. The method as claimed in claim 6, wherein the device is an electrical circuit comprising a static converter and an electrical winding of an electric motor.

8. The method as claimed in claim 7, wherein the communication period further comprises the following steps: (vi) measurement of values of current in the electrical winding of the electric motor, (vii) routing via the link to the second system of these values in the form of the primary data sent by the first system, (viii) processing by the second system of the received values and generation of duty cycle values for the electronic switches of the static converter, (ix) routing via the link to the first system of these duty cycle values in the form of the primary data sent by the second system, and (x) processing by the first system of the values received and application of the values to the electronic switches of the static converter.

9. The method as claimed in claim 8, wherein the electrical winding is a stator and multiphase winding, and in which, during the step (vi), values of current are measured in at least one phase of this stator winding.

10. The method as claimed in claim 9, wherein the static converter is an inverter.

11. The method as claimed in claim 6, wherein the second system interacts with a generator of duty cycle values.

12. The method as claimed in claim 1, wherein the link is a link of the Serial Peripheral Interface (SPI) type.

13. The method as claimed in claim 1, wherein the first system is the communication master.

14. The method as claimed in claim 1, wherein an isolation is interposed between the first system and the second system and the link passes through this isolation.

15. The method as claimed in claim 1, wherein the link has a data rate greater than or equal to 10 Mbits/s.

16. The method as claimed in claim 1, wherein one of the first system and of the second system comprises at least one programmable logic circuit and the other of the first system and of the second system comprises at least one microcontroller or at least one microprocessor.

Description

(1) The invention will be better understood upon reading the description that follows of one non-limiting example of implementation of the latter and upon examining the appended drawings in which:

(2) FIG. 1 shows schematically the physical layer according to the OSI model of an assembly within which the method according to the invention can be implemented, and

(3) FIG. 2 is a timing diagram illustrating a communication sequence when the method is implemented in the assembly in FIG. 1.

(4) FIG. 1 shows the layer 1 according to the OSI model of an assembly 1 within which the method according to the invention can be implemented.

(5) In the example in FIG. 1, the assembly 1 comprises a first system 2 and a second system 3 exchanging data by means of a full-duplex synchronous serial link 4.

(6) In the example being considered, the assembly 1 is installed onboard a vehicle which comprises an electrical circuit comprising an electric motor 6, a battery and an inverter interposed between the battery and the electric motor. The electrical circuit can comprise a connector allowing the battery to be charged via an electrical supply system, notably across the coils of the stator of the electric motor 6.

(7) In the example in question, the assembly 1 forms a part of a device for controlling the electronic switches of the inverter. These switches have for example a switching frequency of the order of a few tens of kHz, for example 20 kHz. They are for example transistors of the bipolar, field-effect or IGBT type.

(8) The first system 2 is for example a peripheral unit interacting with the inverter so as to control its electronic switches and with the electric motor 6 so as to measure the current flowing in each phase of the stator of the motor 6, the latter being notably multiphase, for example three-phase.

(9) The first system 2 sends for example duty cycle values to the electronic switches of the inverter and receives, after passage through an analog/digital converter 7, values of the currents measured in the phases of the stator of the motor 6.

(10) In the example in question, the second system 3 incorporates a generator 8 of duty cycle values as a function of values of current. This generator 8 implements for example a software processing application. As a variant, the generator 8 is external to the second system 3.

(11) The first system 2 is master in the example in FIG. 1, in other words the communication between the first system 2 and the second system 3 is triggered on the initiative of the first system 2. The latter comprises for example a trigger module 9 from which this triggering originates.

(12) Still in the example in FIG. 1, the clock signal is generated by the second system 3 which is slave. Synchronization modules 11 are integrated into the first system 2 and into the second system 3 in order to enable the timing control of the communication by the first system 1. In one variant not shown, the clock signal can be generated by the first system 2.

(13) In the example in question, the first system 2 uses a programmable logic circuit (FPGA). The first system 2 comprises, in this example, a full-duplex module 12 responsible for sending and for receiving data over the link 4. In this example, the second system 3 also comprises a full-duplex module 13.

(14) The link 4 can be of the SPI type, in which case each module 12, 13 is a full-duplex SPI controller.

(15) In one variant not shown, one of the first system 2 and of the second system 3 can comprise two half-duplex modules, one of these two half-duplex modules being responsible for the transmission by said system 2 or 3 of data over the link 4 whereas the other of these two modules is responsible for receiving data routed to said system 2 or 3 via the link 4.

(16) The link 4 allows, in the example in question, the transmission by the first system 2 of primary data, being values of current, to the second system 3 and of secondary data which can be an error flag sent to the second system 3, a mode of operation of the first system 2, temperature values or a multiplexing identifier.

(17) Again in this example, the link 4 allows the transmission by the second system 3 of primary data being duty cycle values generated on the basis of the values of current by the generator 8 and of secondary data which can be a request for reset resulting from an error flag received previously, calibrations associated with the mode of operation requested for the first system 2, a multiplexing identifier, or else limiting duty cycle values, for example.

(18) The link 4 comprises, in the example in FIG. 1, a bundle of wires 15 allowing the messages between the first system 2 and the second system 3, together with the clock signal, to be exchanged.

(19) As disclosed in the patent application filed in France by the applicant on 19 Dec. 2011 under the n 11 61961, the bundle 15 can be composed of four wires, namely a first wire responsible for the routing of the messages from the first system 2 to the second system 3, a second wire responsible for the routing of the messages from the second system 3 to the first system 2, a third wire responsible for the routing of the clock signal generated, in the example described, by the second system 3 and a fourth wire connecting a region of the third wire and the second system. Said region of the third wire from where the fourth wire originates can be positioned in such a manner that the clock signal sent by the fourth wire to the second system 3 is, within said region, substantially identical to the clock signal received by the first system 2.

(20) Again in the example in FIG. 1, the link 4 comprises a wire 17 connecting the synchronization modules 11 together and enabling the timing control of the communication by the first system 2, even though the latter does not generate the clock signal.

(21) In the example in FIG. 1, the first system 2 is galvanically isolated with respect to the second system 3. This galvanic isolation 20 is here formed by means of a transformer, but the invention is not limited to a particular embodiment of the galvanic isolation. The galvanic isolation 20 is, in this example, a multichannel isolation, each wire of the bundle 15 being received in its own channel of the isolation 20. The wire 17 of the link 4 can be received in another channel of the isolation 20.

(22) Where appropriate, the isolation 20 can be a single block or be formed by the joining of two separate isolators, the bundle 15 for example passing through one of the isolators, whereas the wire 17 passes through the other isolator.

(23) A timing diagram will now be described with reference to FIG. 2 that illustrates one example of a communication sequence within the network layer shown in FIG. 1 of the assembly 1.

(24) As can be seen, the communication established by means of the link 4 takes place, in the example, according to a communication period t, the latter notably being in the range between 25 s and 500 s, notably between 25 s and 250 s, being for example around 100 s.

(25) During each period, a clock signal 100 is sent by the second system 3 to the first system 2. This clock signal 100 is sent over a time interval, the amplitude of which t.sub.a is less than the period t.

(26) As can be seen in FIG. 2, during the time interval for routing the clock signal 100, a message 101 is sent by the first system 2 to the second system 3 and a message 102 is sent by the second system 3 to the first system 2. As can be seen in FIG. 2, the message 101 and the message 102 are sent simultaneously with the message 100. This simultaneous transmission is for example triggered by a synchronization message 103 generated by the trigger module 9. The entirety of the message 101 and the entirety of the message 102 are, in the example being considered, routed over the whole time interval for routing the clock signal 100.

(27) Thus, a communication period can be divided up into a first part during which the link simultaneously routes the clock signal 100 and the messages 101 and 102 and a second part during which no data is routed via the link 4, this second part being alternatively referred to as the inter-frame period.

(28) As shown in FIG. 2, the message 101 sent by the first system 2 comprises the primary data 105 and the secondary data 106 mentioned with reference to FIG. 1. In the example in question, the secondary data 106 is sent before the primary data 105.

(29) Again in the example in FIG. 2, the message 102 sent by the second system 3 comprises the primary data 108 and the secondary data 109 mentioned with reference to FIG. 1. In the example in question, the primary data 108 are sent before the secondary data 109.

(30) The primary data 105 and 108 each take for example the form of an atomic block having a priority level higher than that of the atomic blocks forming the secondary data 106 and 109.

(31) Each block forming the primary data 105 and 108 can end with redundancy control data, allowing it to be ensured that the entirety of the primary data has indeed been received after routing via the link 4. The block forming the secondary data 109 can also end with redundancy control data, allowing it to be ensured that the entirety of the secondary data has indeed been received after routing via the link 4. Where necessary, the block forming the secondary data 106 can also end with redundancy control data.

(32) As can be seen in the FIG. 2, the primary data 105 and 108 do not have to be routed at the same time by the link 4, the primary data 105 being routed while secondary data 109 are being routed and the primary data 108 being routed while secondary data 106 are also being routed. On the other hand, a part of the secondary data 106 may be routed via the link 4 at the same time as a part of the secondary data 109.

(33) Furthermore, as can be seen in FIG. 2, each message 101 sent by the first system 2 to the second system 3 can comprise a larger amount of secondary data 106 than of primary data 105. Similarly, each message 102 sent by the first system 2 to the second system 3 can comprise a larger amount of secondary data 109 than of primary data 108.

(34) Several steps will now be described that are carried out during a period N of communication between the first 2 and the second 3 system when it is sought to calculate duty cycle values for the electronic switches of the inverter.

(35) During a first step, an analog acquisition of the currents flowing in the phases of the stator of the electric motor 6 is carried out upon the initiative of the first system 2. This step is initiated upon a command 110 given by the trigger module 9 and takes place right at the start of the period N. During this step, the clock signal 100 and the messages 101 and 102 are routed via the link 4, after the generation at the end of the preceding period N1 of a synchronization message 103. At this stage, the message 101 is formed by the secondary data 106, whereas the message 102 is formed by the secondary data 109. These analog values of current are digitized by the converter 7, conditioned 111 by the full-duplex module 12 of the first system 2 then routed 118 during a second step in the fowl of primary data 105 via the link 4 to the second system 3.

(36) These primary data 105 are received 112 by the full-duplex module 13 of the second system 3 and sent to the generator of duty cycle values 8. This generator 8, on the basis of the data coming from the analog values of currents previously obtained, determines the duty cycle values to be applied to each electronic switch of the inverter during the following period N+1. At the end of this step, the duty cycle values thus determined are transmitted 113 to the full-duplex module 13 of the second system 3.

(37) The duty cycle values are then routed in the form of primary data 108 to the first system 2 via the link 4 upon reception of the synchronization message 103.

(38) These data 108 are received 115 by the full-duplex module 12 of the first system 2, then the first system 2 sends a command to the electronic switches of the inverter by applying to them 116, at the start of the following period N+1, the duty cycle values calculated on the basis of the currents flowing in the phases of the motor 6 during the period N.

(39) Upon examining FIG. 2, it can be observed that the exemplary method described allows the application during the period N+1 of duty cycle values calculated on the basis of the currents measured during the period N despite the return journey via the link 4 and the time for processing by the first system 2 and the second system 3.

(40) For this purpose, the following must be calibrated: a first time between the reception 115 by the full-duplex module 12 of the duty cycle values to be applied during the following period N+1 and the application 116 of these duty cycle values right at the start of said period N+1, a second time between the reception of the message 110 for acquisition of the values right at the start of each period and the start 118 of the routing of the values of current thus acquired via the link 4, and a third time combining the routing of the duty cycle values via the link 4 in the form of the primary data 108, the first time hereinabove and the second time hereinabove. This third time can correspond to the period of time during which the secondary data 106 are routed from the first system 2 to the second system 3.

(41) In the example described, each system 2 or 3 comprises a full-duplex module 12 or 13 but in examples not shown, the first system 2 and/or the second system 3 can comprise a half-duplex module responsible for the transmission of data over the link 4 and a half-duplex module responsible for the reception of data routed via the link 4

(42) The method which has just been described can allow all or part of the following advantages to be obtained: being transparent vis--vis the generator of duty cycle values, using an isolated link with a reduced number of wires carrying out acquisitions of analog current and disposing of a wide flexibility with regard to the choice of the number of electronic switches to be controlled by PWM, rendering the master system autonomous in the case of a failure, sending complementary data allowing information on the state of the systems, any errors, the temperature, etc. to be made available, verifying the integrity of the received data, exchanging data via the link without having to make use of the processor (CPU) when each of the first system and of the second system uses a microcontroller.

(43) The invention is not limited to the examples which have just been described.

(44) The expression comprising a should be understood as being synonymous with the expression comprising at least one, except where the contrary is specified.