Beam forming system having linear samplers

Abstract

A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Claims

1. A frequency conversion/time delay circuit, fed by an input signal having a frequency to be frequency converted to a converted frequency, the frequency conversion/time delay circuit, comprising: a plurality of N signal channels, where N is an integer, each one of the plurality of N signal channels being fed the input signal; a periodic signal having a period T related to the converted frequency and a duty cycle TN; and a time delay signal, each one of the plurality of N signal channels comprising: (a) a sampler fed by the input signal and responsive to the periodic signal for producing a train of sampling pulses; and (b) a controllable time delay circuit, fed by a time delay signal, for producing the train of sampling pulses in response to the periodic signal, the time delay circuit imparting a time delay to the train of sampling pulses in accordance with the time delay signal fed to the time delay circuit; wherein the train of sampling pulses in each one of the N signal channels is produced in accordance with the time delay signal fed to such one of the N signal channels, the train of sampling pulses in one of the N signal channels being delayed with respect to the train of sampling pulses in another one of the N signal channels a time T/N.

2. A frequency conversion/time delay circuit, fed by an input signal having a frequency to be frequency converted to a converted frequency, the frequency conversion circuit, comprising: (A) a plurality of N, where N is an integer, signal channels, each one of the N signal channels being fed by the input signal and a periodic signal having a period T related to the converted frequency and a duty cycle T/N; and a time delay signal, each one of the N signal channels comprising: (i) a sampler fed by the input signal and being responsive to a train of sampling pulses fed thereto; (ii) a controllable time delay circuit fed by the delay signal for producing the train of sampling pulses to the sampler in such one of the signal N channels in response to the periodic signal, the controllable time delay circuit imparting a time delay to the train of sampling pulses in accordance with the time delay signal fed to the controllable time delay circuit; and (B) wherein the train of sampling pulses in the N trains of sampling pulses produced by the controllable time delay circuit in one of the N signal channels is delayed with respect to the sampling pulses in another one of the N signal channels a time T/N in accordance with the time delay signal.

3. A frequency conversion/time delay circuit, comprising: an input port for receiving an input signal having a frequency to be frequency converted to a converted frequency; a source of a plurality of N time delay control signals, where N is an integer; a plurality of N samplers; a plurality of N controllable time delay circuits, each one of the N controllable time delay circuits being fed a corresponding one of the N time delay control signals; a source for producing a train of pulses having a period T and a duty cycle T/N, the train of pulses being fed in common to the plurality of N controllable time delay circuits; a plurality of N signal channels, where N is an integer, each one of the N signal channels being fed to the input port for carrying a corresponding portion of the input signal having the frequency to be frequency converted, each one of the signal channels having: (i) a corresponding one of the N samplers, each one of the N samplers being fed the corresponding portion of the input signal; and (ii) a corresponding one of the N controllable time delay circuits; each one of the N controllable time delay circuits delaying the train of pulses fed thereto in accordance with the one corresponding one of the N time delay control signals fed thereto, each one of the N controllable time delay circuits providing a corresponding one of N trains of sampling signals, each one of the N trains of sampling signals being fed to a corresponding one of the N samplers with each one of the sampling signals in the N trains of sampling signals having a period T and a duty cycle T/N, and with the sampling signals in one of the N trains of the sampling signals being delayed with respect to the sampling signals in another one of the N trains a time T/N.

4. A phased array antenna system, comprising: (A) a beam steering computer; (B) a plurality M, where M is an integer, of antenna elements each one being fed to a corresponding one of a plurality of M antenna ports; (C) a pulse train source, the pulses in the train having a period T, and a duty cycle T/N; (D) a plurality of M frequency conversion/variable time delay circuits, each one of the M frequency conversion/variable time delay circuits being fed to a corresponding one of the M antenna ports, each one of the M frequency conversion/variable time delay circuits, comprising: a plurality of N, where N is an integer, signal channels, each one of the N signal channels being fed to the corresponding one of the one of the M antenna ports, each one of the signal channels having: a sampler coupled to said corresponding one of the one of the M antenna ports and responsive to sampling signals fed thereto; a controllable time delay circuit for producing the train of sampling signals to the sampler in such one of the signal channels in response to a train of pulses fed to the controllable time delay circuit in such one of the signal channels, the controllable time delay circuit imparting a time delay to the pulses in the train of pulses fed to the controllable time delay circuit in such one of the signal channels in accordance with a time delay command signal fed to the controllable time delay circuit by the beam seeing computer; and (E) wherein each one of the sampling signals in the N trains of sampling signals are produced by the controllable time delay circuit in each one of the channels with a period T and a duty cycle T/N with the sampling signals in one of the N trains of the sampling signals being delayed with respect to the sampling signals in another one of the N trains of sampling signals a time T/N.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram of a Radio Frequency beam forming system for a phased array antenna system according to the PRIOR ART;

(2) FIGS. 2A-2C are a schematic diagram and timing diagrams of a version of an RF Sampler architecture according to the PRIOR ART;

(3) FIG. 3 is a block diagram of a phased array antenna system having a hewn forming network and frequency conversion/time delay sections according to the disclosure;

(4) FIG. 4 is a block diagram of an exemplary one of the down conversion/time delay sections used in the phased array antenna system of FIG. 3 according to the disclosure;

(5) FIGS. 5A and 5B are timing diagrams used in the down conversion/time delay sections of FIGS. 3 and 4 according to the disclosure;

(6) FIG. 6 is a block diagram of a testing arrangement for generating calibration factors used by a beam steering computer phased array antenna system of FIG. 3 in generating correction factors used by the beam steering computer in generating time delays for the down conversion/time delay sections according to the disclosure;

(7) FIG. 7 is a flow chart of a process used by the testing arrangement of FIG. 6 in generating the correction factors according to the disclosure; and

(8) FIG. 8 is a semiconductor arrangement for an exemplary one of the frequency conversion/time delay sections of FIG. 4 according to the disclosure.

(9) Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

(10) Referring now to FIG. 3, a phased array antenna 10 is shown, having an array 12 of, M, where M is an integer, antenna elements 14.sub.1-14.sub.M. Each one of the antenna elements 14.sub.1-14.sub.M is coupled to a corresponding one of a plurality of antenna ports 16.sub.1-16.sub.M of a corresponding M down conversion/time delay sections 18.sub.1-18.sub.M, as shown. Each one of the M down conversion/time delay sections 18.sub.1-18.sub.M, is identical in construction, an exemplary one thereof, here down conversion/time delay sections 18.sub.1 being shown in detail in FIG. 4. Each one of the down conversion/time delay sections 18.sub.1-18.sub.M is fed a common local oscillator (LO) signal from LO source 20 on line 22, here a train of pulses having a period T and a duty cycle 25 percent duty cycle. Each one of the down conversion/time delay shifter sections 18.sub.1-18.sub.M: (1) converts the RF signal received at the antenna ports 14.sub.1-14.sub.M, respectively, to a pair of differential baseband signals; one differential pair being a (+) in-phase signal and a () in-phase signal and the other differential pair being a (+) quadrature signal and () quadrature signal; and (2) provide a time delay to the signals passing through the down conversion/time delay sections 18.sub.1-18.sub.M, respectively, selectively in accordance with a set of time delay signals fed to each one of the down conversion/time delay sections 18.sub.1-18.sub.M by a beam steering computer (BSC) 24, as shown. The (+) in-phase signal from the plurality of down conversion/time delay sections are fed, as shown in FIG. 3, to a first capacitor C1; the () in-phase signal from the plurality of down conversion/time delay sections are fed to a first capacitor C2; the (+) quadrature signal from the plurality of down conversion/time delay sections are fed to a first capacitor C3; the () quadrature signal from the plurality of down conversion/time delay sections are fed to a first capacitor C4; as shown, Thus, the four channels may be referred to as: a (+) in-phase signal channel (herein sometimes also referred to as CHANNEL A); a (+) quadrature signal channel (herein sometimes also referred to as CHANNEL B); a () in-phase signal channel (herein sometimes also referred to as CHANNEL C); and, a () quadrature signal channel (herein sometimes also referred to as CHANNEL A). The outputs of the capacitors C1-C4 are fed to a baseband receiver 19, as shown.

(11) Referring now in more detail to FIG. 4, an exemplary one of the M down conversion/time delay sections 18.sub.1-18.sub.M, here down conversion/time delay sections 18.sub.1 is shown to include: a plurality of N, where N is an integer, here for example, 4, signal channels (CHANNELS A-D) all having inputs connected the antenna port 16.sub.1 of the down conversion/time delay section 18.sub.1, as shown. Each one of the signal channels, CHANNEL A-D, is identical in construction and includes sampler/time delay sections 25a-25d, respectively, each, one of the sampler/time delay sections 25a-25d including: a sampler 26a-26d, respectively, here a field effect transistor (FET) having a gate electrode fed by a train of sampling signals on line 28 (shown in FIG. 5A); such train of sampling signals on lines 28a-28d being produced by a variable time delay 30a-30d, respectively, as shown. It is noted that all 4 time delays 30a-30d are fed the same LO train of pulses fed to the down conversion/time delay section 18.sub.1 on line 22. It is also noted that, referring to FIG. 3, the same LO train of pulses is fed to all M down conversion/time delay section 18.sub.1-18.sub.M through line 22. The time delay provided by the time delays 30a-30d is controlled by a time delay control signal fed to the time delays 30a-30d by the by the beam steering computer BSC 24, as shown. It is noted that each one of the 4 time delays 30a-30d is fed a corresponding one of the 4 time delay control signals by the BSC 24, as shown. It is also noted that a different set of 4 time delay control signals is fed to a different one of the M down conversion/time delay sections 18.sub.1-18.sub.M, as shown in FIG. 3.

(12) More particularly, as shown in FIG. 5A, the LO train of pulses on line 22 (FIG. 3) has a period T and a duty cycle, T/N, here T/4. It is noted that each one of the N trains of sampling signals produced by the time delays 30a-30d in each one of the four channels, respectively, has the period T and the duty cycle T/N. It is also noted that the sampling signals on line 28a in one of the N trains of the sampling signals is delayed with respect to the sampling signals in another one of the N trains the sampling signals a time T/N. More particularly, the train of sampling signals on line 28a fed to the sampler 26a in the (+) quadrature signal channel is delayed in time T/4 with respect to the train of sampling signals on line 28b fed to the sampler 26b in the (+) in-phase sisal channel; the train of sampling signals on line 28b fed to the sampler 26b in the () in-phase signal channel is delayed in time T/4 with respect to the train of sampling signals on line 28c fed to the sampler 26c in the (+) quadrature signal channel; and the train of sampling signals on line 28c fed to the sampler 26c in the () quadrature signal channel is delayed in time T/4 with respect to the train of sampling signals on line 28d fed to the sampler 26d in the () quadrature signal channel.

(13) It is noted that when the beam steering computer 24 directs a beam on boresight, the train of sampling pulses on line 28a in the (+) in-phase channels of all of the down conversion/time delay sections 18.sub.1-18.sub.M are in-phase; however, if the beam steering computer 24 wishes to direct a beam an angle from boresight, the beam steering computer 24 produces time delay signals to the time delays 30a-30d in the M frequency conversion/time delay sections 18.sub.1-18.sub.M to delay the train of sampling pulses in the (+) in-phase channels an amount , as shown in FIG. 5B, determined by a calibration procedure to be described. It is noted that the time delays in the produced in the other channels maintains the relationship described above: the train of sampling signals on line 28a fed to the sampler 26b in the (+) quadrature signal channel is delayed in time T/4 with respect to the train of sampling signals on line 28a fed to the sampler 26a in the (+) in-phase signal channel; the train of sampling signals on line 26c fed to the sampler 26c in the () in-phase signal channel is delayed in time T/4 with respect to the train of sampling signals fed to the sampler 26b in the (+) quadrature signal channel; and the train of sampling signals on line 28c fed to the sampler 26c in the () quadrature signal channel is delayed in time T/4 with respect to the train of sampling signals on line 28d fed to the sampler 26d in the () quadrature signal channel.

(14) Referring now to FIG. 6, block diagram is shown of a testing arrangement for generating calibration factors used by the beam steering computer 24 in generating correction factors used by the beam steering computer in generating time delays for the time delays 30a-30d to in turn enable the time delays 30a-30d to produce the trains of sampling signal on lines 28a-28d described above in connection with FIGS. 5A and 5B.

(15) The testing arrangement includes an RF source 31. The output of the RF source 31 is fed to the (+) in-phase and () in phase channels (CHANNELS A and C) of the M down conversion sections/time delay sections 18.sub.1-18.sub.M and to the RF source is fed, after passing through a ninety degree phase shifter 32, to the (+) quadrature channel and () quadrature channels (CHANNELS B and D) of the M down conversion sections/time delay sections 18.sub.1-18.sub.M, as shown. The outputs of the (+) in-phase and () in phase channels (CHANNELS A and B) of the M down conversion sections/time delay sections 18.sub.1-18.sub.M are selectively coupled, through switch sections 36.sub.1-36.sub.M, respectively, to capacitors C.sub.1 and C.sub.2, respectively, as shown. The capacitors C.sub.1 and C.sub.2 are coupled to a first power sensor 38.sub.1, as shown, and the quadrature channel and () quadrature channels of the M down conversion sections/time delay sections 18.sub.1-18.sub.M are selectively coupled, through switch sections 36.sub.1-36.sub.M, respectively, to capacitors C.sub.3 and C.sub.4, respectively, as shown. The capacitors C.sub.3 and C.sub.24 are coupled to a second power sensor 38.sub.2, as shown.

(16) The power sensors 38.sub.1, 38.sub.2 are coupled to a processor 40. The processor 40 operates the switch sections 36.sub.1-36.sub.M and determines calibration, or correction factors .sub.A.sub._.sub.C and .sub.B.sub._.sub.D for each one of the M down conversion/time delay sections 18.sub.1-18.sub.M sequentially in a manner to be described in connection with FIG. 7. Suffice it to say here that the determined correction factors .sub.A.sub._.sub.C and .sub.B.sub._.sub.D for each one of the M down conversion/time delay sections 18.sub.1-18.sub.M are sequentially stored in a memory 42 in the beam steering computer 24 and are used by the beam steering computer 24 in generating the time delay control signals for the variable time delay 30a-30d of samplers 26a-26d during normal beam forming operation of the system 10 shown in FIG. 3.

(17) Referring now to FIG. 7, the local oscillator 20 produces a 25 percent duty cycle pulse train to the variable time delays 30a-30d in all four down converter/time delay channels (CHANNELS A-D) in one of the M frequency conversion/time delay sections 18.sub.1-18.sub.M. (Step 700). The in-phase RF signal produced by the RF source 31 is fed to CHANNELS A AND C of selected one of the M down converter/time delay sections 18.sub.1-18.sub.M (Step 701) and at the same time, the RF signal shifted in phase 90 degrees by the phase shifter 32 is fed to CHANNELS B AND D of the same selected one of the M down converter/time delay sections 18.sub.1-18.sub.M (Step 702).

(18) Two processes, PROCESS A and PROCESS B described below, here, in this example, now are performed to determine simultaneously the calibration, or correction factors .sub.A.sub._.sub.C and .sub.B.sub._.sub.D for each one of the M down conversion/time delay sections 18.sub.1-18.sub.M:

Process A

(19) The beam steering computer 24 applies a one half period time delay T/2 to the time delay 30c in CHANNEL C of the selected down converter/time delay sections 18.sub.1-18.sub.M (Step 703). The beam steering computer 24 varies the one half period time delay provided to the time delay 30c relative to the pulse train applied to the time delay 30a of CHANNEL A while measuring the power sensor 38.sub.1 fed by CHANNELS A AND C to determine the relative time delay .sub.A.sub._.sub.C producing the maximum power output (Step 705). The calibration factors .sub.A.sub._.sub.C are stored in the memory 42 of the beam steering computer 24 (Step 707).

Process B

(20) The beam steering computer 24 applies quarter time period delay (T/4) to the time delay 308b in CHANNEL B, and three-quarter period time delay (3T/4) to the time delay 30d in CHANNEL D of the selected down converter/time delay sections 18.sub.1-18.sub.M (Step 704). The beam steering computer 24 varies the three-quarter period time delay in the pulse train fed to the time delay 30d relative to the one-quarter period time delay (T/4) provided to the time delay 30b of CHANNEL B while measuring the power in power sensor 38.sub.2 fed by CHANNELS B AND D to determine the relative time delay .sub.B.sub._.sub.D producing the maximum power output (Step 706). The calibration factors .sub.B.sub._.sub.D are stored in the memory 42 of the beam steering computer 24 (Step 708).

(21) The processes A and B continue until the calibration factors .sub.A.sub._.sub.C and .sub.B.sub._.sub.D have been determined for all M frequency conversion/time delay sections 18.sub.1-18.sub.M (Step 710).

(22) Next, the entire phased array system 10 is calibrated to determine the time delay commands for the time delays 30a-30d of the M frequency conversion/time delay sections 18.sub.1-18.sub.M to thereby produce proper beam angles for the phased array antenna system. For example, if R-bit, where R is an integer, time delays are used, 2.sup.R beam angles may be produced in response to a corresponding one of 2.sup.R sets of four time delays provided to time delays in the four channels (CHANNELS A, B, C and D) of each one of the M frequency conversion/time delay sections.

(23) To calibrate each frequency conversion/time delay section for each of the 2.sup.R sets of four time delays, the calibration process described earlier and summarized in FIG. 7 is performed with the RF source (31) set to phase increments corresponding with 360/2.sup.R degrees. For example, the 0 degree case will set the phase of the RF source to be locked to the LO source (22) and the calibration procedure is performed to determine the calibration values and these values are then stored in memory. The RF source (31) is then advanced by 360/2.sup.R degrees (if R=5, this would be 11.25 degrees) relative to the LO source (22). The calibration procedure is then performed for this phase setting. This process continues for all 2.sup.R phase states, and then for all M frequency conversion/time delay sections. After calibration settings are stored in memory for all 2.sup.R phase states for all M frequency conversion/time delay sections, the system is now calibrated for all desired beam positions where the particular beam position is determined by the relative time delay between all M frequency conversion/time delay sections in accordance with the standard relationship between the relative phase of each antenna element in a phased array and the resulting far-field beam pattern.

(24) Next, referring to FIG. 8, a semiconductor arrangement 800 is shown for an exemplary one of the M frequency conversion/time delay sections, here section 18.sub.1. The section includes: a column III-V (for example Gallium Arsenide (GaAs or Gallium Nitride (GaN)) semiconductor 802 having formed therein four of the Field Effect Transistors (FETs) switches 26-26d (samplers) having the source electrodes (S) fed by the RF, as shown; the gates G fed by the sampling signals on lines 28a-28d, respectively, as shown; and a column IV (or example silicon) semiconductor 804 having analog signal processing circuitry, including the four capacitors C.sub.1-C.sub.4, coupled to the drain electrodes (D) of the FET switches 26a-26d, respectively, as shown, the four variable time delays 30a-30d, and the LO generator 20 for generating trains of pulses for the four variable time delays 30a-30d. A low parasitic interface between the LO generation circuitry and the switches may be achieved through either heterogeneous or nearly-heterogeneous III-V/IV packaging techniques described above (the iUHD technology or the Redistributed Chip Packaging (RCP)) technology or by resonating out the bondwire parasitic with passive components on the III-V die. More particularly, the III-V semiconductor 802 may have a circuit 803 of passive elements, such as inductor and capacitor C, as shown, arranged to tune out (remove) any parasitics associated with the switches 26a-26d in order to achieve a 50 ohm impedance match over the band of interest. It should be understood that other combination of parallel/series passive elements may be used if required.

(25) The variable time delay circuits 30a-30d may include, for example, a conventional Digitally Controlled Delay Line or a conventional Voltage Controlled Delay Line (VCDL) along with a conventional digital-to-analog converter (DAC). The VCDL is a serial combination of inverters with a supply voltage on several of the inverters is connected to a control voltage instead of the nominal supply voltage. As this control voltage is reduced, the delay through the VCDL circuit is increased. A simple DC DAC is used to produce the control voltage based on digital commands supplied by the beam steering computer 24, as described above. The DVDL may include, for example, R inverters chained together, with the 1st and Rth inverter powered with the nominal supply voltage and the other internal inverters powered by the control voltage. The control voltage is supplied by a DAC (one DAC per VCDL, where each VCDL may contain some number of inverters).

(26) The arrangement 800 may be formed on a common substrate having both III-V and IV, as described in U.S. Pat. No. 7,994,550, entitled Semiconductor structures having both elemental and compound semiconductor devices on a common substrate, inventors, Kaper, et al., assigned to the same assignee as the present patent application, or on two different substrates; one of III-V and the other of IV.

(27) A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, a plurality of the M RF samplers may coexist on the same III-V and IV die, where portions of the IV baseband circuitry and LO generation circuitry can be shared. Accordingly; other embodiments are within the scope of the following claims.