Resin-sealed semiconductor device and method of manufacturing resin-sealed semiconductor device

Abstract

A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-type semiconductor element 100, wherein the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer. The resin-sealed semiconductor device of the present invention can acquire higher resistance to a reverse bias at a high temperature than a conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the present invention has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device.

Claims

1. A resin-sealed semiconductor device comprising: a mesa-type semiconductor element which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin which seals the mesa-type semiconductor element, wherein the mesa-type semiconductor element includes, as the glass layer, a glass layer which is formed by baking a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state, the glass layer is formed using a glass composition which substantially contains none of Pb, P, As, Sb, Li, Na and K, the glass composition contains at least SiO.sub.2, Al.sub.2O.sub.3, an oxide of alkaline earth metal, and the glass composition can be baked at 1100 C. or below, and (i) the content of SiO.sub.2 falls within a range of 53 mol % to 73 mol %, the content of Al.sub.2O.sub.3 falls within a range of 11 mol % to 21 mol %, a content of CaO falls within a range of 3 mol % to 9 mol %, a content of MgO falls within a range of 11 mol % to 21 mol %, the content of nickel oxide falls within a range of 0.01 mol % to 3 mol %, or, (ii) the content of SiO.sub.2 falls within a range of 32 mol % to 48 mol %, the content of Al.sub.2O.sub.3 falls within a range of 9 mol % to 13 mol %, the content of CaO falls within a range of 15 mol % to 23 mol %, a content of ZnO falls within a range of 18 mol % to 28 mol %, a content of B.sub.2O.sub.3 falls within a range of 3 mol % to 10 mol %, the content of nickel oxide falls within a range of 0.01 mol % to 3 mol %.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A to FIG. 1C are views for explaining a resin-sealed semiconductor device of an embodiment 1;

(2) FIG. 2 is a view for explaining a mesa-type semiconductor element of the embodiment 1;

(3) FIG. 3A and FIG. 3B are views for explaining an advantageous effect of the resin-sealed semiconductor device of the embodiment 1;

(4) FIG. 4A to FIG. 4D are views for explaining a method of manufacturing a resin-sealed semiconductor device of the embodiment 1;

(5) FIG. 5A to FIG. 5D are views for explaining the method of manufacturing a resin-sealed semiconductor device of the embodiment 1;

(6) FIG. 6 is a view for explaining a mesa-type semiconductor element of an embodiment 2;

(7) FIG. 7A to FIG. 7D are views for explaining a method of manufacturing a resin-sealed semiconductor device of the embodiment 2;

(8) FIG. 8A to FIG. 8D are views for explaining a method of manufacturing a resin-sealed semiconductor device of the embodiment 2;

(9) FIG. 9 is a table showing conditions and results of examples;

(10) FIG. 10A and FIG. 10B are views for explaining bubbles generated in the inside of a glass layer in a preliminary evaluation.

(11) FIG. 11A and FIG. 11B are photographs for explaining bubbles generated in the inside of a glass layer in a subsequent evaluation.

(12) FIG. 12 is a graph showing the result of a high-temperature reverse bias test.

(13) FIG. 13 is a view for explaining a mesa-type semiconductor element according to a modification.

(14) FIG. 14 is a view for explaining a conventional mesa-type semiconductor element.

MODE FOR CARRYING OUT THE INVENTION

(15) Hereinafter, a resin-sealed semiconductor device, and a method of manufacturing a resin-sealed semiconductor device according to the present invention are explained in conjunction with embodiments shown in the drawings.

Embodiment 1

1. Resin-Sealed Semiconductor Device

(16) FIG. 1A to FIG. 1C are views for explaining a resin-sealed semiconductor device 10 of an embodiment 1. FIG. 1A is a perspective view of the resin-sealed semiconductor device 10, FIG. 1B is a plan view of the resin-sealed semiconductor device 10 in a state where a resin is removed from the resin-sealed semiconductor device 10, and FIG. 1C is a side view of the resin-sealed semiconductor device 10 in a state where a resin is removed from the resin-sealed semiconductor device 10.

(17) FIG. 2 is a view for explaining a mesa-type semiconductor element 100 of the embodiment 1.

(18) The resin-sealed semiconductor device 10 of the embodiment 1 includes, as shown in FIG. 1, the mesa-type semiconductor element 100, and a molding resin 40 which seals the mesa-type semiconductor element 100. The mesa-type semiconductor element 100 is mounted on a die pad 23 of a lead frame 20 which is constituted of a lead 21, a lead 22 and the die pad 23. One electrode of the mesa-type semiconductor element 100 is connected to the lead 21 via the die pad 23, and the other electrode of the mesa-type semiconductor element 100 is connected to the lead 22 via a gold wire 30.

(19) As shown in FIG. 2, the mesa-type semiconductor element 100 includes a mesa-type semiconductor base body 108 having a pn-junction exposure portion C in an outer peripheral tapered region B which surrounds a mesa region A, and a glass layer 124 which covers at least the outer peripheral tapered region B. The outer peripheral tapered region B is directly covered with the glass layer 124.

(20) The mesa-type semiconductor base body 108 includes an n.sup.-type semiconductor layer 110, a p.sup.+-type semiconductor layer 112 which is formed by diffusion of a p-type impurity from one surface of the n.sup.-type semiconductor layer 110, and an n.sup.+-type semiconductor layer 114 which is formed by diffusion of an n-type impurity from the other surface of the n.sup.-type semiconductor layer 110. The mesa-type semiconductor element 100 is a pn diode. In FIG. 2, symbol 134 indicates an anode electrode layer, and symbol 136 indicates a cathode electrode layer.

(21) The resin-sealed semiconductor device 10 of the embodiment 1 is characterized in that the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer 124. Such a glass layer may be formed using a glass composition which substantially contains none of Pb, As, Sb, Li, Na and K. As such a glass composition, a glass composition which substantially contains none of Pb, P, As, Sb, Li, Na and K (see Claim 5), and a glass composition which substantially contains none of Pb, B, P, As, Sb, Li, Na and K (see Claim 9) can preferably be exemplified.

(22) The glass composition of the former case may be (1) a glass composition which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, (2) a glass composition which contains at least SiO.sub.2, Al.sub.2O.sub.3, ZnO, CaO, and 3 mol % to 10 mol % of B.sub.2O.sub.3, or (3) a glass composition which contains at least SiO.sub.2, Al.sub.2O.sub.3, an oxide of alkaline earth metal, and at least one metal oxide selected from a group consisting of nickel oxide, copper oxide, manganese oxide, and zirconium oxide.

(23) The glass composition of the latter case may be (4) a glass composition which contains at least SiO.sub.2, Al.sub.2O.sub.3, MgO and CaO, or (5) a glass composition which contains at least SiO.sub.2, Al.sub.2O.sub.3 and ZnO.

(24) In this case, to contain some specific components means not only the case where the glass composition contains only such specific components but also the case where the glass composition further contains other components which can be usually contained in the glass composition besides such specific components. Further, to substantially contain no specific element means that the glass composition contains no any such specific element as the component, and does not exclude the glass composition in which the above-mentioned specific element is mixed as an impurity in the raw materials which constitute respective components of glass. Further, to contain no specific element also means that the glass composition contains no oxide of the specific element, no nitride of the specific element or the like.

(25) Out of these glass compositions, as the glass composition described in (1), it is possible to use, for example, a glass composition where the content of SiO.sub.2 falls within a range of 41.1 mol % to 61.1 mol %, the content of B.sub.2O.sub.3 falls within a range of 5.8 mol % to 15.8 mol %, the content of Al.sub.2O.sub.3 falls within a range of 7.4 mol % to 17.4 mol %, the content of ZnO falls within a range of 3.0 mol % to 24.8 mol %, the content of the oxide of alkaline earth metal falls within a range of 5.5 mol % to 15.5 mol %, and the content of nickel oxide falls within a range of 0.01 mol % to 3.0 mol %.

(26) In this case, it is possible to use a glass composition where, as the oxides of alkaline earth metals, the content of CaO falls within a range of 2.8 mol % to 7.8 mol %, the content of MgO falls within a range of 1.1 mol % to 3.1 mol %, and the content of BaO falls within a range of 1.7 mol % to 4.7 mol %.

(27) It is also possible to use a glass composition where, as the oxides of alkaline earth metals, the content of CaO falls within a range of 3.8 mol % to 10.9 mol %, and the content of MgO falls within a range of 1.7 mol % to 4.7 mol %.

(28) It is also possible to use a glass composition where, as the oxides of alkaline earth metals, the content of CaO falls within a range of 3.3 mol % to 9.3 mol %, and the content of BaO falls within a range of 2.2 mol % to 6.2 mol %.

(29) It is also possible to use a glass composition where, as the oxides of alkaline earth metals, the content of MgO falls within a range of 2.2 mol % to 6.2 mol %, and the content of BaO falls within a range of 3.3 mol % to 9.3 mol %.

(30) It is also possible to use a glass composition which contains no nickel oxide.

(31) As the glass composition described in (2), it is possible to use, for example, a glass composition where the content of SiO.sub.2 falls within a range of 32 mol % to 48 mol % (for example, 40 mol %), the content of Al.sub.2O.sub.3 falls within a range of 9 mol % to 13 mol % (for example, 11 mol %), the content of ZnO falls within a range of 18 mol % to 28 mol % (for example, 23 mol %), the content of CaO falls within a range of 15 mol % to 23 mol % (for example, 19 mol %), and the content of B.sub.2O.sub.3 falls within a range of 3 mol % to 10 mol % (for example, 7 mol %).

(32) As the glass composition described in (3), it is possible to use, for example, a glass composition where the content of SiO.sub.2 falls within a range of 53 mol % to 73 mol % (for example, 62.6 mol %), the content of Al.sub.2O.sub.3 falls within a range of 11 mol % to 21 mol % (for example, 15.3 mol %), the content of CaO falls within a range of 3 mol % to 9 mol % (for example, 5.5 mol %), the content of MgO falls within a range of 11 mol % to 21 mol % (for example, 15.6 mol %), and the content of nickel oxide falls within a range of 0.01 mol % to 3 mol % (for example, 1 mol %).

(33) It is also possible to use a glass composition where the content of SiO.sub.2 falls within a range of 32 mol % to 48 mol % (for example, 39.6 mol %), the content of Al.sub.2O.sub.3 falls within a range of 9 mol % to 13 mol % (for example, 10.9 mol %), the content of CaO falls within a range of 15 mol % to 23 mol % (for example, 18.8 mol %), the content of ZnO falls within a range of 18 mol % to 28 mol % (for example, 22.8 mol %), the content of B.sub.2O.sub.3 falls within a range of 3 mol % to 10 mol % (for example, 6.9 mol %), the content of nickel oxide falls within a range of 0.01 mol % to 3 mol % (for example, 1 mol %).

(34) As the glass composition described in (4), it is possible to use, for example, a glass composition where the content of SiO.sub.2 falls within a range of 53 mol % to 73 mol % (for example, 63.2 mol %), the content of Al.sub.2O.sub.3 falls within a range of 11 mol % to 21 mol % (for example, 15.5 mol %), the content of MgO falls within a range of 11 mol % to 21 mol % (for example, 15.7 mol %), and the content of CaO falls within a range of 3 mol % to 6 mol % (for example, 5.6 mol %).

(35) Further, as the glass composition described in (5), it is possible to use, for example, a glass composition where the content of SiO.sub.2 falls within a range of 40 mol % to 60 mol % (for example, 50 mol %), the content of Al.sub.2O.sub.3 falls within a range of 5 mol % to 15 mol % (for example, 10 mol %), and the content of ZnO falls within a range of 30 mol % to 50 mol % (for example, 40 mol %).

2. Advantageous Effect of Resin-Sealed Semiconductor Device

(36) FIG. 3A and FIG. 3B are views for explaining an advantageous effect of the resin-sealed semiconductor device 10 of the embodiment 1. FIG. 3A is a view showing a state where a reverse voltage is applied to the resin-sealed semiconductor device 10 of the embodiment 1, and FIG. 3B is a view showing a state where a reverse voltage is applied to a resin-sealed semiconductor device of a comparison example. In FIG. 3A and FIG. 3B, a broken line indicates a distal end portion of a depletion layer. The resin-sealed semiconductor device of the comparison example is a resin-sealed semiconductor device formed by molding a conventional mesa-type semiconductor element 900 with a resin. In FIG. 3B, AFTER BT TEST means after a high-temperature reverse bias test.

(37) According to the resin-sealed semiconductor device 10 of the embodiment 1, the mesa-type semiconductor element 100 includes a glass layer made of lead-free glass (glass which contains no Pb) having a lower dielectric constant than lead-containing glass as the glass layer 124 and hence, there exists no possibility that ions of high concentration are induced on an interface between a molded resin and the glass layer as well as on an interface between the glass layer and a semiconductor layer in the midst of performing a high-temperature reverse bias test (see FIG. 3A) different from the case of the resin-sealed semiconductor device of the comparison example (see FIG. 3B). As a result, an amount of a leakage current which is increased during the high-temperature reverse bias test can be decreased compared to the prior art.

(38) As a result, the resin-sealed semiconductor device 10 of the embodiment 1 can acquire higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device 10 of the embodiment 1 has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device. That is, the resin-sealed semiconductor device 10 of the embodiment 1 is the resin-sealed semiconductor device having higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device while being the resin-sealed semiconductor device which is manufactured by molding the mesa-type semiconductor element with a resin.

3. Method of Manufacturing Resin-Sealed Semiconductor Device

(39) The resin-sealed semiconductor device 10 of the embodiment 1 can be manufactured by the following method (method of manufacturing a resin-sealed semiconductor device of the embodiment 1).

(40) FIG. 4A to FIG. 4D and FIG. 5A to FIG. 5D are views for explaining the method of manufacturing a resin-sealed semiconductor device of the embodiment 1. That is, FIG. 4A to FIG. 4D and FIG. 5A to FIG. 5D are views showing respective steps of the method of manufacturing a resin-sealed semiconductor device.

(41) In the method of manufacturing a resin-sealed semiconductor device of the embodiment 1, as shown in FIG. 4A to FIG. 4D and FIG. 5A to FIG. 5D, semiconductor substrate preparing step, trench forming step, glass layer forming step, photoresist forming step, oxide film removing step, roughened surface region forming step, electrode forming step, semiconductor substrate cutting step, and resin sealing step are performed in this order. Hereinafter, the method of manufacturing a resin-sealed semiconductor device of the embodiment 1 is explained in the order of these steps.

(42) (a) Semiconductor Substrate Preparing Step

(43) Firstly, a p.sup.+-type semiconductor layer 112 is formed by diffusion of a p-type impurity from one surface of an n.sup.-type semiconductor substrate (n.sup.-type silicon substrate) 110, and an n.sup.+-type semiconductor layer 114 is formed by diffusion of an n-type impurity from the other surface of the n.sup.-type semiconductor substrate 110 thus forming a semiconductor substrate in which a pn junction arranged parallel to a main surface of the semiconductor substrate is formed. Thereafter, oxide films 116, 118 are formed by thermal oxidation on a surface of the p.sup.+-type semiconductor layer 112 and a surface of the n.sup.+-type semiconductor layer 114 respectively (see FIG. 4A).

(44) (b) Trench Forming Step

(45) Next, predetermined opening portions are formed on the oxide film 116 at predetermined positions by photo etching. After etching the oxide film, subsequently, the semiconductor substrate is etched thus forming trenches 120 having a depth exceeding the pn junction from one surface of the semiconductor substrate (see FIG. 4B).

(46) (c) Glass Layer Forming Step

(47) Next, a layer made of the glass composition is formed on inner surfaces of the trenches 120 and a surface of the semiconductor substrate in the vicinity of the trenches 120 by an electrophoresis method, and the layer made of the glass composition is baked so that the glass layer 124 for passivation is formed on the inner surfaces of the trenches 120 and the surface of the semiconductor substrate in the vicinity of the trenches 120 (see FIG. 4C). Accordingly, the pn junction exposure portion in the inside of the trench 120 is brought into a state where the pn junction exposure portion is directly covered with the glass layer 124. As the glass composition, various glass compositions which substantially contain no Pb can be used as described above.

(48) (d) Photoresist Forming Step

(49) Next, a photoresist 126 is formed such that the photoresist 126 covers a surface of the glass layer 124 (see FIG. 4D).

(50) (e) Oxide Film Removing Step

(51) Next, the oxide film 116 is etched using the photoresist 126 as a mask so that the oxide film 116 at a position 130 where an Ni plating electrode film is to be formed is removed (see FIG. 5A).

(52) (f) Roughened Surface Region Forming Step

(53) Next, a surface of the semiconductor base body at the position 130 where the Ni-plating electrode film is to be formed is subjected to surface roughening treatment thus forming a roughened surface region 132 for enhancing adhesiveness between an Ni plating electrode and the semiconductor substrate (see FIG. 5B).

(54) (g) Electrode Forming Step

(55) Next, Ni plating is applied to the semiconductor substrate thus forming an anode electrode 134 on the roughened surface region 132 and forming a cathode electrode 136 on the other surface of the semiconductor substrate (see FIG. 5C).

(56) (h) Semiconductor Substrate Cutting Step

(57) Next, the semiconductor substrate is cut by dicing or the like at a center portion of the glass layer 124 thus dividing the semiconductor substrate into chips whereby mesa-type semiconductor elements (pn diodes) 100 are manufactured (see FIG. 5D).

(58) (i) Resin Sealing Step

(59) Next, the mesa-type semiconductor element 100 is mounted on a die pad 23 of a lead frame not shown in the drawing (see FIG. 1). One electrode of the mesa-type semiconductor element 100 and a lead 21 are connected to each other, while the other electrode of the mesa-type semiconductor element 100 and a lead 22 are connected to each other by a gold wire 30. Then, these parts are arranged in a resin sealing die not shown in the drawing and, thereafter, a molding resin is injected into the inside of the die and is cured thus manufacturing a resin-sealed semiconductor device. The resin-sealed semiconductor device 10 of the embodiment 1 can be obtained by taking out the resin-sealed semiconductor device from the die.

(60) Through the above-mentioned steps, the resin-sealed semiconductor device 10 of the embodiment 1 can be manufactured.

Embodiment 2

(61) FIG. 6 is a view for explaining a mesa-type semiconductor element 102 of an embodiment 2.

(62) A resin-sealed semiconductor device of the embodiment basically has the substantially same constitution as the resin-sealed semiconductor device 10 of the embodiment 1. However, the resin-sealed semiconductor device of the embodiment 2 differs from the resin-sealed semiconductor device 10 of the embodiment 1 with respect to the constitution of the mesa-type semiconductor element. That is, in the mesa-type semiconductor element 102 of the embodiment 2, as shown in FIG. 6, an outer peripheral tapered region B is covered with a glass layer 124 with an insulation layer 121 interposed therebetween.

(63) As described above, the resin-sealed semiconductor device of the embodiment 2 differs from the resin-sealed semiconductor device 10 of the embodiment 1 with respect to the constitution of the mesa-type semiconductor element. However, in the same manner as the resin-sealed semiconductor device 10 of the embodiment 1, the mesa-type semiconductor element 102 includes a glass layer made of lead-free glass (glass which contains no Pb) having a lower dielectric constant than lead-containing glass as the glass layer 124 and hence, there exists no possibility that ions of high concentration are induced on an interface between a molded resin and the glass layer as well as on an interface between the glass layer and a semiconductor layer in the midst of performing a high-temperature reverse bias test whereby, as a result, a leakage current which is increased during the high-temperature reverse bias test can be decreased compared to the prior art.

(64) As a result, the resin-sealed semiconductor device of the embodiment 2 can acquire higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the embodiment 2 has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device. That is, the resin-sealed semiconductor device of the embodiment 2 is the resin-sealed semiconductor device having higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device while being the resin-sealed semiconductor device which is manufactured by molding the mesa-type semiconductor element with a resin.

(65) According to the resin-sealed semiconductor device of the embodiment 2, the outer peripheral tapered region B is covered with the glass layer 124 with the insulation layer 121 interposed therebetween. Accordingly, it is also possible to acquire an advantageous effect that bubbles are hardly generated in a sintering step and an advantageous effect that a reverse leakage current in the resin-sealed semiconductor device can be further decreased.

(66) The resin-sealed semiconductor device of the embodiment 2 can be manufactured by the following method (method of manufacturing a resin-sealed semiconductor device of the embodiment 2).

(67) FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8D are views for explaining the method of manufacturing a resin-sealed semiconductor device of the embodiment 2. That is, FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8D are views showing respective steps of the method of manufacturing a resin-sealed semiconductor device.

(68) In the method of manufacturing a resin-sealed semiconductor device of the embodiment 2, as shown in FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8D, semiconductor substrate preparing step, trench forming step, insulation layer forming step, glass layer forming step, photoresist forming step, oxide film removing step, roughened surface region forming step, electrode forming step, semiconductor substrate cutting step, and resin sealing step are performed in this order. Hereinafter, the method of manufacturing a resin-sealed semiconductor device of the embodiment 2 is explained in the order of these steps.

(69) (a) Semiconductor Substrate Preparing Step

(70) Firstly, a p.sup.+-type semiconductor layer 112 is formed by diffusion of a p-type impurity from one surface of an n.sup.-type semiconductor substrate (n.sup.-type silicon substrate) 110, and an n.sup.+-type semiconductor layer 114 is formed by diffusion of an n-type impurity from the other surface of the n.sup.-type semiconductor substrate 110 thus forming a semiconductor substrate in which a pn junction arranged parallel to a main surface of the semiconductor substrate is formed. Thereafter, oxide films 116, 118 are formed by thermal oxidation on a surface of the p.sup.+-type semiconductor layer 112 and a surface of the n.sup.+-type semiconductor layer 114 respectively.

(71) (b) Trench Forming Step

(72) Next, predetermined opening portions are formed on the oxide film 116 at predetermined positions by photo etching. After etching the oxide film, subsequently, the semiconductor substrate is etched thus forming trenches 120 having a depth exceeding the pn junction from one surface of the semiconductor substrate (see FIG. 7A).

(73) (c) Insulation Layer Forming Step

(74) Next, an insulation layer 121 formed of a silicon oxide film is formed on inner surfaces of the trenches 120 by a thermal oxidation method using dry oxygen (DryO.sub.2) (see FIG. 7B). A thickness of the insulation layer 121 is set to a value which falls within a range of 5 nm to 60 nm (20 nm, for example). The insulation layer is formed such that a semiconductor base body is introduced into a diffusion furnace and, thereafter, thermal oxidation treatment is performed at a temperature of 900 C. for 10 minutes while supplying an oxygen gas into the diffusion furnace. When the thickness of the insulation layer 121 is less than 5 nm, there may be a case where a reverse current reduction effect cannot be acquired. On the other hand, when the thickness of the insulation layer 121 exceeds 60 nm, there may be a case where a layer made of a glass composition cannot be formed by an electrophoresis method in a next glass layer forming step.

(75) (d) Glass Layer Forming Step

(76) Next, a layer made of the glass composition is formed on inner surfaces of the trenches 120 and a surface of the semiconductor substrate in the vicinity of the trenches 120 by an electrophoresis method, and the layer made of the glass composition is baked so that the glass layer 124 for passivation is formed on the inner surfaces of the trenches 120 and the surface of the semiconductor substrate in the vicinity of the trenches 120 (see FIG. 7C). Here, in forming the layer made of the glass composition on the inner surfaces of the trenches 120, the layer made of the glass composition is formed such that the layer covers the inner surface of the trench 120 with the insulation layer 121 interposed therebetween. Accordingly, the pn junction exposure portion in the trench 120 is brought into a state where the pn junction exposure portion is covered with the glass layer 124 with the insulation layer 121 interposed therebetween.

(77) (e) Photoresist Forming Step

(78) Next, a photoresist 126 is formed such that the photoresist 126 covers a surface of the glass layer 124 (see FIG. 7D).

(79) (f) Oxide Film Removing Step

(80) Next, the oxide film 116 is etched using the photoresist 126 as a mask so that the oxide film 116 at a position 130 where an Ni plating electrode film is to be formed is removed (see FIG. 8A).

(81) (g) Roughened Surface Region Forming Step

(82) Next, a surface of the semiconductor substrate at the position 130 where the Ni-plating electrode film is to be formed is subjected to surface roughening treatment thus forming a roughened surface region 132 for enhancing adhesiveness between an Ni plating electrode and the semiconductor substrate (see FIG. 8B).

(83) (h) Electrode Forming Step

(84) Next, Ni plating is applied to the semiconductor substrate thus forming an anode electrode 134 on the roughened surface region 132 and forming a cathode electrode 136 on the other surface of the semiconductor substrate (see FIG. 8C).

(85) (i) Semiconductor Substrate Cutting Step

(86) Next, the semiconductor substrate is cut by dicing or the like at a center portion of the glass layer 124 thus dividing the semiconductor base body into chips whereby mesa-type semiconductor elements (pn diodes) 102 are manufactured (see FIG. 8D).

(87) (j) Resin Sealing Step

(88) Next, the mesa-type semiconductor element 102 is mounted on a die pad 23 of a lead frame not shown in the drawing (see FIG. 1). One electrode of the mesa-type semiconductor element 102 and a lead 21 are connected to each other, while the other electrode of the mesa-type semiconductor element 102 and a lead 22 are connected to each other by a gold wire 30. Then, these parts are arranged in a resin sealing die not shown in the drawing and, thereafter, a molding resin is injected into the inside of the die and is cured thus manufacturing a resin-sealed semiconductor device. The resin-sealed semiconductor device of the embodiment 2 can be obtained by taking out the resin-sealed semiconductor device from the die.

(89) Through the above-mentioned steps, the resin-sealed semiconductor device of the embodiment 2 can be manufactured.

Examples

1. Preparation of Samples

(90) FIG. 9 is a Table showing conditions and results of examples. Raw materials are prepared at composition ratios indicated in examples 1 to 8 and comparison examples 1 and 2 (see FIG. 9). The raw materials are sufficiently mixed and stirred together by a mixer and, thereafter, the mixed raw material is put into a platinum crucible and is melted in an electric furnace by elevating the temperature to a predetermined temperature (1350 C. to 1550 C.) and is held in a molten state for two hours. Then, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. The glass flakes are pulverized by a ball mill until the glass flakes obtain an average particle size of 5 mm thus obtaining powdery glass composition.

(91) The raw materials used in the examples are SiO.sub.2, H.sub.3BO.sub.3, Al.sub.2O.sub.3, ZnO, CaCO.sub.3, MgO, BaCO.sub.3, NiO and PbO.

(92) The respective glass compositions obtained by the above-mentioned methods are evaluated in accordance with the following evaluation aspects.

(93) (1) Evaluation Aspect 1 (Baking Temperature)

(94) When the baking temperature is excessively high, the baking temperature largely influences a semiconductor device in a manufacturing process. Accordingly, the score good is given when a baking temperature is 1100 C. or below, and the score bad is given when the baking temperature exceeds 1100 C.

(95) (2) Evaluation Aspect 2 (Resistance to Chemicals)

(96) The score good is given when the glass composition exhibits insolubility to both aqua regia and a plating liquid, and the score bad is given when the glass composition exhibits solubility to at least one of aqua regia and a plating liquid.

(97) (3) Evaluation Aspect 3 (Average Linear Expansion Coefficient)

(98) Glass plates in a flaky shape are prepared from a material in a molten state obtained in the above-mentioned 1. Preparation of samples, and an average linear expansion coefficient of the glass composition at a temperature of 50 C. to 550 C. is measured by using the glass plates in a flaky shape. The average linear expansion coefficient is measured by a total expansion measuring method (temperature elevation speed: 10 C./min) using Thermomechanical Analyzers TMA-60 made by SHIMADZU CORP where silicon single crystal having a length of 20 mm is used as a standard sample. As the result, the score good is given when the difference between the average linear expansion coefficient of the glass composition within a temperature range of 50 C. to 550 C. and the linear expansion coefficient (3.73.Math.10.sup.6) of silicon within a temperature range of 50 C. to 550 C. is equal to or below 0.7.Math.10.sup.6, and the score bad is given when such difference exceeds 0.7.Math.10.sup.6.

(99) (4) Evaluation Aspect 4 (Insulation Property)

(100) A mesa-type semiconductor element is manufactured by the same method as the method of manufacturing a resin-sealed semiconductor device of the embodiment 1, and a reverse breakdown voltage characteristic of the manufactured mesa-type semiconductor element is measured. As the result, the score good is given when a reverse breakdown voltage characteristic of the mesa-type semiconductor element falls within a normal range, and the score bad is given when a reverse breakdown voltage characteristic of a mesa-type semiconductor element falls outside a normal range.

(101) (5) Evaluation Aspect 5 (Presence or Non-Presence of Crystallization)

(102) In a step of manufacturing a semiconductor device (pn diode) by a method substantially equal to the method of manufacturing a semiconductor device of the embodiment 4, the score good is given when vitrification can be performed without causing the crystallization of the glass composition, and the score bad is given when vitrification cannot be performed due to the crystallization.

(103) (6) Evaluation Aspect 6 (Presence or Non-Presence of Generation of Bubbles)

(104) A mesa-type semiconductor element is manufactured by a method substantially equal to the method of manufacturing a resin-sealed semiconductor device of the embodiment 1, and the observation is made whether or not bubbles are generated in the inside of the glass layer 124 (particularly, in the vicinity of an interface between the silicon substrate and the glass layer 124) (preliminary evaluation). Then, layers made of glass compositions are formed by applying the glass compositions of the examples 1 to 8 and the comparison examples 1 to 2 to silicon substrates having a size of 10 mm10 mm and glass layers are formed by baking the layers made of the glass compositions. Thereafter, the observation is made whether or not bubbles are generated in the inside of the glass layers (particularly, in the vicinity of an interface between the silicon substrate and the glass layer) (subsequent evaluation).

(105) FIG. 10A and FIG. 10B are views for explaining bubbles b generated in the inside of the glass layer 124 in the preliminary evaluation. FIG. 10A is a cross-sectional view of a semiconductor device when no bubbles b are generated, while FIG. 10B is a cross-sectional view of a semiconductor device when bubbles b are generated. FIG. 11A and FIG. 11B are photographs for explaining bubbles b generated in the inside of the glass layer 124 in the subsequent evaluation. FIG. 11A is a photograph showing an interface between the silicon substrate and the glass layer when no bubbles b are generated in an enlarged manner, and FIG. 11B is a photograph showing an interface between the silicon substrate and the glass layer when bubbles b are generated in an enlarged manner. As the result of the experiment, it is found that there is enough correlation between the result of the preliminary evaluation and the result of the evaluation of the present invention. In the subsequent evaluation, the score good is given when no bubbles having a diameter of 50.Math.m or more are generated in the inside of the glass layer, the score fair is given when one to twenty bubbles having a diameter of 50.Math.m or more are generated in the inside of the glass layer, and the score bad is given when twenty one or more bubbles having a diameter of 50.Math.m or more are generated in the inside of the glass layer.

(106) (7) Evaluation Aspect 7 (Resistance to Reverse Bias at High Temperature)

(107) A resin-sealed semiconductor device is manufactured by a method substantially equal to the method of manufacturing a resin-sealed semiconductor device of the embodiment 1, a high-temperature reverse bias test is performed with respect to the manufactured resin-sealed semiconductor device, and a resistance to a reverse bias at a high temperature is measured. The high-temperature reverse bias test is performed by measuring a reverse current for 70 hours for every 10 minutes in a state where a sample is placed in a thermostatic-bathhigh-temperature bias tester where a temperature condition is set to 150 C. and a voltage of 600V is applied between the anode electrode and the cathode electrode.

(108) FIG. 12 is a graph showing the result of high-temperature reverse bias test. In FIG. 12, a solid line indicates a reverse current with respect to a sample prepared using the glass composition of the example 1, and a broken line indicates a reverse current with respect to a sample prepared using the glass composition of the comparison example 1. As shown in FIG. 12, with respect to the sample prepared using the glass composition of the comparison example 1, it is found that a leakage current (reverse current) is increased with the lapse of time even after the leakage current (reverse current) is increased along with the temperature elevation immediately after the high-temperature reverse bias test starts. To the contrary, with respect to the sample prepared using the glass composition of the example 1, it is found that a leakage current (reverse current) is hardly increased after the leakage current (reverse current) is increased along with the temperature elevation immediately after the high-temperature reverse bias test starts. As the result, the score good is given when a leakage current (reverse current) is hardly increased after the leakage current (reverse current) is increased along with the temperature elevation immediately after the high-temperature reverse bias test starts as described above, and the score bad is given when a leakage current (reverse current) is increased with the lapse of time even after the leakage current (reverse current) is increased along with the temperature elevation immediately after the high-temperature reverse bias test starts.

(109) (8) Comprehensive Evaluation

(110) The score good is given when the score good is given with respect to all of the above-mentioned evaluation aspects 1 to 7, and the score bad is given when the score fair or bad is given with respect to at least one of the respective evaluation aspects.

3. Evaluation Result

(111) As can be understood also from FIG. 9, in all glass compositions according to the comparison examples 1 an 2, the score bad is given with respect to at least one of the evaluation aspects so that the score bad is given with respect to the comprehensive evaluation. That is, in the glass composition according to the comparison example 1, the score bad is given with respect to the evaluation aspect 7. Further, in the glass composition according to the comparison example 2, the score bad is given with respect to the evaluation aspect 2.

(112) To the contrary, in all glass compositions according to the examples 1 to 8, the score good is given with respect to all evaluation aspects (evaluation aspects 1 to 7). As the result, it is found that, with respect to all glass compositions according to the examples 1 to 8, it is possible to manufacture a resin-sealed semiconductor device having higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device. It is also found that (1) the glass composition can be baked at a proper temperature (for example, 1100 C. or below), (2) the glass composition exhibits resistance to chemicals (aqua regia and a plating liquid, for example) used in a step, (3) the glass composition has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly an average linear expansion coefficient at a temperature range of 50 C. to 550 C. being close to a linear expansion coefficient of silicon) thus making warping of a wafer in a step extremely small, and (4) a manufactured glass layer has an excellent insulation property and hence, a resin-sealed semiconductor device having an excellent reverse breakdown voltage characteristic can be manufactured.

(113) Although the resin-sealed semiconductor device, and the method of manufacturing a resin-sealed semiconductor device according to the present invention have been explained heretofore in conjunction with the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be carried out without departing from the gist of the present invention. For example, the following modifications are conceivable.

(114) (1) In the above-mentioned embodiments 1 and 2, although the glass layer is formed using the glass composition described in the embodiment 1, the present invention is not limited to such glass composition. For example, the glass layer may be formed using other glass compositions which substantially contain no Pb.

(115) (2) In the above-mentioned embodiment 2, an insulation layer is formed by a thermal oxidation method using dry oxygen (DryO.sub.2). However, the present invention is not limited to such an insulation layer. For example, an insulation layer may be formed by a thermal oxidation method using dry oxygen and nitrogen (DryO.sub.2+N.sub.2), an insulation layer may be formed by a thermal oxidation method using wet oxygen (WetO.sub.2), or an insulation layer may be formed by a thermal oxidation method using wet oxygen and nitrogen (wetO.sub.2+1%).

(116) (3) In the above-mentioned embodiments 1 and 2, the mesa-type semiconductor element which is constituted of a diode (pn diode) is used. However, the present invention is not limited to such embodiments. For example, a mesa-type semiconductor element constituted of a thyristor may be used. Further, besides the mesa-type semiconductor element constituted of a thyristor, the present invention is also applicable to semiconductor devices in general where a pn junction is exposed (for example, power MOSFET, IGBT and the like).

(117) FIG. 13 is a view for explaining a mesa-type semiconductor element 200 of a modification.

(118) A resin-sealed semiconductor device of the modification basically has the substantially same constitution as the resin-sealed semiconductor device 10 of the embodiment 1. However, the resin-sealed semiconductor device of the modification differs from the resin-sealed semiconductor device 10 of the embodiment 1 with respect to a point that the resin-sealed semiconductor device uses a mesa-type semiconductor element constituted of a thyristor.

(119) That is, the resin-sealed semiconductor device of the modification includes: a mesa-type semiconductor element 200 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region surrounding a mesa region, and a glass layer 224 which covers at least the outer peripheral tapered region; and a molding resin which seals the mesa-type semiconductor element 200, wherein the mesa-type semiconductor element 200 includes a glass layer which substantially contains no Pb as the glass layer 224.

(120) The mesa-type semiconductor element 200 of the modification is formed of a thyristor. As shown in FIG. 13, the mesa-type semiconductor element 200 includes: a mesa-type semiconductor base body 208 an n.sup.-type semiconductor layer 210; a first p.sup.+-type semiconductor layer 212 which is arranged in a state where the first p.sup.+-type semiconductor layer 212 is brought into contact with the n.sup.-type semiconductor layer 210; a second p.sup.+-type semiconductor layer 214 which is arranged in a state where the second p.sup.+-type semiconductor layer 214 is brought into contact with the n.sup.-type semiconductor layer 210; an n.sup.+-type semiconductor region 216 which is formed on a surface of the second p.sup.+-type semiconductor layer 214; an anode electrode 234 which is connected to the first p.sup.+-type semiconductor layer 212; a cathode electrode 236 which is connected to the n.sup.+-type semiconductor region 216, and a gate electrode 238 which is connected to the second p.sup.+-type semiconductor layer 214.

(121) As described above, the resin-sealed semiconductor device of the modification differs from the resin-sealed semiconductor device 10 of the embodiment 1 with respect to a point that the resin-sealed semiconductor device uses the mesa-type semiconductor element formed of a thyristor. However, in the same manner as the resin-sealed semiconductor device 10 of the embodiment 1, the mesa-type semiconductor element includes a glass layer made of lead-free glass (glass which contains no Pb) having a lower dielectric constant than lead-containing glass as the glass layer. Accordingly, the resin-sealed semiconductor device of the modification can acquire higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device in the same manner as the resin-sealed semiconductor device 10 of the embodiment 1, although the resin-sealed semiconductor device of the modification has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device. That is, the resin-sealed semiconductor device of the modification is the resin-sealed semiconductor device having higher resistance to a reverse bias at a high temperature than the conventional resin-sealed semiconductor device while being the resin-sealed semiconductor device which is manufactured by molding the mesa-type semiconductor element with a resin.

EXPLANATION OF SYMBOLS

(122) 10: resin-sealed semiconductor device 20: lead frame 21, 22: lead 23: die pad 30: gold wire 40: resin 100, 102, 200: mesa-type semiconductor element 110, 910: n.sup.-type semiconductor layer 112, 912: p.sup.+-type semiconductor layer 114, 914: n.sup.+-type semiconductor layer 116, 118, 916, 918: oxide film 120, 920: trench 121: insulation film 124, 924: glass layer 126, 926: photoresist 130, 930: position where Ni plating electrode film is to be formed 132, 932: roughened surface region 134, 234, 934, 234: anode electrode 136, 236, 936: cathode electrode 210: n.sup.-type semiconductor layer 212: first p.sup.+-type semiconductor layer 214: second p.sup.+-type semiconductor layer 216: n.sup.+-type semiconductor region 238: gate electrode layer