Flash Memory Device with Three Dimensional Half Flash Structure and Methods for Forming the Same

Abstract

A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Claims

1. A method of forming a memory array, the method comprising: forming a plurality of isolation structures in a substrate, wherein the plurality of isolation structures extend lengthwise in a first direction; and forming a plurality of memory cells between the plurality of isolation structures on the substrate, wherein the plurality of memory cells includes a gate structure comprising: a control gate dielectric layer having a first length in a second direction perpendicular to the first direction; and a control gate layer on the control gate dielectric layer having a second length less than the first length in the second direction.

2. The method of claim 1, wherein the forming of the plurality of memory cells comprises forming a pair of active regions on opposing sides of the gate structure in the second direction, and the pair of active regions includes a first active region bounded by a first isolation structure of the plurality of isolation structures and a second active region bounded by a second isolation structure of the plurality of isolation structures.

3. The method of claim 2, further comprising: forming a frame-shaped spacer structure around the gate structure, wherein the frame-shaped spacer structure has a length in the first direction greater than a length of the pair of active regions in the first direction.

4. The method of claim 2, wherein the forming of the plurality of memory cells comprises: forming a first column of memory cells of the plurality of memory cells between the first isolation structure and the second isolation structure; and forming a second column of memory cells of the plurality of memory cells between the second isolation structure and a third isolation structure of the plurality of isolation structures.

5. The method of claim 4, wherein the forming of the first column of memory cells comprises forming a first memory cell and the forming of the second column of memory cells comprises forming a second memory cell substantially aligned with the first memory cell in the second direction.

6. The method of claim 5, wherein the forming of the first column of memory cells further comprises forming a third memory cell adjacent the first memory cell in the first direction, and the forming of the second column of memory cells further comprises forming a fourth memory cell adjacent the second memory cell in the first direction and substantially aligned with the third memory cell in the second direction.

7. The method of claim 6, wherein the first memory cell and second memory cell are separated in the second direction by a first pitch and the first memory cell and third memory cell are separated in the first direction by a second pitch less than the first pitch.

8. The method of claim 1, wherein a width of the plurality of isolation structures is less than a width of the substrate between the plurality of isolation structures.

9. The method of claim 1, wherein the control gate layer has a length in the first direction greater than the second length of the control gate layer in the second direction.

10. The method of claim 1, wherein the forming of the plurality of memory cells comprises: forming extension regions of active regions in the substrate on opposite sides of the gate structure in the second direction; and after the forming of the extension regions, etching the control gate layer to expose an upper surface of the control gate dielectric layer.

11. The method of claim 10, wherein the forming of the plurality of memory cells further comprises: after the etching of the control gate layer, forming a spacer structure on the gate structure; and after the forming of the spacer structure, forming deep regions of the active regions in the substrate on opposite sides of the gate structure in the second direction.

12. The method of claim 11, wherein the forming of the spacer structure comprises: forming a first sidewall spacer on a sidewall of the control gate dielectric layer; and forming a second sidewall spacer on a sidewall of the control gate layer and on the upper surface of the control gate dielectric layer.

13. The method of claim 12, further comprising: forming an electrical contact on the exposed upper surface of the control gate dielectric layer.

14. The method of claim 13, further comprising: forming an interlevel dielectric layer on the gate structure such that the interlevel dielectric layer contacts the control gate dielectric layer between the electrical contact and the second sidewall spacer.

15. The method of claim 13, wherein the plurality of memory cells further comprises a channel region between the pair of active regions and the forming of the electrical contact comprises forming the electrical contact over the channel region.

16. A method of forming a memory array, the method comprising: forming an isolation structure in a substrate, wherein the isolation structure extends lengthwise in a first direction; and forming a plurality of memory cells on opposing sides of the isolation structure, wherein the plurality of memory cells comprises: a pair of active regions including an active region contacting the isolation structure; and a gate structure on the substrate between the pair of active regions, comprising: a control gate dielectric layer having a first length in a second direction perpendicular to the first direction; and a control gate on the control gate dielectric layer having a second length less than the first length in the second direction.

17. The method of claim 16, wherein the forming of the isolation structure comprises forming a plurality of isolation structures, and the forming of the plurality of memory cells comprises: forming a first column of memory cells of the plurality of memory cells between a first isolation structure of the plurality of isolation structures and a second isolation structure of the plurality of isolation structures; and forming a second column of memory cells of the plurality of memory cells between the second isolation structure and a third isolation structure of the plurality of isolation structures.

18. The method of claim 17, wherein the forming of the first column of memory cells comprises forming a first memory cell and a third memory cell adjacent the first memory cell in the first direction, and the forming of the second column of memory cells comprises forming a second memory cell substantially aligned with the first memory cell in the second direction and a fourth memory cell adjacent the second memory cell in the first direction and substantially aligned with the third memory cell in the second direction.

19. The method of claim 18, wherein the forming of the plurality of memory cells further comprises separating the first memory cell and second memory cell in the second direction by a first pitch and separating the first memory cell and third memory cell in the first direction by a second pitch less than the first pitch.

20. A memory array, comprising: a plurality of isolation structures in a substrate, wherein the plurality of isolation structures extend lengthwise in a first direction; and a plurality of memory cells between the plurality of isolation structures, wherein the plurality of memory cells includes a gate structure comprising: a control gate dielectric layer having a first length in a second direction perpendicular to the first direction; and a control gate layer on the control gate dielectric layer having a second length less than the first length in the second direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0004] FIG. 1 is a vertical cross-sectional view illustrating a step of forming a continuous tunnel dielectric layer, a continuous floating gate layer, a continuous control gate dielectric layer, a continuous control gate layer and photoresist layer on a substrate in a method for fabricating a semiconductor device in accordance with some embodiments.

[0005] FIG. 2 is a vertical cross-sectional view illustrating a step of patterning the photoresist layer in a method for fabricating a semiconductor device in accordance with some embodiments.

[0006] FIG. 3 is a vertical cross-sectional view illustrating a step of patterning the continuous tunnel dielectric layer, the continuous floating gate layer, the continuous control gate dielectric layer and the continuous control gate layer with the patterned photoresist.

[0007] FIG. 4 is a vertical cross-sectional view illustrating a step of ion implanting the substrate to form active extension regions in the substrate in a method for fabricating a semiconductor device in accordance with some embodiments.

[0008] FIG. 5 is a vertical cross-sectional view illustrating a step of depositing a photoresist in a method for fabricating a semiconductor device in accordance with some embodiments.

[0009] FIG. 6 is a vertical cross-sectional view illustrating a step of patterning a photoresist in a method for fabricating a semiconductor device in accordance with some embodiments.

[0010] FIG. 7 is a vertical cross-section view illustrating a step of further etching the control gate electrode using the patterned photoresist as a mask.

[0011] FIG. 8 is a vertical cross-sectional view illustrating a step of forming a continuous sidewall spacer layer in a method for fabricating a semiconductor device in accordance with some embodiments.

[0012] FIG. 9 is a vertical cross-sectional view illustrating a step of forming sidewall spacers by etching the continuous sidewall spacer layer in a method for fabricating a semiconductor device in accordance with some embodiments.

[0013] FIG. 10 is a vertical cross-sectional view illustrating a step of ion implanting the substrate to form deep source and drain regions a method for fabricating a semiconductor device in accordance with some embodiments.

[0014] FIG. 11 is a top view illustrating a step of siliciding the deep source and drain regions and the gate electrode in a method for fabricating a semiconductor device in accordance with some embodiments.

[0015] FIG. 12 is a vertical cross-sectional view illustrating a step of forming an interlevel dielectric layer and source/drain electrodes in a method for fabricating a semiconductor device in accordance with some embodiments.

[0016] FIG. 13 is a top-down view of an array of flash memory cells in accordance with some embodiments.

[0017] FIG. 14 is a flowchart illustrating a method of making a semiconductor memory device in accordance with some embodiments.

DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

[0019] Further, spatially relative terms, such as beneath, below, lower, above, upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0020] Generally, the structures and methods of the present disclosure can be used to form flash memory devices in which at least some of the flash memory devices have a control gate electrode that is shorter in length than the length of the corresponding floating gate electrode. Further, at least some of the flash memory devices have at least one electrical contact to the gate dielectric layer in addition to the electrical contacts to the source region, drain region and control gate electrode. The floating gate electrode can be programmed and erased by applying a voltage to the electrical contact connected to the gate dielectric layer. By using the electrical contact to the gate dielectric layer for programming and erasing rather than using the control gate electrode, the resistance R.sub.poly associated with the polysilicon control gate electrode can be avoided. The elimination of the resistance R.sub.poly associated with the polysilicon control gate electrode may result in a better coupling ratio which results in faster programming and erasing of the flash memory device.

[0021] In some embodiments, more than one electrical contact may be provided to the gate dielectric layer. The use of more than one electrical contact to the gate dielectric layer may result in an increased coupling area. The increased coupling area may in turn result in a higher coupling ratio. The coupling ratio is defined by equation 1 below:

[00001]$\begin{array}{cc}{}_{\mathrm{cg}}=\frac{C_{\mathrm{ONO}}}{\left(C_D+C_S+C_B+C_{\mathrm{ONO}}\right)}& \mathrm{Equation}l\end{array}$

[0022] Where .sub.cg is the coupling ratio, C.sub.ONO is the capacitance between the control gate and the floating gate, C.sub.D is the capacitance between the drain and the floating gate, C.sub.S is the capacitance between the source and the floating gate, and C.sub.B is the capacitance between the floating gate and the bulk semiconductor as measured in the channel. As discussed above, the increase in the coupling ratio may result in faster programming and erasing of the flash memory device.

[0023] In conventional flash memory, each memory cell resembles a standard metal-oxide-semiconductor field-effect transistor (MOSFET) except that the transistor has two gates instead of one. The memory cells can be seen as an electrical switch in which current flows between two active regions (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this, there is the FG insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge screens the electrical field from the CG, thus, increasing the threshold voltage (V.sub.T1) of the cell. Thus, a higher voltage (V.sub.T2) must be applied to the CG to make the MOSFET channel conductive. In order to read a value from the transistor, an intermediate voltage between the threshold voltages (V.sub.T1 & V.sub.T2) is applied to the CG. If the channel conducts at this intermediate voltage, the FG must be uncharged (if it was charged, we would not get conduction because the intermediate voltage is less than V.sub.T2), and hence, a logical 1 is stored in the gate. If the channel does not conduct at the intermediate voltage, it indicates that the FG is charged, and hence, a logical 0 is stored in the gate. The presence of a logical 0 or 1 is sensed by determining whether there is current flowing through the transistor when the intermediate voltage is asserted on the CG. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.

[0024] In various embodiments, the status of the memory device (i.e. logical 1 or 0) can be determined with the contact to the control gate electrode as in other flash memory devices.

[0025] Referring to FIG. 1, a continuous tunnel dielectric layer 104L, a continuous floating gate layer 106L, a continuous control gate dielectric layer 114L, a continuous control gate layer 116L and a continuous photoresist layer 118L may be formed on a semiconductor substrate 102. The semiconductor substrate 102 may be made of any suitable material, such as silicon, silicon on insulator (SOI) or silicon on sapphire (SOS). The semiconductor substrate 102 may include electrical dopants (such as p-type dopants or n-type dopants) at an atomic concentration less than 1.010.sup.14/cm.sup.3 in order to provide low electrical conductivity and to minimize eddy current that may be induced by inductive coupling with high frequency electrical signals from, to, or between semiconductor dies or redistribution wiring interconnects to be subsequently placed in proximity.

[0026] The continuous tunnel dielectric layer 104L may be made of any suitable material, such as an oxide or nitride, such as silicon oxide. The continuous floating gate layer 106L may be made of any suitable material, such as polysilicon. The continuous control gate layer 116L may be made of a metal, such as tungsten, nickel, aluminum or alloys thereof or the continuous control gate layer 116L may be made of be made of polysilicon.

[0027] The continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L and the continuous control gate layer 116L may be each deposited by any suitable method, such as chemical vapor deposition (CVD), organometallic chemical vapor deposition (OMCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The continuous photoresist layer 118L may be a positive or negative photoresist.

[0028] In various embodiments, the continuous control gate dielectric layer 114L may include a continuous first oxide layer 108L, a continuous nitride layer 110L and continuous second oxide layer 112L. This layered structure may be referred to as a oxide-nitride-oxide (ONO) sandwich layer. A continuous first oxide layer 108L may be deposited over the continuous floating gate layer 106L. The continuous first oxide layer 108L may be made of any suitable oxide, such as SiO.sub.2, HfO.sub.2, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, ZrO.sub.2, TiO.sub.2. Next, a continuous nitride layer 110L, such as silicon nitride, may be deposited over the continuous first oxide layer 108L.

[0029] A continuous second oxide layer 112L may be deposited over the continuous nitride layer 110L. In this manner, a continuous oxide/nitride/oxide control gate dielectric layer 114L may be formed over the continuous floating gate layer 106L. The continuous second oxide layer 112L may be made of the same material as the continuous first oxide layer 108L or may be made of a different material. The continuous first oxide layer 108L may have a thickness in the range of 20 -200 , such as 50 -150 , although lesser or greater thicknesses are within the contemplated scope of disclosure. The continuous nitride layer 110L may have a thickness in the range of 20 -250 , such as 50 -200 , although lesser or greater thicknesses are within the contemplated scope of disclosure. The continuous second oxide layer 112L may have thickness in the range of 100 -500 , such as 200 -400 , although lesser or greater thicknesses are within the contemplated scope of disclosure. In an embodiment, a thickness of the continuous second oxide layer 112L may be 5-10% greater than a thickness of the continuous first oxide layer 108L.

[0030] Referring FIG. 2, the continuous photoresist layer 118L may be exposed to radiation and patterned. As illustrated in FIG. 2, the continuous photoresist layer 118L may be patterned to form a patterned photoresist layer 118 such that a central portion of the continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L are masked by the patterned photoresist layer 118.

[0031] Referring FIG. 3, the patterned photoresist layer 118 may then be used to mask and pattern the continuous control gate layer 116L, the continuous control gate dielectric layer 114L (including continuous second oxide layer 112L, continuous nitride layer 110L, and the continuous first oxide layer 108L), the continuous floating gate layer 106L, and the continuous tunnel dielectric layer 104L. The result may be a stack 119 of patterned layers 104, 106, 114, 116 that includes a patterned tunnel dielectric layer 104, a floating gate electrode 106, a patterned control gate dielectric layer 114 and a control gate electrode 116. In various embodiments, the patterned control gate dielectric layer 114 may include an ONO sandwich layer comprising a patterned first oxide layer 108, a patterned nitride layer 110 and a patterned second oxide layer 112. The continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L may be patterned by one or more wet etching processes, one or more dry etching processes or a combination of wet and dry etching processes.

[0032] Referring to FIG. 4, the semiconductor substrate 102 may be subject to a first ion implantation step 120 to form active extension regions 122, 124 (i.e. source/drain extension regions) in the semiconductor substrate 102. The stack 119 of patterned layers may serve to mask the portion of the semiconductor substrate 102 between the active extension regions 122, 124. Therefore, active extension regions 122, 124 may be self-aligned to the floating gate electrode 106 and the control gate electrode 116. The active extension regions 122, 124 may be doped either p-type or n-type as desired. Example n-type dopants include, but are not limited to, antimony, arsenic and phosphorous. Example p-type dopants include, but are not limited to boron, aluminum and gallium. The active extension regions 122, 124 may have an implanted dopant concentration of 110.sup.20 to 510.sup.21, such as 210.sup.20 to 210.sup.21, although lesser or greater dopant concentrations are within the contemplated scope of disclosure. The region under the stack 119 of patterned layers located between active extension regions 122, 124 constitutes the channel region 125. The patterned photoresist layer 118 may be removed by any suitable process, such as an ashing process. Alternatively, the patterned photoresist layer 118 may be removed prior to the first ion implantation step 120 occurs.

[0033] Referring to FIGS. 5 and 6, a second photoresist layer 118a may be deposited over the semiconductor substrate 102 and the stack 119 of patterned layers 104, 106, 114, 116. The second photoresist layer 118a may then be patterned to expose a portion of the stack 119 of patterned layers 104, 106, 114, 116. The second photoresist layer 118a may be made of the same material as the material of the patterned photoresist layer 118 or may be made of a different material.

[0034] Referring to FIG. 7, the exposed portion of the control gate electrode 116 may be etched to form a smaller length control gate electrode 116a. That is, the control gate electrode 116 may be etched such that the length L.sub.CG of the smaller length control gate electrode 116a along its major axis, is shorter than the length L.sub.FG of the underlying floating gate electrode 106 along a major axis of the floating gate electrode 106. The control gate electrode 116 may be either wet etched or dry etched to form the smaller length control gate electrode 116a. The underlying patterned control gate dielectric layer 114 may serve as an etch stop. The remaining second photoresist layer 118a may be removed by any suitable process, such as an ashing process.

[0035] Referring to FIG. 8, a continuous sidewall spacer layer 126L may be conformally deposited over the surface of the semiconductor substrate 102 and the stack 119 of patterned layers 104, 106, 114, 116a. The continuous sidewall spacer layer 126L may be made of any suitable dielectric material, such SiO.sub.2 or Si.sub.3N.sub.4. The continuous sidewall spacer layer 126L may be deposited by any suitable method, such as CVD, OMCVD, PECVD, LPCVD or ALD.

[0036] Referring to FIG. 9, the continuous sidewall spacer layer 126L may be anisotropically etched to form a first sidewall spacer 126a located over sidewalls of the patterned tunnel dielectric layer 104, the floating gate electrode 106 and the patterned control gate dielectric layer 114, a second sidewall spacer 126b located over sidewalls of the smaller length control gate electrode 116a and a third sidewall spacer 126c located over sidewalls of the patterned tunnel dielectric layer 104, the floating gate electrode 106, the patterned control gate dielectric layer 114 and the smaller length control gate electrode 116a. The anisotropic etching process removes portions of the continuous sidewall spacer layer 126L such that portions of the substrate 102, portions of the active extension regions 122, 124, a portion of the patterned control gate dielectric layer 114 and the top surface of smaller length control gate electrode 116a may be exposed.

[0037] Referring to FIG. 10, a second ion implantation step 128 may be performed. In this step, the exposed portions of the active extension regions 122, 124 may be ion implanted to form deep active regions 130, 132 adjacent the active extension regions 122, 124. The deep active regions 130, 132 may have an implanted ion concentration in the range of 110.sup.20 to 510.sup.21, such as 210.sup.20 to 210.sup.21, although lesser or greater dopant concentrations are within the contemplated scope of disclosure. The ions implanted in the second ion implantation step 128 may be the same as or different from the ions implanted in the first ion implantation step 120. Together, one of the active extension regions 122, 124 and the adjacent deep active region 130, 132 form a source region and the other of the active extension regions 122, 124 and the adjacent deep active region 130, 132 for a drain region.

[0038] Referring to FIG. 11, a silicide layer 134 may be optionally formed on the top surfaces of the deep active regions 130, 132. The silicide layer 134 may provide enhanced electrical connection with subsequently formed via contacts. A photoresist layer (not shown) may be deposited over the surface of the intermediate structure illustrated in FIG. 10 and patterned to expose top surfaces of the deep active regions 130, 132. The silicide layer 134 may then be formed by depositing a thin layer of metal (not shown) and heating to react the metal with the deep active regions 130, 132. Further, as illustrated, if the smaller length control gate electrode 116a is made of polysilicon, metal may be deposited on the top surface of the smaller length control gate electrode 116a and heated for form a silicide layer 134 on the top surface of the control gate electrode 116a.

[0039] Referring to FIG. 12, an interlevel dielectric layer 136 may be deposited over the entirety of the intermediate structure illustrated in FIG. 11. Via holes (not shown) may be formed in the interlevel dielectric layer 136 and subsequently filled with metal, such as W, Cu, Co, Mo, Ru, other elemental metals, or an alloy or a combination thereof. In this manner, electrical contacts 138 to the deep active regions 130, 132 may be formed to complete a flash memory cell 100. The formation of the interlevel dielectric layer 136 and the electrical contacts 138 completes a flash memory cell 100. In an embodiment, the flash memory cell 100 may have a first electrical contact 138 electrically connected to one of the deep active regions 130, 132 (source or drain) through optional silicide layer 134, a second electrical contact 138 electrically connected to the other deep active region 130, 132 (source or drain) through optional silicide layer 134, and a third electrical contact 139 electrically connected to the smaller length control gate electrode 116a through optional silicide layer 134. A fourth electrical contact 140a may be electrically connected to the patterned control gate dielectric layer 114 through optional top layer of the patterned second oxide layer 112. In an embodiment, the flash memory cell 100 may include a fifth electrical contact 140b electrically connected to the patterned control gate dielectric layer 114 through optional top layer of the patterned second oxide layer 112. In various embodiments, the flash memory cell 100 may be configured such that the flash memory cell 100 may be programmed and erased by applying a voltage to the fourth electrical contact 140a and read by applying a voltage to the fifth electrical contact 140b.

[0040] FIG. 13 illustrates a two dimensional array 200 of flash memory cells 100. To electrically isolate columns of adjacent flash memory cells 100, shallow trench isolation (STI) structures 150 may be formed in the semiconductor substrate 102. The shallow trench isolation structures 150 may be formed by etching trenches (not shown) in the semiconductor substrate 102 and filling the trenches with a dielectric material, such as SiO.sub.2. The STI trenches may have a depth in a range from 50 nm to 500 nm, such as 100 nm to 400 nm, although lesser or greater depths are within the contemplated scope of disclosure. For example, the STI trenches 150 may have a depth in a range of 75 nm to 400 nm, 100 nm to 350 nm, although lesser or greater depths are within the contemplated scope of disclosure.

[0041] In various embodiments, the two dimensional array 200 of flash memory cells 100 includes a two-dimensional periodic array of floating gate electrodes 106 and smaller length control gate electrode 116a located over a semiconductor substrate 102 which has a doping of a first conductivity type. The smaller length control gate electrode 116a may be located over the floating gate electrodes 106. The length L.sub.CG along a major axis of the smaller length control gate electrode 116a may be less than a length L.sub.FG along a major axis of the floating gate electrode 106. The two dimensional array 200 of flash memory cells 100 also includes a two-dimensional array of deep active regions 130, 132 that may be formed within the semiconductor substrate 102. The deep active regions 130, 132 have a doping of a second conductivity type. The two-dimensional array of deep active regions 130, 132 may be laterally offset from the two-dimensional array of floating gate electrodes 106 along a first horizontal direction. Each of the floating gate electrodes 106 may be located between a neighboring pair of deep active regions 130, 132 within the two-dimensional array of deep active regions 130, 132. In various embodiments, each of the two-dimensional array of floating gate electrodes 106, the two-dimensional array of deep active regions 130, 132, and the two-dimensional array of smaller length control gate electrode 116a has a same first pitch along the horizontal direction.

[0042] FIG. 14 is a flowchart illustrating general method 300 of making a memory device according to various embodiments. Referring to step 302, a continuous tunnel dielectric layer 104L may be deposited over a semiconductor substrate 102. The tunnel dielectric may be made of any suitable dielectric material and may have a thickness in the range of 1-15 nm. Referring to step 304 a continuous floating gate layer 106L may be deposited over the continuous tunnel dielectric layer 104L. Referring to step 306, a continuous control gate dielectric layer 114L may be deposited over the continuous floating gate layer 106L. In various embodiments, the continuous control gate dielectric layer 114L may comprise a continuous first oxide layer 108L, a continuous nitride layer 110L and a continuous second oxide layer 112L. Referring to step 308, a continuous control gate layer 116L may be deposited over the continuous control gate dielectric layer 114L. The continuous tunnel dielectric layer 104L, continuous floating gate layer 106L, continuous control gate dielectric layer 114L and continuous control gate layer 116L may be deposited by any suitable method such as CVD, OMCVD, PECVD, LPCVD or ALD. Referring to step 310, the continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L and the continuous control gate layer 116L may be patterned to form a patterned tunnel dielectric layer 104, a floating gate electrode 106, a patterned control gate dielectric layer 114 and a control gate electrode 116. Patterning may be performed by depositing a continuous photoresist layer 118L over the continuous control gate layer 116L and using photolithography to pattern an appropriate mask over the continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L and the continuous control gate layer 116L. The exposed layers of the continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L and the continuous control gate layer 116L may be etched to form the control gate electrode 116, patterned control gate dielectric layer 114, floating gate electrode 106 and patterned tunnel dielectric layer 104. Any suitable etching method such as wet etching, dry etching or their combination may be used to form the control gate electrode 116, the patterned control gate dielectric layer 114, the floating gate electrode 106 and the patterned tunnel dielectric layer 104. Referring to step 312, the control gate electrode 116 may be further patterned to form a smaller length control gate electrode 116a. The smaller length control gate electrode 116a may have a length L.sub.CG parallel to the major axis of the semiconductor substrate 102 that is shorter than a length L.sub.FG of the floating gate electrode 106.

[0043] Generally, the structures and methods of the present disclosure may be used to form flash memory cells 100 in which at least some of the flash memory cells 100 have a smaller length control gate electrode 116a which is shorter in length L.sub.CG than the floating gate electrode 106. Further, at least some of the flash memory cells 100 may have at least one electrical contact 140a, 140b to the patterned control gate dielectric layer 114 in addition to the electrical contacts 138 to the deep active regions 130, 132 (source/drain regions) and the third electrical contact 139 to the smaller length control gate electrode 116a. The floating gate electrode 106 may be programmed and erased by applying a voltage to the electrical contact 140a, 140b connected to the patterned control gate dielectric layer 114. By using the electrical contact 140a, 140b to the patterned control gate dielectric layer 114 for programming and erasing rather than using the smaller length control gate electrode 116a, the resistance R.sub.poly associated with the (polysilicon) smaller length control gate electrode 116a may be avoided. The elimination of the resistance R.sub.poly associated with the polysilicon smaller length control gate electrode 116a may result in a faster memory device. In some embodiments, more than one electrical contact 140a, 140b may be provided to the patterned control gate dielectric layer 114. This may result in an increased coupling area which may lead to a higher coupling ratio. The increase in the coupling ratio may also result in a faster flash memory cell 100.

[0044] An embodiment is drawn to a flash memory cell 100 located on a semiconductor substrate 102 including a floating gate electrode 106, a patterned tunnel dielectric layer 104 located between the semiconductor substrate 102 and the floating gate electrode 106, a smaller length control gate electrode 116a and a patterned control gate dielectric layer 114 located between the floating gate electrode 106 and the smaller length control gate electrode 116a. The length L.sub.CG of a major axis of the smaller length control gate electrode 116a is less than a length L.sub.FG of a major axis of the floating gate electrode 106.

[0045] An embodiment is drawn to a two dimensional array 200 of flash memory cells 100 including a two-dimensional array of floating gate electrodes 106 and smaller length control gate electrode 116a located over a semiconductor substrate 102 having a doping of a first conductivity type. The smaller length control gate electrode 116a may be located over the floating gate electrodes 106 and have a length L.sub.CG along a major axis of the smaller length control gate electrode 116a that is less than a length L.sub.FG along a major axis of the floating gate electrode 106. The two dimensional array 200 also includes a two-dimensional array of deep active regions 130, 132 that may be formed within the semiconductor substrate 102. The deep active regions 130, 132 may have a doping of a second conductivity type. Also, the deep active regions 130, 132 may be laterally offset from the two-dimensional array of floating gate electrodes 106 along a first horizontal direction. Each of the floating gate electrodes 106 may be located between a neighboring pair of deep active regions 130, 132 within the two-dimensional array of deep active regions 130, 132.

[0046] In various embodiments, each of the two-dimensional array of floating gate electrodes 106, the two-dimensional array of deep active regions 130, 132, and the two-dimensional array of smaller length control gate electrode 116a may have a same first pitch P.sub.1 along the first horizontal direction. In various embodiments, the array of flash memory cells 100 comprises a two-dimensional periodic array of flash memory cells 100. Each flash memory cell 100 in the two-dimensional periodic array comprises a floating gate electrode 106 in the two-dimensional array of floating gate electrodes 106, deep active regions 130, 132 in a two-dimensional array of deep active regions 130, 132, and a smaller length control gate electrode 116a in the two-dimensional array of smaller length control gate electrode 116a. Each flash memory cell 100 in the two-dimensional periodic array 200 may be laterally offset from an adjacent flash memory cell 100 in the two-dimensional periodic array 200 along a second horizontal direction with a same second pitch P.sub.2.

[0047] An embodiment is drawn to a method 300 of making a flash memory device 100 including depositing a continuous tunnel dielectric layer 104L over a semiconductor substrate 102, depositing a continuous floating gate layer 106L over the continuous tunnel dielectric layer 104L, depositing a continuous control gate dielectric layer 114L over the continuous floating gate layer 106L, depositing a continuous control gate layer 116L over the continuous control gate dielectric layer 114L, patterning the continuous tunnel dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L and the continuous control gate layer 116L to form a patterned tunnel dielectric layer 104, a floating gate electrode 106, a patterned control gate dielectric layer 114 and a control gate electrode 116 and further patterning the control gate electrode 116 to form a smaller length control gate electrode 116a such that the smaller length control gate electrode 116a has a length L.sub.CG parallel to the major axis of the substrate 102 that is shorter than a length L.sub.FG of a major axis of the floating gate electrode 106.

[0048] In an embodiment, active extension regions 122, 124 may be formed in the semiconductor substrate 102 extending laterally from sidewalls of the patterned tunnel dielectric layer 104. The active extension regions 122, 124 may be formed by a first ion implantation step 120. In an embodiment, deep active regions 130, 132 may be formed with a second ion implantation step 128.

[0049] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.