Chip Scale Package

Abstract

A novel semiconductor chip scale package encapsulates semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.

Claims

1. A semiconductor device package, comprising: a semiconductor chip having a device side with metallic contact bumps thereon, a non-device side opposite the device side, and four edges; a first layer of mold compound covering the four edges and the device side of the chip; a second layer of mold compound covering the non-device side of the chip; the first layer of mold compound joining the second layer of mold compound at a plane that is coplanar to the non-device side of the chip.

2. The semiconductor device package of claim 1, in which a top portion of the contact bumps on the device side of the semiconductor chip protrude from the first layer of mold compound.

3. The semiconductor device package of claim 2, in which the protruding portion of the contact burns is covered with a metallic film containing gold.

4. The semiconductor device package of claim 3, in which the contact bumps contain nickel.

5. The semiconductor device package of claim 1, in which the first layer of mold compound contains filler particles.

6. The semiconductor device package of claim 5, further comprising partially ground filler particles near the plane where the first layer and the second layer of mold compound meet.

7. The semiconductor device of claim 6, in which the partially ground filler particles are embedded in the first layer of mold compound.

8. The semiconductor device of claim 7, in which the partially ground filler particles are not embedded in the second mold compound.

9-17. (canceled)

18. A semiconductor device, comprising: a semiconductor chip having a device side and four edge and a non-device side; a first layer of mold compound covering the device side of the chip and extending down the four edges; a second layer of a different mold compound covering the non-device side of the semiconductor chip and extending from the non-device side, joining the first layer of mold compound.

19. The semiconductor device of claim 18, further comprising copper contact on the device side of the semiconductor chip.

20. The semiconductor device of claim 19, in which the first layer of mold compound has partially ground filler particles near the second layer of mold compound.

21. The semiconductor device of claim 20, in which the partially ground particles form surface co-planar with the non-device side of the semiconductor chip.

22. A semiconductor device, comprising: a first mold compound having filler particles; and partially ground filler particles disposed on a surface of a layer of second mold compound.

23. The semiconductor device of claim 22, further comprising a semiconductor chip on the surface of the layer of second mold compound.

24. The semiconductor device of claim 23, further comprising metallic contacts on a device side of the semiconductor chip.

25. The semiconductor device of claim 24, in which the metallic contacts comprise copper.

26. The semiconductor device of claim 25, in which the metallic contacts further comprise gold or platinum.

Description

BRIEF DESCRIPTION DRAWING FIGURES

[0015] FIG. 1 through FIG. 6 depicts the process flow that embodies some aspects of this invention.

[0016] FIG. 7 depicts a cross section view of a semiconductor device package that embodies some aspects of this invention.

[0017] FIG. 8 is a micrographic photograph of a semiconductor device package partially fabricated according to some aspects of this invention.

[0018] FIG. 9 is another micrographic photograph of a semiconductor device package partially fabricated according to some aspects of this invention.

[0019] FIG. 10 is another micrographic photograph of a semiconductor device package partially fabricated according to some aspects of this invention.

DETAIL DESCRIPTION

[0020] FIG. 1 through FIG. 6 depicts a process flow that embodies some aspects of this invention. The package 100 depicted in FIG. 1 comprises a silicon wafer 101 with integrated circuit elements fabricated in it. Although the wafer used in the illustrative flow is silicon, this process may also be performed on semiconductor other than silicon such as silicon carbide, gallium nitride, etc. The integrated circuit elements are manifested by the nickel bumps 103 through which the integrated circuit may be connected to a printed circuit board.

[0021] In this illustrative process the nickel bumps are plated on the silicon wafer surface to a thickness of about 30 m. In alternative processes, copper may be used instead of nickel. The bumps may be plated to a thickness more or less than 30 m.

[0022] Also depicted in FIG. 1 are two trenches 102 formed in the silicon wafer 101. The trenches may be cut by the sawing process that is customarily used in the art of semiconductor device assembly except the trenches do not reach the back side of the wafer. In this illustrative process, the depth of the trenches bout 300 m and is deeper than the integrated circuit elements in the silicon wafer.

[0023] Methods other than sawing, such as reactive on etching (RCE), laser heating, and water jet may also be used to form the trench as known in the art.

[0024] FIG. 2 depicts the wafer in a later stage of the process flow. In FIG. 2, the trenches are shown as filled with mold compound 201 with a transfer molding step known in the art. In this illustrative process flow, the mold compound is a mixture of epoxy and filler particles. The trenches in FIG. 2 are about 140 m wide and some filler particles have diameter about 25 m.

[0025] In this illustrative process flow, the mold compound material 201 as applied may cover the top of the contact bumps 103 and must be removed. There are other molding processes that will leave the top of the contact bumps free of mold compound. One such process involves lining the inner surface of the mold cavity with an elastic film. The film covers the top portion of the contact bumps and keeps the area from the mold compound. The film adds cost to the molding process but saves the cost involved in the cleaning process afterwards.

[0026] In this illustrative process flow, a light chemical mechanical polish (CMP) known in the art is used successfully in the removal of mold compound from the top area of the contact bumps 103. Following the CMP step, the contact bumps are plated with a thin layer of metallic material 302 that is wettable in soldering processes known in the art. In this illustrative process flow, the metallic material includes gold.

[0027] FIG. 4 depicts the semiconductor device package in a later stage of the process flow. Before this stage the individual silicon chips and the back portion of the silicon wafer below the bottom of the trenches are one unitary piece. Even though the silicon chips are clearly delineated by the trenches around them, they are all connected to the back portion of the silicon wafer. As depicted in FIG. 4, the back portion of the silicon wafer that connects the individual chips is removed and the individual silicon chips 401 are severed from their neighbors.

[0028] In this illustrative process flow, the back portion of the silicon wafer is removed by a back-grinding process known in the art. The grinding passes the bottom of the trenches and separates the individual silicon chips.

[0029] The grinding process not only removes the back portion of the silicon wafer but also a portion of the mold compound near the bottom of the trenches. And at the completion of the grinding step, the back side of each silicon chip is coplanar with the surface of the mold compound in the trenches around the silicon chip. The co-planarity is evident in FIG. 10 as between the back surface of the silicon chip 1001 and the bottom of the mold compound and where some filler particles 1002 are partially ground.

[0030] At the completion of the grinding operation individual silicon chips 401 are severed from the neighboring chips but are held together by the mold compound in the trenches and the shape of the wafer is maintained. A stress relief step may be taken to remove some damaged silicon from the back side with chemical or plasma etch and that may create a small step in the order of micrometers between the mold compound and the back side of the chips.

[0031] FIG. 5 depicts the semiconductor device package 500 in a later stage of the process flow. In this illustrative process flow, a second layer of mold compound material 501 is applied to the backside of the silicon chips. The second layer of mold compound 501 meets the first layer of mold compound at the surface 503 which is coplanar to the back of the chip 401. The second layer mold compound being be applied with a transfer molding process. Or it may be laminated.

[0032] After the second layer of mold compound is cured, the individual devices may be electrically tested, marked, and singulated. FIG. 6 depicts the individual devices 601 following singulation.

[0033] FIG. 7 depicts a typical semiconductor device package that embodies aspects of this invention. Element 701 is the silicon chip with integrated circuit elements connected to the contact bumps 702. The silicon chip 701 and the contact bumps 702 are encapsulated with a first layer of mold compound 704 and a second layer of mold compound 703. The back side of the silicon chip is coplanar with the interface between the first mold compound layer 704 and the first mold compound layer 703.

[0034] In FIG. 8, element 801 depicts a portion of a silicon wafer. Element 802 depicts a trench formed between silicon chips 805 and 806 in the silicon wafer 801 and as being filled with mold compound 804. Element 803 is a contact bump made of nickel metal. Element 808 is excess mold compound over the top surface of the contact bumps 803. FIG. 9 depicts a portion of the front side of a silicon wafer 901 post a chemical mechanical polish (CMP) process. At this stage of the process flow, the top surfaces of the contact bumps 903 are clear of mold compound. In order to enhance the solderability of the contact bumps to metal pads on printed circuit board, the surface of the contact bumps may be coated with a thin metallic film that contains noble metal such as gold or platinum at this stage.

[0035] The process flow and the semiconductor device packages fabricated with the process flow are for demonstrative purposes only and they do not limit the scope of the invention, which is described in the appending claims.