Semiconductor Device and Method for Reducing Metal Burrs Using Laser Grooving

Abstract

A semiconductor device is formed using a jig. The jig includes a metal frame, a polymer film, and an adhesive layer disposed between the metal frame and polymer film. An opening is formed through the adhesive layer and polymer film. A groove is formed around the opening. A semiconductor package is disposed on the jig over the opening with a side surface of the semiconductor package adjacent to the groove. A shielding layer is formed over the semiconductor package and jig. The semiconductor package is removed from the jig.

Claims

1. A semiconductor device, comprising: a jig including a metal frame, a polymer film, and an adhesive layer disposed between the metal frame and polymer film; an opening formed through the adhesive layer and polymer film; a groove formed in the adhesive layer and polymer film around the opening; a semiconductor package disposed on a top surface of the adhesive layer of the jig over the opening with a portion of the top surface remaining exposed between a side surface of the semiconductor package and the groove; and a shielding layer formed over the semiconductor package and jig, wherein a portion of the shielding layer extends into the groove.

2. The semiconductor device of claim 1, wherein the groove extends into the polymer film.

3. The semiconductor device of claim 1, wherein the semiconductor package includes a flat bottom surface physically contacting the adhesive layer.

4. The semiconductor device of claim 1, wherein the shielding layer coats a side surface of the adhesive layer in the groove without completely filling the groove.

5. The semiconductor device of claim 1, wherein the groove extends completely through the adhesive layer and polymer film.

6. The semiconductor device of claim 1, wherein the groove includes a plurality of discrete and separate portions.

7. A semiconductor device, comprising: a jig including a polymer film and an adhesive layer disposed on the polymer film; a groove formed completely through the polymer film and adhesive layer, wherein the groove is formed with a plurality of discrete and separate portions with one of the portions along each edge of the semiconductor package; a semiconductor package disposed on the jig with a side surface of the semiconductor package adjacent to the groove; and a shielding layer formed over the semiconductor package and jig.

8. The semiconductor device of claim 7, wherein an edge of the semiconductor package is disposed within a footprint of the groove, and wherein the semiconductor package includes a flat bottom surface physically contacting the adhesive layer with a portion of the flat bottom surface exposed within the groove.

9. The semiconductor device of claim 7, further including a lateral gap between the groove and semiconductor package, wherein a first portion of a top surface of the adhesive layer is exposed within the lateral gap, and wherein a second portion of the top surface of the adhesive layer physically contacts the semiconductor package.

10. The semiconductor device of claim 7, further including a flat plate disposed on the polymer film opposite the adhesive layer.

11. The semiconductor device of claim 10, wherein the flat plate extends over the groove.

12. The semiconductor device of claim 7, wherein the groove includes a plurality of discrete and separate portions.

13. The semiconductor device of claim 7, wherein the shielding layer coats a side surface of the adhesive layer in the groove without completely filling the groove.

14. A semiconductor device, comprising: a jig; a groove formed completely through the jig; a semiconductor package disposed over the jig with a side surface of the semiconductor package adjacent to the groove; and a shielding layer formed over the semiconductor package and jig, wherein a portion of the shielding layer extends into the groove.

15. The semiconductor device of claim 14, wherein an edge of the semiconductor package is disposed within a footprint of the groove, and wherein the semiconductor package includes a flat bottom surface physically contacting the adhesive layer with a portion of the flat bottom surface exposed within the groove.

16. The semiconductor device of claim 14, further including a lateral gap between the groove and semiconductor package, wherein a first portion of a top surface of the adhesive layer is exposed within the lateral gap, and wherein a second portion of the top surface of the adhesive layer physically contacts the semiconductor package.

17. The semiconductor device of claim 14, further including a flat plate disposed on the jig opposite the semiconductor package.

18. The semiconductor device of claim 17, wherein the flat plate extends over the groove.

19. The semiconductor device of claim 14, wherein the groove includes discrete and separate portions along each respective edge of the semiconductor package.

20. A semiconductor device, comprising: a metal frame; an adhesive layer disposed over the metal frame, wherein the adhesive layer overlaps a footprint of the metal frame, and wherein the adhesive layer is in direct physical contact with the metal frame; a polymer film disposed over the adhesive layer, wherein the adhesive layer is disposed between the polymer film and metal frame, wherein the polymer film is attached to the metal frame by the adhesive layer, and wherein an edge of the polymer film and an edge of the adhesive layer are aligned; an opening formed through the adhesive layer and polymer film; and a groove formed completely through the adhesive layer and polymer film around the opening.

21. The semiconductor device of claim 20, wherein a side surface of the semiconductor package is oriented in parallel with the groove.

22. The semiconductor device of claim 21, wherein an edge of the semiconductor package is disposed within a footprint of the groove, and wherein the semiconductor package includes a flat bottom surface physically contacting the adhesive layer with a portion of the flat bottom surface exposed within the groove.

23. The semiconductor device of claim 21, further including a lateral gap between the groove and semiconductor package, wherein a first portion of a top surface of the adhesive layer is exposed within the lateral gap, and wherein a second portion of the top surface of the adhesive layer physically contacts the semiconductor package.

24. The semiconductor device of claim 20, further including a flat plate disposed on the polymer film opposite the adhesive layer.

25. The semiconductor device of claim 24, wherein the flat plate extends over the groove.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIGS. 1a-1c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;

[0018] FIGS. 2a and 2b illustrate forming a shielding layer over a semiconductor package;

[0019] FIGS. 3a-3f illustrate forming a shielded semiconductor package with laser grooving to reduce burrs;

[0020] FIGS. 4a-4h illustrate additional laser grooving options;

[0021] FIGS. 5a and 5b illustrate options for forming the laser grooving completely through the jig; and

[0022] FIGS. 6a and 6b illustrate integrating the shielded packages into an electronic device.

DETAILED DESCRIPTION OF THE DRAWINGS

[0023] The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term semiconductor die as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

[0024] FIGS. 3a-3f illustrate forming a shielding layer over a semiconductor package using laser grooving to reduce metal burr production. A jig 150 includes metal frame 152 and polyimide (PI) film 154 attached to the metal frame using a silicone adhesive layer 156. Metal frame 152 can be formed from any suitable material, e.g., aluminum or steel. Non-metal materials, such as wood or plastic, are used in some embodiments. Other types of polymer or non-polymer film or tape can be used for PI film 154. Adhesive layer 156 can be any suitable type of adhesive.

[0025] In FIG. 3b, an opening 160 is formed through PI film 154 using a laser, saw, knife, or other type of cutting tool 162. Opening 160 is sized to have a footprint slightly smaller than a package being processed so that the package lies flat on PI film 154 with any interconnect structures of the package extending down through the opening. While a unit-sized jig 150 with only a single opening 160 is shown, in most embodiments the jig is large enough to process tens, hundreds, or thousands of units at once. An opening 160 is formed through PI film 154 for each unit to be processed in parallel. Metal frame 152 can extend between and surround each unit or simply frame the entire jig 150 without extending between units.

[0026] In FIG. 3c, a groove 170 is formed into or through adhesive layer 156 surrounding opening 160. Groove 170 can either be continuous completely around opening 160, or the groove can include discrete portions for each side of the opening as shown below in FIG. 5a. Groove 170 is formed using the same cutting tool 162 from FIG. 3b, or a different type of tool can be used. The groove can be formed using a laser, knife, blade, or any other suitable cutting method.

[0027] In FIG. 3d, a package 180 to be shielded is disposed on jig 150 over opening 160. Package 180 has a package substrate 182. Substrate 182 includes one or more insulating layers 184 interleaved with one or more conductive layers 186. Insulating layer 184 is a core insulating board in one embodiment, with conductive layers 186 patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers 186 also include conductive vias electrically coupled through insulating layers 184. Substrate 182 can include any number of conductive and insulating layers interleaved over each other. A solder mask or passivation layer can be formed over either side of substrate 182. Any suitable type of substrate or leadframe is used for substrate 182 in other embodiments.

[0028] Any components desired to implement the intended functionality of packages 180 are mounted to or disposed over substrate 182 and electrically connected to conductive layers 186. FIG. 3d shows semiconductor die 104 and discrete components 122 mounted onto substrate 182 as merely one example. An encapsulant 188 is deposited over substrate 182, semiconductor die 104, and discrete components 122. Conductive bumps 190 are formed or disposed on contact pads of conductive layer 186 in a similar manner to conductive bumps 114 on conductive layer 112 of semiconductor die 104.

[0029] Groove 170 is formed with an inner wall 172 positioned to approximately align with side surfaces 174 of package 180. Inner walls 172 of groove 170 and side surfaces 174 of package 180 are coplanar or approximately coplanar.

[0030] In FIG. 3e, a conductive material is sputtered over package 180 to form a conductive shielding layer 200. Shielding layer 200 is formed using any suitable metal deposition technique, e.g., chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable conductive material. In some embodiments, shielding layer 200 can be made by sputtering on multiple layers of differing material, e.g., stainless steel-copper-stainless steel or titanium-copper. Shielding layer 200 reduces electromagnetic interference (EMI) between the components of package 180 and other nearby electronic devices. Shielding layer 200 is optionally grounded through conductive layers 186 exposed at a side surface of substrate 182 to improve EMI reduction.

[0031] Shielding layer 200 extends down side surfaces 174 of package 180 and into grooves 170. The portions of shielding layer 200 on side surfaces 174 and side walls 172 combine into one uniform vertical span of conductive material. Whereas in the prior art the shielding layer runs down the sides of the package and then immediately makes a 90-degree turn at the jig, groove 170 results in shielding layer 200 extending down side surfaces 174 and then continuing down vertically even below the bottom of package 180.

[0032] In FIG. 3f, package 180 with shielding layer 200 is removed from jig 150. Shielding layer 200 breaks cleanly along the horizontal line between side surface 174 and side wall 172 as package 180 is lifted. When the package is lifted in the prior art, a horizontal portion of the shielding layer directly adjacent to the package is much more likely to be lifted along with the package compared to shielding layer 200 that continues vertically below package 180.

[0033] FIGS. 4a-4h illustrate a plurality of other configurations for grooves that reduce burr production. FIG. 4a shows groove 210 extending all the way through adhesive layer 156 and into PI film 154. The sidewall 212 of groove 210 is still approximately coplanar to side surfaces 174 of package 180. Having a deeper groove 210 compared to groove 170 further reduces the likelihood of shielding layer 200 separating from the jig because there is a larger surface area of contact in the same plane as side surface 174. FIG. 4b shows an even deeper groove 220 that extends completely through both adhesive layer 156 and PI film 154. The portion of PI film 154 below package 180 remains connected to the surrounded PI film at the corners of the package as shown in FIG. 5a.

[0034] FIGS. 3d, 4a, and 4b show three different options for the depths of a groove to reduce metal burrs. A groove can be formed to any desired depth. FIGS. 4c-4h show different lateral offsets with the three previously shown groove depths. FIGS. 4c and 4d show variations of groove 170 in FIG. 3c. Groove 170a in FIG. 4c extends through adhesive layer 156 as with groove 170. However, groove 170a also extends laterally under package 180. Groove 170b in FIG. 4d is laterally offset from package 180. A portion of adhesive layer 156 remains unaltered between groove 170b and side surface 174. Groove 170b does not extend to or under package 180.

[0035] FIGS. 4e and 4f show similar variations as FIG. 4c and FIG. 4d, except for groove 210 in FIG. 4a instead of groove 170. Groove 210a extends under package 180 while groove 210b leaves a separation between the package and groove. Similarly, FIGS. 4g and 4h show variations of groove 220 with groove 220a extending under package 180 and groove 220b leaving separation between package 180 and the groove. The key point is to have a groove in the carrier near the attach area between package 180 and PI film 154. The shielding layer is formed over any desired semiconductor package and into any of the above-described grooves. The grooves aid in tearing the shielding layer near the semiconductor package being shielded so that a large part of the shielding layer is less likely to tear off from jig 150 with the package.

[0036] FIGS. 5a and 5b illustrate options for forming grooves 220 completely through both adhesive layer 156 and PI film 154. FIG. 5a shows a plan view of PI film 154 with grooves 220 formed along all four sides of opening 160. Grooves 220 are discontinuous at the corners so that the inner portions 154a of PI film 154 are not completely physically separated. Any of the groove embodiments can be formed in discrete sections for each side or continuously around opening 160.

[0037] In FIG. 5b, a thin plate 230 is added under PI film 154 to support the inner portion 154a. Thin plate 230 allows groove 220 to be formed continuously around opening 160 without losing the inner portion 154a of PI film 154 and package 180. Thin plate 230 is a metal plate with an adhesive layer to attach PI film 154. In another embodiment, thin plate 230 is an adhesive tape. Any thickness of thin plate 230 can be used to allow a deeper groove to be formed, including being formed partially through thin plate 230. A groove can be formed completely through thin plate 230 if the inner portions remain connected at the corners as in FIG. 5a.

[0038] FIGS. 6a and 6b illustrate incorporating the above-described shielded semiconductor packages, e.g., package 180 with shielding layer 200, into an electronic device 300. FIG. 6a illustrates a partial cross-section of package 180 mounted onto a printed circuit board (PCB) or other substrate 302 as part of electronic device 300. Bumps 190 are reflowed onto conductive layer 304 of PCB 302 to physically attach and electrically connect package 180 to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between package 180 and PCB 302. Semiconductor die 104 is electrically coupled to conductive layer 304 through substrate 182 and bumps 190.

[0039] FIG. 6b illustrates electronic device 300 including PCB 302 with a plurality of semiconductor packages mounted on a surface of the PCB, including package 180. Electronic device 300 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device 300 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 300 can be a subcomponent of a larger system. For example, electronic device 300 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device 300 can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components.

[0040] In FIG. 6b, PCB 302 provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed over a surface or within layers of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 304 provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces 304 also provide power and ground connections to the semiconductor packages as needed.

[0041] In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB 302. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB 302.

[0042] For the purposes of illustration, several types of first level packaging, including bond wire package 346 and flipchip 348, are shown on PCB 302. Additionally, several types of second level packaging, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) 358, quad flat non-leaded package (QFN) 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364 are shown mounted on PCB 302 along with package 180. Conductive traces 304 electrically couple the various packages and components disposed on PCB 302 to package 180, giving use of the components within package 180 to other components on the PCB.

[0043] Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

[0044] While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.