Semiconductor Device and Method of Forming Selective EMI Shielding with Slotted Substrate

Abstract

A semiconductor device has a substrate and a slot formed in the substrate. A first electrical component is disposed over the substrate adjacent to the slot. An encapsulant is deposited over the first electrical component with a surface of the encapsulant coplanar to a surface of the substrate within the slot. A shielding layer is formed over the encapsulant and physically contacting the surface of the substrate within the slot. The substrate is singulated to form a semiconductor package with the first electrical component after forming the shielding layer.

Claims

1. A semiconductor device, comprising: a substrate including a plurality of conductive layers and a plurality of insulating layers interleaved between the conductive layers; a slot formed completely through the substrate; a first electrical component disposed over the substrate adjacent to the slot; an encapsulant deposited over the first electrical component and substrate, wherein a surface of the encapsulant is coplanar to a surface of the substrate within the slot, and wherein the slot remains devoid of the encapsulant; and a shielding layer formed over the encapsulant and physically contacting the surface of the substrate within the slot.

2. The semiconductor device of claim 1, further including a mask disposed over the substrate and under the shielding layer.

3. The semiconductor device of claim 2, wherein the mask is disposed on the substrate adjacent to the encapsulant opposite the slot.

4. The semiconductor device of claim 1, wherein the slot is curved.

5. The semiconductor device of claim 1, further including a second electrical component disposed on the substrate outside the encapsulant and shielding layer.

6. The semiconductor device of claim 1, wherein a plurality of semiconductor packages is connected by the substrate.

7. A semiconductor device, comprising: a substrate including a conductive layer and an insulating layer; a slot formed completely through the substrate; a first electrical component disposed over the substrate after the substrate; an encapsulant deposited over the substrate, wherein a surface of the encapsulant is adjacent to the slot and the slot remains devoid of the encapsulant; and a shielding layer formed over the encapsulant and extending over a surface of the substrate within the slot.

8. The semiconductor device of claim 7, further including a mask disposed over the substrate and under the shielding layer.

9. The semiconductor device of claim 8, wherein the mask is disposed on the substrate adjacent to the encapsulant opposite the slot.

10. The semiconductor device of claim 8, wherein the mask completely covers the substrate except for where the encapsulant was deposited.

11. The semiconductor device of claim 7, wherein the slot is rounded.

12. The semiconductor device of claim 7, further including a second electrical component disposed over the substrate outside the encapsulant and shielding layer.

13. The semiconductor device of claim 7, wherein a plurality of semiconductor packages is connected by the substrate.

14. A semiconductor device, comprising: a substrate including a slot formed completely through the substrate; an encapsulant deposited over the substrate, wherein the slot remains devoid of the encapsulant; and a shielding layer formed over the substrate and into the slot.

15. The semiconductor device of claim 14, further including a mask disposed over the substrate and under the shielding layer.

16. The semiconductor device of claim 15, wherein the mask is disposed on the substrate adjacent to the encapsulant opposite the slot.

17. The semiconductor device of claim 14, wherein the substrate is round.

18. The semiconductor device of claim 14, further including an electrical component disposed over the substrate outside the encapsulant.

19. The semiconductor device of claim 14, wherein a plurality of semiconductor packages remains connected by the substrate.

20. A semiconductor device, comprising: a substrate including a slot formed in the substrate; an encapsulant deposited over the substrate; and a shielding layer formed over the encapsulant and into the slot.

21. The semiconductor device of claim 20, wherein a surface of the encapsulant is coplanar to a surface of the substrate within the slot.

22. The semiconductor device of claim 20, further including a mask disposed over the substrate and under the shielding layer.

23. The semiconductor device of claim 20, wherein the slot is curved.

24. The semiconductor device of claim 20, further including an electrical component disposed over the substrate outside the encapsulant.

25. The semiconductor device of claim 20, further including a plurality of semiconductor packages connected by the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIGS. 1a-1c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;

[0019] FIGS. 2a-2g illustrate forming shielded semiconductor packages;

[0020] FIGS. 3a-3o illustrate forming shielded semiconductor packages with singulation occurring after the shielding layer is formed;

[0021] FIGS. 4a and 4b illustrate an alternative process flow; and

[0022] FIGS. 5a and 5b illustrate integrating the shielded semiconductor packages into an electronic device.

DETAILED DESCRIPTION OF THE DRAWINGS

[0023] The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term semiconductor die as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

[0024] FIGS. 3a-3o illustrate forming shielded packages with a slotted printed circuit board or substrate to solve problems existing in the prior art. FIGS. 3a and 3b show an initial step of forming semiconductor packages 200 on substrate 202. FIG. 3a is a partial cross section and FIG. 3b shows a plan view. While only two units are shown being formed on one substrate, hundreds or thousands of packages 200 are commonly formed in a single substrate panel 202 using the same steps described herein but performed en masse.

[0025] Substrate 202 includes one or more insulating layers 204 interleaved with one or more conductive layers 206. Insulating layer 204 is a core insulating board in one embodiment, with conductive layers 206 patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers 206 also include conductive vias electrically coupled vertically through insulating layers 204. Substrate 202 can include any number of conductive and insulating layers interleaved over each other. A solder mask or passivation layer can be formed over either side of substrate 202. Any suitable type of substrate or leadframe is used for substrate 202 in other embodiments.

[0026] Any components desired to implement the intended functionality of packages 200 are mounted to or disposed over substrate 202 and electrically connected to conductive layers 206. Components can be mounted onto the top and bottom surfaces of substrate 202 in any suitable configuration. In the disclosed embodiment, components mounted to substrate 202 at this stage are limited to region 208, which will be encapsulated in a subsequent manufacturing step. Semiconductor die 104 and discrete components 152 are surface mounted onto substrate 200 within region 208 of each package 200 using, e.g., any suitable pick and place method or device. Any suitable electrical component can be mounted within region 208 as desired.

[0027] A slot 210 is formed through substrate 202 adjacent to and along the boundary of each encapsulated region 208. Slot 210 is formed along region 208 so that, after being encapsulated, a shielding layer formed over region 208 can extend down into slot 210 and connect to a portion of conductive layer 206 exposed within the slot. Slot 210 is formed opposite to non-encapsulated package region 212, so that the slot corresponds to an area of substrate 202 that will need to be cut for singulation. Slot 210 could partially extend between regions 208 and 212 in some embodiments. Multiple slots 210 can be used at various locations along the boundary of region 208 rather that one long slot. Slots 210 extend completely through substrate 202 but could also be formed only partially through the substrate. Slots 210 expose conductive layer 206 from each region 208 at a side surface of substrate 202 so that a subsequently formed shielding layer will physically and electrically contact the conductive layers.

[0028] Slot 210 is formed during initial manufacturing of substrate 202, which is commonly done by a different manufacturer than the manufacturer forming packages 200 on the substrate. Forming slots 210 before manufacturing of packages 200 commences is simple for the substrate manufacturer and eases requirements for the semiconductor package manufacture. In other embodiment, the manufacturer of semiconductor packages 200 can form slots 210 using a laser, water jet, saw blade, router, or other type of cutting or machining tool.

[0029] In FIGS. 3c and 3d, an encapsulant 214 is deposited over region 208 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 214 is limited to region 208 by pressing a mold against the top surface of substrate 202 and injecting encapsulant 214 into the mold. In other embodiments, encapsulant 214 entirely covers substrate 202 and then is removed outside of regions 208. In embodiments that use transfer molding or injection molding, encapsulant 214 is deposited using a mold with each chamber connected to adjacent chambers that allows the deposited molding compound to flow between packages 200. The areas of encapsulant 214 shown in FIG. 3d will be interconnected by paths or bridges of encapsulant between them after molding. The encapsulant path connecting the illustrated areas of encapsulant 214 is removed prior to completion of packages 200.

[0030] Encapsulant 214 can be polymer composite material, such as an epoxy resin, epoxy acrylate, or polymer with or without a filler. Encapsulant 214 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Encapsulant 214 also protects semiconductor die 104 from degradation due to exposure to light. A side surface 215 of encapsulant 214 is coplanar with a side surface 216 of slot 210. In other embodiments, side surface 215 is laterally offset from side surface 216.

[0031] FIGS. 3e and 3f show masking substrate 202 outside of encapsulant 214 and slots 210 using a tape 220. Tape 220 completely covers substrate 202 outside of regions 208 and slots 210. A conductive material is sputtered over substrate 200 in FIGS. 3g and 3h to form a conductive shielding layer 224. Shielding layer 224 is formed using any suitable metal deposition technique, e.g., chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, titanium, combinations thereof, or any other suitable conductive material. In some embodiments, shielding layer 224 can be made by sputtering on multiple layers of differing material, e.g., stainless steel-copper-stainless steel or titanium-copper. Shielding layer 224 reduces electromagnetic interference (EMI) between the components of package 200 and other nearby electronic devices.

[0032] Shielding layer 224 is formed down side surface 215 of encapsulant 214 and into slot 210. In embodiments where surfaces 215 and 216 are not perfectly aligned, shielding layer 224 runs horizontally across substrate 202 between surface 215 and surface 216. Shielding layer 224 is grounded through conductive layers 206, which are exposed at side surface 216 of substrate 202. Slots 210 allow shielding layer 224 to contact side surface 216 without fully singulating each package 200 prior to sputtering. Therefore, subsequent processing steps described below are performed with substrate 202 remaining as a strip of devices rather than with singulated packages 200. Slot 210 can be formed in any arbitrary shape, so complex package shapes and designs are easily accommodated. Package 200 can be any suitable geometric shape, such as oval, circle, square, octagon, etc. Package 200 can also be an irregular shape, meaning not easily defined using vocabulary or mathematical expressions.

[0033] In FIGS. 3i and 3j, tape 220 is removed along with the portions of shielding layer 224 formed on the tape. Removing tape 220 exposes area 212 of packages 200, along with a plurality of contact pads of conductive layer 206 for mounting of components outside of encapsulant 214. Shielding layer 224 remains over encapsulant 214 in region 208.

[0034] External discrete components 228 are surface mounted onto substrate 202 in FIGS. 3k and 3l. Components 228 are reliably aligned with contact pads of conductive layer 206 because packages 200 remain connected to each other by substrate 202 and are unable to easily shift from their intended positions. With packages 200 completed, singulation occurs in FIGS. 3m and 3n by using a laser or other cutting tool 230 to cut around the boundaries of packages 200. Laser 230 cuts around packages 200 from one end of slot 210 to the other to completely singulate the packages. Slot 210 already has partially singulated packages 200, so the final singulation step takes less time than if the entire package boundary needed to be cut.

[0035] FIG. 30 shows completed packages 200 with shielding layer 224. Packages 200 are manufactured with a lower failure rate than the prior art because processing steps after formation of shielding layer 224 are performed with substrate 202 connecting each unit together as a strip. There is no need for a singulation step prior to forming shielding layer 224. Singulation is the final manufacturing step so shifting of units after singulation is less likely to cause manufacturing defects. Risks of unit-based handling are significantly reduced.

[0036] FIGS. 4a and 4b illustrate an alternative process flow. Continuing from the process step shown in FIGS. 3c and 3d, a mask 220a is formed over region 212 in FIG. 4a. Mask 220a is similar to tape 220 except only formed over regions 212 and not over substrate 202 as a whole. In FIG. 4b, shielding layer 224a is formed over substrate 202, packages 200, and mask 220a. Mask 220a is removed to expose regions 212 including contact pads of conductive layer 206. FIG. 4b shows a similar process step to FIG. 3j, except that shielding layer 224a remains covering substrate 202 outside of packages 200. The extra remaining portions of shielding layer 224a compared to shielding layer 224 are removed by the singulation step shown in FIGS. 3m and 3n. The end packages 200 being formed are not significantly different.

[0037] In some embodiments, the above-described packages, e.g., package 200, are a complete stand-alone electrical system that is fully functional by itself. A plastic molding or other type of case is made to hold substrate 202 in place within a product such as a wireless headphone or smart watch. Package 200 can have integrated antennae for Bluetooth, WiFi, or other protocols as well as a piezoelectric or other speaker to generate noise, a screen to display a watch face, and other desired electrical components. Additional electrical devices can be connected by wire or cable if needed within the same product case. Substrate 202 is the main board of the end device. There is no other main board that package 200 is connected to.

[0038] FIGS. 5a and 5b illustrate another embodiment where the above-described semiconductor packages, e.g., package 200, are integrated into a larger electronic device 300. FIG. 5a illustrates a partial cross-section of package 200 mounted onto a printed circuit board (PCB) or other substrate 302 as part of electronic device 300. Bumps 306 are formed on the bottom of substrate 202 during manufacturing, in a similar process to bumps 112 being formed on die 104, and then reflowed onto conductive layer 304 of PCB 302 to physically attach and electrically connect package 200 to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between package 200 and PCB 302. Semiconductor die 104 are electrically coupled to conductive layer 304 through substrate 202.

[0039] FIG. 5b illustrates electronic device 300 including PCB 302 with a plurality of semiconductor packages mounted on a surface of the PCB, including package 200. Electronic device 300 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device 300 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 300 can be a subcomponent of a larger system. For example, electronic device 300 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device 300 can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components.

[0040] In FIG. 5b, PCB 302 provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed over a surface or within layers of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 304 provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces 304 also provide power and ground connections to the semiconductor packages as needed.

[0041] In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB 302. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB 302.

[0042] For the purpose of illustration, several types of first level packaging, including bond wire package 346 and flipchip 348, are shown on PCB 302. Additionally, several types of second level packaging, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) 358, quad flat non-leaded package (QFN) 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364 are shown mounted on PCB 302 along with package 200. Conductive traces 304 electrically couple the various packages and components disposed on PCB 302 to package 200, giving use of the components within package 200 to other components on the PCB.

[0043] Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

[0044] While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.