SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor device includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Claims

1. A semiconductor device comprising: an SiC substrate having a first surface; an active region formed on the first surface of the SiC substrate; an outer peripheral region formed on the first surface of the SiC substrate, the outer peripheral region disposed from the active region to an edge portion of the SiC substrate; a surface insulating film having a first end portion located in the outer peripheral region; a surface metal layer that is in contact with the first surface of the SiC substrate; a well region of a second conductivity type formed in a manner extending across the active region and the outer peripheral region; and a second conductivity-type layer formed below a contact portion of the surface metal layer on the first surface, the second conductivity-type layer being deeper than the well region, wherein a thickness of the surface insulating film becomes thicker toward the outer peripheral region so that a thicker portion of the surface insulating film is formed in the outer peripheral region, the first end portion and the thicker portion are connected to each other, and the surface insulating film is formed on the first surface that is planar in the single plane such that the first end portion and the thicker portion are in contact with the first surface that is planar in the single plane.

2. The semiconductor device according to claim 1, wherein the surface insulating film includes a first portion having a first thickness and a second portion having a second thickness thicker than the first portion.

3. The semiconductor device according to claim 2, further comprising a source electrode having a part overlapping the surface insulating film in a thickness direction of the SiC substrate.

4. The semiconductor device according to claim 3, further comprising a transistor provided in the active region.

5. The semiconductor device according to claim 4, wherein the transistor is formed in stripes.

6. The semiconductor device according to claim 5, wherein the transistor includes a gate electrode, a source region, and a drain region.

7. The semiconductor device according to claim 6, wherein a step is formed between the first portion and the second portion.

8. The semiconductor device according to claim 6, wherein the surface metal layer includes the source electrode having a covering part overlapping the first portion of the surface insulating film that is thicker than the first portion of the surface insulating film.

9. The semiconductor device according to claim 6, further comprising a contact hole formed in the surface insulating film, wherein the source electrode is disposed in the contact hole.

10. The semiconductor device according to claim 6, further comprising a gate pad formed at a region proximate to an outer edge line of the semiconductor device in a plan view.

11. The semiconductor device according to claim 6, wherein the gate electrode is a material containing polysilicon.

12. The semiconductor device according to claim 6, further comprising a channel region of a second conductivity type disposed on the source region on a second surface side opposed to the first surface, in a manner contacting the source region.

13. The semiconductor device according to claim 12, further comprising a channel contact region of the second conductivity type selectively disposed on a first surface side so that the channel contact region is electrically connected with the channel region, wherein the source electrode is electrically connected with the source region and the channel contact region.

14. The semiconductor device according to claim 12, wherein an impurity material forming the channel region of the second conductivity type is an aluminum.

15. The semiconductor device according to claim 6, further comprising a gate insulating film made of a material including SiO.sub.2 that is formed between the gate electrode and the SiC substrate.

16. The semiconductor device according to claim 1, wherein the thicker portion has a thickness of 5500 to 20000 .

17. The semiconductor device according to claim 1, further comprising a multilayer wiring structure disposed on the surface insulating film.

18. The semiconductor device according to claim 1, further comprising a recess formed, on the first surface, laterally of the contact portion of the surface metal layer, wherein the second conductivity-type layer is, at a bottom portion of the recess, formed to be thicker than a part at a side portion of the recess.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0055] FIGS. 1A and 1B are a schematic plan view of a semiconductor device according to a first preferred embodiment of the present invention, in which FIG. 1A shows an overall view and FIG. 1B shows a layout diagram of a plurality of unit cells.

[0056] FIG. 2 is an enlarged view showing a main part of the semiconductor device according to the first preferred embodiment of the present invention, in which an upper side of the figure shows a sectional view and a lower side of the figure shows a plan view.

[0057] FIG. 3A is a schematic view showing a part of a process for manufacturing the semiconductor device according to the first preferred embodiment of the present invention.

[0058] FIG. 3B is a view showing a step following that of FIG. 3A.

[0059] FIG. 3C is a view showing a step following that of FIG. 3B.

[0060] FIG. 3D is a view showing a step following that of FIG. 3C.

[0061] FIG. 3E is a view showing a step following that of FIG. 3D.

[0062] FIG. 3F is a view showing a step following that of FIG. 3E.

[0063] FIG. 3G is a view showing a step following that of FIG. 3F.

[0064] FIG. 3H is a view showing a step following that of FIG. 3G.

[0065] FIG. 3I is a view showing a step following that of FIG. 3H.

[0066] FIG. 3J is a view showing a step following that of FIG. 3I.

[0067] FIG. 3K is a view showing a step following that of FIG. 3J.

[0068] FIG. 4 is an enlarged view showing a main part of a semiconductor device according to a second preferred embodiment of the present invention, in which an upper side of the figure shows a sectional view and a lower side of the figure shows a plan view.

[0069] FIG. 5A is a schematic view showing a part of a process for manufacturing the semiconductor device according to the second preferred embodiment of the present invention.

[0070] FIG. 5B is a view showing a step following that of FIG. 5A.

[0071] FIG. 6 is an enlarged view showing a main part of a semiconductor device according to a third preferred embodiment of the present invention, in which an upper side of the figure shows a sectional view and a lower side of the figure shows a plan view.

[0072] FIG. 7A is a schematic view showing a part of a process for manufacturing the semiconductor device according to the third preferred embodiment of the present invention.

[0073] FIG. 7B is a view showing a step following that of FIG. 7A.

[0074] FIGS. 8A and 8B are views showing a modification of the layout of unit cells.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0075] Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

First Preferred Embodiment

[0076] FIGS. 1(a) and 1(b) are a schematic plan view of a semiconductor device according to a first preferred embodiment of the present invention, in which FIG. 1(a) shows an overall view and FIG. 1(b) shows a layout diagram of a plurality of unit cells.

[0077] The semiconductor device 1 includes a SiC-based trench-gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in FIG. 1(a), the semiconductor device 1 has, for example, a square chip-shaped contour in a plan view. The chip-shaped semiconductor device 1 is sized to have a vertical and horizontal length of about several millimeters in the illustration of FIG. 1(a). An active region 2 and an outer peripheral region 3 disposed around the active region 2 are set on a surface of the semiconductor device 1.

[0078] In the active region 2, a plurality of unit cells 4 each of which performs a transistor operation are defined in a grid shape by a gate trench 5. Each unit cell 4 includes an annular n.sup.+-type source region 6, an annular source trench 7 (second trench) surrounded by the n.sup.+-type source region 6, and a p.sup.+-type channel contact region 8 formed in an island shape inside the source trench 7. The p.sup.+-type channel contact region 8 is surrounded by the source trench 7 at its periphery. Also, each unit cell 4 is sized to have a vertical and horizontal length of about 10 m in the illustration of FIG. 1(b).

[0079] The outer peripheral region 3 is, in the present preferred embodiment, formed in an annular shape in a manner surrounding the active region 2. In the outer peripheral region 3, a plurality of guard rings 9 are formed spaced apart from each other, in a manner surrounding the active region 2. In addition, the guard rings 9 under a source pad 10 (described later) are shown perspectively in FIG. 1(a).

[0080] A source pad 10 (surface metal layer) is formed on the surface of the semiconductor device 1. The source pad 10 is formed across substantially the whole of the surface of the semiconductor device 1, in a manner extending across the plurality of unit cells 4. The source pad 2, in the present preferred embodiment, has a substantially square shape in a plan view with the four corners being curved outward. A removal region 11 is formed near the center of one side of the source pad 10. The removal region 11 is a region in which the source pad 10 is not formed.

[0081] A gate pad 12 is disposed in the removal region 11. The gate pad 12 and the source pad 10 are provided with an interval therebetween, and are insulated from each other.

[0082] FIG. 2 is an enlarged view showing a main part of the semiconductor device according to the first preferred embodiment of the present invention, in which an upper side of the figure shows a sectional view, and a lower side of the figure shows a plan view.

[0083] Next, an internal structure of the semiconductor device 1 will be described.

[0084] The semiconductor device 1 includes a substrate (not shown) made of n.sup.+-type SiC (for example, having a concentration of 110.sup.18 to 110.sup.21 cm.sup.3) and an n.sup.-type epitaxial layer 13 made of n.sup.-type SiC (for example, having a concentration of 110.sup.15 to 110.sup.17 cm.sup.3) formed on the substrate. The n.sup.-type epitaxial layer 13 is a layer formed by causing SiC to epitaxially grow on a surface of the substrate. In the present preferred embodiment, the substrate and the n.sup.-type epitaxial layer 13 are shown as an example of a semiconductor layer of the present invention.

[0085] In a surface portion of the n.sup.-type epitaxial layer 13, a p-type well 14 (for example, having a concentration of 110.sup.16 to 110.sup.19 cm.sup.3) is formed in a manner extending across the active region 2 and the outer peripheral region 3. On the other hand, a region of a portion under the p-type well 14 in the n.sup.-type epitaxial layer 13 is an n.sup.-type drain region 15.

[0086] An n.sup.+-type source region 6 is formed in a surface portion of the p-type well 14 in the active region 2, and exposed on the surface of the n.sup.-type epitaxial layer 13. In addition, the part of the p-type well 14 within the active region 2 is a p-type channel region 16 which is disposed in a manner contacting the n.sup.+-type source region 6 and in which a channel is formed at the time of a transistor operation.

[0087] Moreover, the gate trench 5 and the source trench 7 are formed in a manner penetrating through the n.sup.+-type source region 6 and the p-type channel region 16 (p-type well 14) to reach the n.sup.-type drain region 15. The gate trench 5 and the source trench 7 are, in the present preferred embodiment, formed with the same width and the same depth, but may be different in depth from each other. For example, the source trench 7 may be shallower or may be deeper than the gate trench 5.

[0088] Each unit cell 4 is separated into a prismatic portion 17 surrounded by the source trench 7 and an annular portion 18 disposed between the source trench 7 and the gate trench 5 and spaced apart from the prismatic portion 17 by the source trench 7. In the present preferred embodiment, the width W.sub.1 of the annular portion 18 (distance between the source trench 7 and the gate trench 5) is, for example, 0.5 m to 2.0 m.

[0089] In a top portion of the prismatic portion 17, a p.sup.+-type channel contact region 8 (for example, having a concentration of 110.sup.18 to 110.sup.21 cm.sup.3) is formed in a manner exposed on the surface of the n.sup.-type epitaxial layer 13. Accordingly, the p.sup.+-type channel contact region 8 forms a part of the side face of the source trench 7. The p.sup.+-type channel contact region 8, in the present preferred embodiment, has its deepest portion at a position higher than that of a bottom portion of the source trench 7, but the deepest portion is not particularly necessary at this position. As long as an uppermost portion of the p.sup.+-type channel contact region 8 (in the present preferred embodiment, the part exposed on the surface of the n.sup.-type epitaxial layer 13) is at a position higher than that of the bottom portion of the source trench 7 and is contactable, said deepest portion may be at the same depth position as that of the bottom portion of the source trench 7 or may be deeper.

[0090] In the annular portion 18, an n.sup.+-type source region 6 and a p-type channel region 16 are formed in order from the surface side. Accordingly, the n.sup.+-type source region 6 and the p-type channel region 16 form parts of the side face of the gate trench 5, respectively. The n.sup.+-type source region 6 is, in the present preferred embodiment, formed with the same depth as that of the p.sup.+-type channel contact region 8.

[0091] Also, in the n.sup.-type epitaxial layer 13, a p-type layer 19 (for example, having a concentration of 110.sup.16 to 110.sup.19 cm.sup.3) serving as an example of a second conductivity-type layer of the present invention is formed in a manner continuing from the p-type channel region 16 and the p.sup.+-type channel contact region 8. The p-type layer 19 is, in the present preferred embodiment, formed in a manner extending across the prismatic portion 17 and the annular portion 18 via the bottom portion of the source trench 7, and its inner region is in contact with the source trench 7 (exposed into the source trench 7). The p-type layer 19 is connected to the p-type channel region 16 at a portion lateral to the source trench 7 of the annular portion 18, and is connected to the p.sup.+-type channel contact region 8 at a portion lateral to the source trench 7 of the prismatic portion 17. Thus, the p-type channel region 16 and the p.sup.+-type channel contact region 8 are electrically connected via the p-type layer 19.

[0092] Also, the p-type layer 19 is also formed in a manner extending across outer peripheral edges of the gate trench 5 via a bottom portion of an outermost peripheral line of the gate trench 5, and is connected, at the outer peripheral edges, to the p-type well 14 extending to the outer peripheral region 3.

[0093] Also, the p-type layer 19 is, at the bottom portion of the source trench 7, formed to be thicker than a part at a side portion of the source trench 7. However, in the prismatic portion 17, a portion lateral to the source trench 7 is surrounded by the source trench 7, and ion implantation is uniformly performed from its periphery. Therefore, the p-type layer 19 is formed thicker than the part at the bottom portion of the source trench 7, so as to fill a part under the p.sup.+-type channel contact region 8.

[0094] Also, the p-type layer 19 is formed in a manner extending along the gate trench 5. In the present preferred embodiment, the p-type layer 19 is formed across the entire periphery of the annular portion 18 surrounded by the gate trench 5, in a manner not contacting the gate trench 5 (spaced from the gate trench 5). Accordingly, an n.sup.-type drain region 15 is disposed at a part of the side face of the gate trench 5, so that a current path at the time of channel formation can be secured.

[0095] The gate trench 5 is, in the present preferred embodiment, formed in a substantially U-shape in a sectional view having a side face and a bottom face. On an inner surface (side face and bottom face) of the gate trench 5, a gate insulating film 20 is formed such that its one surface and the other surface extend along the inner surface of the gate trench 5.

[0096] The gate insulating film 20 is, at the bottom portion of the gate trench 5, formed to be thicker than a part at a side portion of the gate trench 5. In the gate trench 5 having a substantially U-shape in a sectional view as in the present preferred embodiment, the relatively thick part of the gate insulating film 20 is a part that contacts the bottom face of the gate trench 5, and the relatively thin part is a part that contacts the side face of the gate trench 5. By making the insulating film thick at the bottom portion of the gate trench 5 where electric field concentration is likely to occur, withstand voltage in the bottom portion of the gate trench 5 can be improved. In addition, the side face and bottom face sometimes cannot be clearly distinguished depending on the shape of the gate trench 5, but in that case, it suffices that the gate insulating film 20 that contacts a face in a direction crossing the depth direction of the gate trench 5 is relatively thick.

[0097] Moreover, the inside of the gate insulating film 20 is filled back with a gate electrode 21. In the present preferred embodiment, the gate electrode 21 is buried in the gate trench 5 such that its upper face becomes substantially flush with the surface of the n.sup.-type epitaxial layer 13. The gate electrode 21 is opposed to the p-type channel region 16 via the gate insulating film 20. In each unit cell 4, by controlling a voltage to be applied to the gate electrode 21, an annular channel along the periphery of the unit cell 4 is formed in the p-type channel region 16. Then, a drain current that flows along the side face of the gate trench 5 toward the surface of the n.sup.-type epitaxial layer 13 can be caused to flow to the n.sup.+-type source region 6 via the channel. A transistor operation of the semiconductor device 1 is thereby performed.

[0098] Similarly, the source trench 7 is also, in the present preferred embodiment, formed in a substantially U-shape in a sectional view having a side face and a bottom face. On an inner surface (side face and bottom face) of the source trench 7, a source trench insulating film 22 is formed such that its one surface and the other surface extend along the inner surface of the source trench 7.

[0099] The source trench insulating film 22 is, at the bottom portion of the source trench 7, formed to be thicker than a part at a side portion of the source trench 7. In addition, the side face and bottom face sometimes cannot be clearly distinguished depending on the shape of the source trench 7, but in that case, it suffices that the source trench insulating film 22 that contacts a face in a direction crossing the depth direction of the source trench 7 is relatively thick. Moreover, the inside of the source trench insulating film 22 is filled back with a trench buried layer 23. In the present preferred embodiment, the trench buried layer 23 is buried in the source trench 7 such that its upper face becomes substantially flush with the surface of the n.sup.-type epitaxial layer 13.

[0100] In the present preferred embodiment, the gate insulating film 20 and the source trench insulating film 22 are constituted of the same material, and the gate electrode 21 and the trench buried layer 23 are constituted of the same material.

[0101] For example, as the material for the gate insulating film 20 and the source trench insulating film 22, a film of any of SiO.sub.2, AlON, Al.sub.2O.sub.3, SiO.sub.2/AlON, SiO.sub.2/AlON/SiO.sub.2, SiO.sub.2/SiN, and SiO.sub.2/SiN/SiO.sub.2 can be used, and more preferably, a film having a SiO.sub.2 film containing nitrogen (N) is used. In addition, SiO.sub.2/AlON means a laminated film of SiO.sub.2 (lower side) and AlON (upper side). Providing a gate insulating film 20 constituted of a high-dielectric-constant (high-k) film of AlON, Al.sub.2O.sub.3, or the like allows an improvement in gate withstand voltage, so that device reliability can be improved. Further, providing a gate insulating film 20 constituted of a material having a SiO.sub.2 film containing nitrogen (N) also allows an improvement in channel mobility.

[0102] As the material for the gate electrode 21 and the trench buried layer 23, polysilicon can be used, and more preferably, n.sup.+-type polysilicon is used. The n.sup.+-type polysilicon has a relatively low sheet resistance, which therefore allows increasing transistor switching speed.

[0103] In addition, the gate insulating film 20 and the source trench insulating film 22 may be constituted of materials different from each other. Similarly, the gate electrode 21 and the trench buried layer 23 may also be constituted of materials different from each other. For example, the gate electrode 21 may be a metal gate electrode containing any of Mo, W, Al, Pt, Ni, and Ti. The metal gate electrode can also make gate resistance relatively low, which therefore allows increasing transistor switching speed.

[0104] In a surface portion of the p-type well 14 in the outer peripheral region 3, a p.sup.+-type well contact region 24 (for example, having a concentration of 110.sup.18 to 110.sup.21 cm.sup.3) is formed. The p.sup.+-type well contact region 24 is, in the present preferred embodiment, in an annular shape in a manner surrounding the active region 2, and is formed with the same depth as that of the p.sup.+-type channel contact region 8.

[0105] Also, outside of the p-type well 14 in the outer peripheral region 3, guard rings 9 are formed spaced from the p-type well 14.

[0106] The guard ring 9, in the present preferred embodiment, includes a trench 31 formed in the surface of the n.sup.-type epitaxial layer 13 and a p-type layer 32 (for example, having a concentration of 110.sup.16 to 110.sup.19 cm.sup.3) formed at, at least, a bottom portion of the trench 31. In the present preferred embodiment, the p-type layer 32 is formed at bottom and side portions of the trench 31, and is, at the bottom portion of the trench 31, formed to be thicker than a part at the side portion of the trench 31. Also, in the present preferred embodiment, the trench 31 is formed with the same depth as that of the gate trench 5, and the p-type layer 32 is formed with the same depth as that of the p-type layer 19.

[0107] Similar to the gate trench 5, in the trench 31, a trench buried layer 34 is buried via a trench insulating film 33. As the materials for the trench insulating film 33 and the trench buried layer 34, the same materials as those for the gate insulating film 20 and the gate electrode 21 can be used, respectively.

[0108] On the surface of the n.sup.-type epitaxial layer 13, a surface insulating film 25 is formed so as to extend across the active region 2 and the outer peripheral region 3. The surface insulating film 25 is made of an insulator such as silicon oxide (SiO.sub.2), for example. The surface insulating film 25 is formed such that an inner part 27 on the active region 2 becomes thinner than an outer part 26 on the outer peripheral region 3. In the present preferred embodiment, the inner part 27 on the active region 2 has a thickness of 5000 or less, and the outer part 26 on the outer peripheral region 3 has a thickness of about 5500 to 20000 . The surface insulating film 25 may be called an interlayer insulating film when a multilayer wiring structure is disposed thereon, which is not shown in FIG. 2.

[0109] In the surface insulating film 25, contact holes 28 that selectively expose the p.sup.+-type channel contact region 8, the source trench 7, and the n.sup.+-type source region 6 are formed for every unit cell 4 over the entire surface of the n.sup.-type epitaxial layer 13. In the present preferred embodiment, a source portion 30 is defined in each unit cell 4 by the contact hole 28. Also, in the surface insulating film 25, a contact hole 29 that selectively exposes the p.sup.+-type well contact region 24 is formed over the entire surface of the n.sup.-type epitaxial layer 13.

[0110] On the surface insulating film 25, a source pad 10 is formed. The source pad 10 is connected collectively to the p.sup.+-type channel contact regions 8 and the n.sup.+-type source regions 6 of all unit cells 4 and the p.sup.+-type well contact region 24 via the respective contact holes 28 and 29. In other words, the source pad 10 serves as a common electrode to all unit cells 4. Also, as the material for the source pad 10, a metal containing copper (Cu) may be used, and more preferably, a metal containing an AlCu-based alloy is used. Because the sheet resistance of the source pad 10 can thereby be reduced, the current density can be increased. Also, the source pad 10 has a thickness (distance from the surface of the n.sup.-type epitaxial layer 13 to a surface of the source pad 10) of, for example, 4 m to 5 m. In addition, the source pad 10 may have a contact metal made of, for example, a laminated structure (Ti/TiN) of titanium (Ti) and titanium nitride (TiN) at a connection part with the n.sup.-type epitaxial layer 13.

[0111] On the other hand, the gate pad 12 (refer to FIG. 1(a)) is electrically connected to the gate electrode 21 via a gate wiring (not shown) or the like.

[0112] FIG. 3A to FIG. 3K are schematic views showing in the order of steps a part of a process for manufacturing the semiconductor device according to the first preferred embodiment of the present invention.

[0113] For manufacturing the semiconductor device 1, as shown in FIG. 3A, an n.sup.-type impurity is doped into the surface of a SiC substrate (not shown) while SiC crystals are caused to grow thereon by epitaxy such as a CVD method, an LPE method, or an MBE method. An n.sup.-type epitaxial layer 13 is thereby formed on the SiC substrate. In addition, as the n.sup.-type impurity, for example, N (nitride), P (phosphorous), As (arsenic), or the like can be used.

[0114] Next, a p-type impurity is selectively ion-implanted from the surface of the n.sup.-type epitaxial layer 13. A p-type well 14 (p-type channel region 16) is thereby formed. In addition, as the p-type impurity, for example, Al (aluminum), B (boron), or the like can be used. Also, simultaneously with formation of the p-type well 14, the rest of the n.sup.-type epitaxial layer 13 is formed as an n.sup.-type drain region 15.

[0115] Next, as shown in FIG. 3B, an n-type impurity is selectively ion-implanted from the surface of the n.sup.-type epitaxial layer 13. An n.sup.+-type source region 6 is thereby formed.

[0116] Next, as shown in FIG. 3C, the n.sup.-type epitaxial layer 13 is selectively etched by use of a mask having openings in regions where the gate trench 5, the source trenches 7, and the trenches 31 are to be formed. An n.sup.-type epitaxial layer 13 is thereby dry-etched from the surface in a manner penetrating through the n.sup.+-type source region 6 and the p-type channel region 16, so that a gate trench 5, source trenches 7, and trenches 31 are simultaneously formed. In conjunction therewith, the n.sup.-type epitaxial layer 13 is defined into a plurality of unit cells 4 by the gate trench 5. The unit cells 4 are to have prismatic portions 17 and annular portions 18. Also, as an etching gas, for example, a mixed gas (SF.sub.6/O.sub.2 gas) containing SF.sub.6 (sulfur hexafluoride) and O.sub.2 (oxygen), a mixed gas (SF.sub.6/O.sub.2/HBr gas) containing SF.sub.6, O.sub.2, and HBr (hydrogen bromide), or the like can be used.

[0117] Next, as shown in FIG. 3D, a p-type impurity is selectively ion-implanted from the surface of the n.sup.-type epitaxial layer 13. The p-type impurity is implanted, for example, in a direction perpendicular to the surface of the n.sup.-type epitaxial layer 13. A p-type layer 19 and a p-type layer 32 are thereby simultaneously formed. In addition, the p-type layer 19 and the p-type layer 32 may be formed by separate ion implantation steps.

[0118] Next, as shown in FIG. 3E, a p-type impurity is selectively ion-implanted from the surface of the n.sup.-type epitaxial layer 13. P.sup.+-type channel contact regions 8 and a p.sup.+-type well contact region 24 are thereby simultaneously formed.

[0119] Next, the n.sup.-type epitaxial layer 13 is thermally treated at 1400 C. to 2000 C., for example. The ions of the p-type impurity and n.sup.-type impurity implanted into the n.sup.-type epitaxial layer 13 are thereby activated.

[0120] Next, as shown in FIG. 3F, a gate insulating film 20, a source trench insulating film 22, and a trench insulating film 33 are simultaneously formed by, for example, thermal oxidization. In addition, when the gate insulating film 20, the source trench insulating film 22, and the trench insulating film 33 are constituted of high-dielectric-constant (high-k) films, it suffices to deposit a film material by a CVD method.

[0121] Next, as shown in FIG. 3G, a polysilicon material doped with an n-type impurity is deposited from above the n.sup.-type epitaxial layer 13 by, for example, a CVD method. The deposition of the polysilicon material is continued until at least the gate trench 5, the source trenches 7, and the trenches 31 have been completely filled back. Thereafter, the deposited polysilicon material is etched back until its etched-back face becomes flush with the surface of the n.sup.-type epitaxial layer 13. A gate electrode 21 and trench buried layers 23 and 34 are thereby simultaneously formed.

[0122] Next, as shown in FIG. 3H, an insulating material such as SiO.sub.2 is deposited from above the n.sup.-type epitaxial layer 13 by, for example, a CVD method. A surface insulating film 25 is thereby formed.

[0123] Next, as shown in FIG. 3I, a part on the active region 2 of the surface insulating film 25 is selectively etched. Only said part is thereby thinned, so that an inner part 27 and an outer pert 26 of the surface insulating film 25 are formed.

[0124] Next, as shown in FIG. 3J, by the surface insulating film 25 being selectively etched, contact holes 28 and 29 are simultaneously formed.

[0125] Next, as shown in FIG. 3K, a metal material is deposited from above the n.sup.-type epitaxial layer 13 by, for example, a sputtering method. Then, by patterning said material, a source pad 10 is formed. The semiconductor device 1 shown in FIG. 2 is obtained through the above steps.

[0126] As above, according to the present semiconductor device 1, the trench buried layer 23 is buried in the source trenches 7 via the trench insulating film 22. Therefore, on the surface of the n.sup.-type epitaxial layer 13 (device surface), a difference in level (unevenness) between the source portions 30 exposed from the contact holes 28 and other parts can be reduced. The flatness of the source pad 10 on said device surface can thereby be improved. Thus, when, for example, a wire is bonded to the surface of the source pad 10, adhesion between the source pad 10 and the wire can be improved. As a result, the wire can be satisfactorily bonded, so that the wire bonding portion can be improved in reliability. Further, because the source pad 10 is excellent in flatness, destruction of the device by ultrasonic vibration and pressure can be prevented at the time of wire bonding, and a decline in assembling yield can be prevented.

[0127] On the other hand, a concentration of equipotential surfaces in a vicinity of the bottom portion of the gate trench 5 can be prevented by the source trench 7, so that a potential gradient in the vicinity of the bottom portion can be made gradual. Therefore, an electric field concentration to the bottom portion of the gate trench 5 can be relaxed. Further, the p.sup.+-type channel contact region 8 is formed in the top portion of the prismatic portion 17 and is disposed at a position higher than that of the bottom portion of the source trench 7. Thus, even when there is formed a source trench 7, contact with the p-type channel region 16 can be reliably made via the p.sup.+-type channel contact region 8. In other words, at the time of an improvement in flatness of the source pad 10, a degradation in device performance such as gate withstand voltage and contact performance with the p-type channel region 16 can be prevented.

[0128] Further, in the present preferred embodiment, because the p-type layer 19 is formed around the source trench 7, a depletion layer can be generated from a junction (p-n junction) between the p-type layer 19 and the n.sup.-type drain region 15. Moreover, because the depletion layer keeps equipotential surfaces away from the gate trench 5, electric fields to be imposed on the bottom portion of the gate trench 5 can be further relaxed.

[0129] Also, in the present preferred embodiment, because a SiC device in which latch-up is unlikely to occur as compared with a Si device is used, the p.sup.+-type channel contact region 8 and the p-type channel region 16 can be provided at positions separated from each other by the source trench 7. That is, in a Si device, because latch-up is relatively likely to occur, it is preferable to dispose the p.sup.+-type channel contact region 8 near the p-type channel region 16 to reduce the distance between the regions 8 and 16 as short as possible so as to lower a base resistance between said regions 8 and 16. On the other hand, in such a SiC device as the present semiconductor device 1, because latch-up is relatively unlikely to occur and the importance of considering a base resistance between the regions 8 and 16 is low, the p.sup.+-type channel contact region 8 does not need to be disposed near the p-type channel region 16. Thus, the p.sup.+-type channel contact region 8 and the p-type channel region 16 can be provided at positions separated from each other by the source trench 7 to electrically connect the regions 8 and 16 by a route through the bottom portion of the source trench 7.

[0130] Also, because the source trench insulating film 22 is disposed outside of the trench buried layer 23, flow of an off-leakage current between the n.sup.-type epitaxial layer 13 and the source pad 10 can be prevented. Specifically, the p-type layer 19 is, at a side portion of the source trench 7, thinner than a part at the bottom portion of the source trench 7 because ions are unlikely to enter a portion lateral to the source trench 7 at the time of ion implantation. Therefore, when a high voltage is applied at OFF-time, an off-leakage current may flow passing through the thin part of the p-type layer 19. Therefore, forming a source trench insulating film 22 allows reliably interrupting a leakage current by the source trench insulating film 22 even if an off-leakage current passes through the p-type layer 19.

[0131] Also, if the trench buried layer 23 buried in the source trench 7 is polysilicon, when forming contact holes 28 in the surface insulating film 25 made of SiO.sub.2 (FIG. 3J), the trench buried layer 23 (polysilicon layer) can be used as an etching stopper. Therefore, control of the step of said contact etching can be simply performed.

[0132] Also, because the source trenches 7 are formed simultaneously with the gate trench 5 (FIG. 3C), the source trenches 7 can be simply formed without increasing the manufacturing process. Further, if the source trenches 7 and the gate trench 5 are the same width, the etching rate for the source trenches 7 can be made the same as that for the gate trench 5, so that etching for forming the source trenches 7 can be stably controlled.

Second Preferred Embodiment

[0133] FIG. 4 is an enlarged view showing a main part of a semiconductor device according to a second preferred embodiment of the present invention, in which an upper side of the figure shows a sectional view, and a lower side of the figure shows a plan view. In FIG. 4, parts corresponding to the respective portions shown in FIG. 1 and FIG. 2 described above are shown with the same reference signs.

[0134] In the first preferred embodiment described above, the trench buried portion buried in the source trench 7 consists of the source trench insulating film 22 and the trench buried layer 23 (polysilicon layer), but as in the present semiconductor device 41, it may consist only of an insulating layer 42 that fills back the source trenches 7.

[0135] As the material for the insulating layer 42, SiO.sub.2 can be used, and more preferably, SiO.sub.2 containing phosphorus (P) or boron (B) is used. As such SiO.sub.2, for example, PSG (phosphorus silicate glass) or PBSG (phosphorus boron silicate glass) can be used.

[0136] A process for manufacturing the semiconductor device 41 according to the present preferred embodiment is substantially the same as the steps shown in FIG. 3A to FIG. 3K. However, after a gate electrode 21 and trench buried layers 23 and 34 are formed in the step of FIG. 3G, as shown in FIG. 5A, the trench buried layer 23 is selectively etched to be removed, so that the source trenches 7 are made hollow. Then, as shown in FIG. 5B, a surface insulating film 25 is formed on the n.sup.-type epitaxial layer 13 to thereby fill back the source trenches 7 by use of a part of the surface insulating film 25. The source trench insulating film 22 and the surface insulating film 25 are thereby integrated inside the source trenches 7, so that an insulating layer 42 is formed.

[0137] According to the present semiconductor device 41, because the source trenches 7 are filled with the insulating layer 42, flow of an off-leakage current between the n.sup.-type epitaxial layer 13 and the source pad 10 can be effectively prevented.

[0138] Also, if the insulating layer 42 is SiO.sub.2 containing phosphorous or boron, because the melting point of SiO.sub.2 falls, the process for burying the insulating layer 42 can be simply performed.

[0139] Of course, in the present semiconductor device 41 as well, the same effects as those of the first preferred embodiment can also be realized.

Third Preferred Embodiment

[0140] FIG. 6 is an enlarged view showing a main part of a semiconductor device according to a third preferred embodiment of the present invention, in which an upper side of the figure shows a sectional view, and a lower side of the figure shows a plan view. In FIG. 6, parts corresponding to the respective portions shown in FIG. 1 and FIG. 2 described above are shown with the same reference signs.

[0141] In the first preferred embodiment described above, the trench filling portion buried in the source trench 7 consists of the source trench insulating film 22 and the trench buried layer 23 (polysilicon layer), but as in the present semiconductor device 61, it may consist only of a polysilicon layer 62 that fills back the source trenches 7. As the material for the polysilicon layer 62, p.sup.+-type polysilicon is preferably used.

[0142] A process for manufacturing the semiconductor device 61 according to the present preferred embodiment is substantially the same as the steps shown in FIG. 3A to FIG. 3K. However, after a gate insulating film 20, a source trench insulating film 22, and a trench insulating film 33 are formed in the step of FIG. 3F, as shown in FIG. 7A, the source trench insulating film 22 is selectively etched to be removed, so that the source trenches 7 are made hollow. Then, as shown in FIG. 7B, by polysilicon being deposited from above the n.sup.-type epitaxial layer 13, the source trenches 7 are filled back with that polysilicon. A gate electrode 21 and a polysilicon layer 62 are thereby simultaneously formed.

[0143] According to the present semiconductor device 61, because the polysilicon layer 62 is buried in the source trenches 7, when forming contact holes 28 in the surface insulating film 25 made of SiO.sub.2 (FIG. 3J), the polysilicon layer 62 can be used as an etching stopper. Therefore, control of the step of said contact etching can be simply performed.

[0144] Also, if the polysilicon layer 62 is p.sup.+-type polysilicon, the p.sup.+-type channel contact region 8 and the p-type channel region 16 can be electrically connected by use of the polysilicon layer 62. Because the length of a current path between the regions 8 and 16 can thereby be reduced, a base resistance therebetween can be reduced. As a result, latch-up can be satisfactorily prevented. Further, because the p.sup.+-type channel contact region 8 is in contact with the polysilicon layer 62 at a side face of the source trench 7, a contact resistance therebetween can also be reduced. The reduction in contact resistance also contributes to a reduction in the base resistance between the regions 8 and 16.

[0145] Of course, in the present semiconductor device 61 as well, the same effects as those of the first preferred embodiment can also be realized.

[0146] Although preferred embodiments of the present invention have been described above, the present invention can be embodied in other forms.

[0147] For example, an arrangement may be adopted in which the conductivity type of each semiconductor part of each semiconductor device (1, 41, 61) is inverted. For example, in the semiconductor devices 1, the p-type parts may be n.sup.-type and the n.sup.-type parts may be p-type.

[0148] Also, in the semiconductor device (1, 41, 61), the layer that constitutes a semiconductor layer is not limited to an n.sup.-type epitaxial layer made of SiC, and may be a layer or the like made of GaN, diamond, or Si.

[0149] Also, each unit cell 4 is not limited to a square shape in a plan view (quadrangular shape), but may have another shape such as, for example, a triangular shape in a plan view, a pentagonal shape in a plan view, or a hexagonal shape in a plan view, and may further have a stripe shape as in the semiconductor device 81 of FIG. 8.

[0150] Also, in the preferred embodiment described above, an example has been mentioned in which the source trench 7 is formed in an annular shape and the channel contact region 8 is disposed inside thereof, but the source trench 7 need not to be an annular shape. For example, the source trench 7 may be formed in a recessed shape such as a triangle, quadrangle, circle, or oblong in a plan view and the channel contact region 8 may be disposed outside thereof.

[0151] Also, the guard ring 9 is a structure including the trench 31 formed in the surface of n.sup.-type epitaxial layer 13 and the p-type layer 32 formed in, at least, the bottom portion of the trench 31, but may be a structure consisting only of, for example, p-type semiconductor regions.

[0152] The semiconductor device of the present invention can be incorporated in, for example, a power module for use in an inverter circuit that constitutes a drive circuit for driving an electric motor available as a power source for an electric vehicle (including a hybrid vehicle), an electric train, an industrial robot, and the like. Additionally, the semiconductor device of the present invention can also be incorporated in a power module for use in an inverter circuit that converts electric power generated by a solar cell, a wind power generator, and other power generators (particularly, private electric generators) so as to be matched with electric power from commercial power sources.

[0153] Also, the features grasped from the disclosures of the preferred embodiments described above may be combined with each other even among different preferred embodiments. Also, the components presented in the respective preferred embodiments may be combined within the scope of the present invention.

[0154] The preferred embodiments of the present invention are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the spirit and scope of the present invention shall be limited solely by the accompanying claims.

REFERENCE SIGNS LIST

[0155] 1 Semiconductor device [0156] 2 Active region [0157] 3 Outer peripheral region [0158] 4 Unit cell [0159] 5 Gate trench [0160] 6 N.sup.+-type source region [0161] 7 Source trench [0162] 8 P.sup.+-type channel contact region [0163] 10 Source pad [0164] 13 N.sup.-type epitaxial layer [0165] 14 P-type well [0166] 15 N.sup.-type drain region [0167] 16 P-type channel region [0168] 19 P-type layer [0169] 20 Gate insulating film [0170] 21 Gate electrode [0171] 22 Source trench insulating film [0172] 23 Trench buried layer [0173] 25 Surface insulating film [0174] 26 Outer part (of surface insulating film) [0175] 27 Inner part (of surface insulating film) [0176] 28 Contact hole [0177] 30 Source portion [0178] 41 Semiconductor device [0179] 42 Insulating layer [0180] 61 Semiconductor device [0181] 62 Polysilicon layer [0182] 81 Semiconductor device