Doherty Amplifier

Abstract

Example embodiments relate to Doherty amplifiers. One example includes a radiofrequency (RF) power amplifier. The RF power amplifier includes an input lead. The RF power amplifier also includes a first output lead. Additionally, the RF power amplifier includes a first semiconductor die arranged in between the input lead and the first output lead. The first semiconductor die includes a first edge arranged adjacent to the input lead and an opposing second edge arranged adjacent to the first output lead. Further, the RF power amplifier includes a field-effect transistor integrated on the first semiconductor die. The field-effect transistor includes a gate bondpad assembly and a drain bondpad assembly. The field-effect transistor also includes a plurality of gate bondwires and a plurality of drain bondwires. In addition, the field-effect transistor includes a plurality of gate fingers extending in a first direction and a plurality of drain fingers extending in a second direction.

Claims

1. A radiofrequency (RF) power amplifier, comprising: a field-effect transistor comprising: a gate bondpad assembly; a drain bondpad assembly; a plurality of gate fingers extending in a first direction from the gate bondpad assembly towards the drain bondpad assembly; and at least one auxiliary gate bondpad assembly, each auxiliary gate bondpad assembly being arranged spaced apart from the plurality of gate fingers in a respective direction perpendicular to the first direction, wherein each auxiliary gate bondpad assembly is arranged closer to the drain bondpad assembly than to the gate bondpad assembly when seen in the first direction, and wherein each auxiliary gate bondpad assembly is electrically connected to the gate bondpad assembly; and for each of the at least one auxiliary gate bondpad assembly, one or more bondwires that each have: a first end that is physically and electrically connected to that auxiliary gate bondpad assembly; and a second end that is configured to be RF grounded during operation.

2. The RF power amplifier according to claim 1, further comprising a first semiconductor die, wherein the field-effect transistor is integrated at or near an upper surface of the first semiconductor die.

3. The RF power amplifier according to claim 2, further comprising a heat-conducting or electrically conductive substrate on which the first semiconductor die is mounted.

4. The RF power amplifier according to claim 3, further comprising a package body made of a solidified molding compound.

5. The RF power amplifier according to claim 1, wherein each of the at least one auxiliary gate bondpad assembly is electrically connected to the gate bondpad assembly via the plurality of gate fingers, and wherein the field-effect transistor comprises, for each of the at least one auxiliary gate bondpad assembly, a respective conductive track that physically connects that auxiliary gate bondpad assembly to the plurality of gate fingers.

6. The RF power amplifier according to claim 5, wherein the position at which the respective conductive track connects to a gate finger corresponds to a position along that gate finger that falls within the last 50 percent of that gate finger, taking the gate bondpad assembly as a starting point of that gate finger.

7. The RF power amplifier according to claim 1, wherein at least one auxiliary gate bondpad assembly is arranged adjacent the drain bondpad assembly.

8. The RF power amplifier according to claim 1, further comprising at least one DC blocking capacitor, each DC blocking capacitor having a first terminal that is configured to be electrically grounded during operation and a second terminal, wherein the second ends of the one or more bondwires for at least one auxiliary gate bondpad assembly are physically connected to the second terminal of a respective DC blocking capacitor among the at least one DC blocking capacitor.

9. The RF power amplifier according to claim 8, wherein the at least one DC blocking capacitor is electrically connected in between the gate bondpad assembly and the at least one auxiliary gate bondpad assembly.

10. The RF power amplifier according to claim 1, wherein the at least one auxiliary gate bondpad assembly comprises a pair of auxiliary gate bondpad assemblies.

11. The RF power amplifier according to claim 1, wherein the gate bondpad assembly, the drain bondpad assembly, or the at least one auxiliary gate bondpad assembly comprises at least one bondpad or a bondbar.

12. The RF power amplifier according to claim 1, wherein the field-effect transistor comprises a silicon-based laterally diffused metal-oxide semiconductor (LDMOS) or a Gallium Nitride-based field-effect transistor.

13. A Doherty amplifier, comprising: a Doherty splitter arranged for splitting an input radiofrequency (RF) signal into a main RF signal and a peak RF signal; a main amplifier for amplifying the main RF signal; a peak amplifier for amplifying the peak RF signal; and a Doherty combiner for combining the amplified main RF signal and the amplified peak RF signal into an output RF signal, wherein the main amplifier and the peak amplifier each comprises a RF power amplifier, comprising: a field-effect transistor comprising: a gate bondpad assembly; a drain bondpad assembly; a plurality of gate fingers extending in a first direction from the gate bondpad assembly towards the drain bondpad assembly; and at least one auxiliary gate bondpad assembly, each auxiliary gate bondpad assembly being arranged spaced apart from the plurality of gate fingers in a respective direction perpendicular to the first direction, wherein each auxiliary gate bondpad assembly is arranged closer to the drain bondpad assembly than to the gate bondpad assembly when seen in the first direction, and wherein each auxiliary gate bondpad assembly is electrically connected to the gate bondpad assembly; and for each of the at least one auxiliary gate bondpad assembly, one or more bondwires that each have: a first end that is physically and electrically connected to that auxiliary gate bondpad assembly; and a second end that is configured to be RF grounded during operation.

14. The Doherty amplifier according to claim 13, wherein the RF power amplifier of the main amplifier and the RF power amplifier of the peak amplifier each comprises a substrate that is shared among the main amplifier and the peak amplifier.

15. The Doherty amplifier according to claim 14, wherein the RF power amplifier of the main amplifier and the RF power amplifier of the peak amplifier each further comprises a package body made of a solidified molding compound, and wherein the package body of the RF power amplifier of the main amplifier and the package body of the RF power amplifier of the peak amplifier form a single contiguous package body.

16. The Doherty amplifier according to claim 13, further comprising a first semiconductor die, wherein the field-effect transistor of at least one RF power amplifier is integrated at or near an upper surface of the first semiconductor die.

17. The Doherty amplifier according to claim 13, wherein each of the at least one auxiliary gate bondpad assembly of at least one RF power amplifier is electrically connected to the gate bondpad assembly of the respective RF power amplifier via the plurality of gate fingers of the respective RF power amplifier, and wherein the field-effect transistor of at least one RF power amplifier comprises, for each of the at least one auxiliary gate bondpad assembly of the respective RF power amplifier, a respective conductive track that physically connects that auxiliary gate bondpad assembly of the respective RF power amplifier to the plurality of gate fingers of the respective RF power amplifier.

18. The Doherty amplifier according to claim 17, wherein the position at which the respective conductive track connects to a gate finger corresponds to a position along that gate finger that falls within the last 50 percent of that gate finger, taking the respective gate bondpad assembly as a starting point of that gate finger.

19. The Doherty amplifier according to claim 13, wherein at least one auxiliary gate bondpad assembly of at least one RF power amplifier is arranged adjacent the drain bondpad assembly of the respective RF power amplifier.

20. The Doherty amplifier according to claim 13, wherein the gate bondpad assembly of at least one RF power amplifier, the drain bondpad assembly of at least one RF power amplifier, or the at least one auxiliary gate bondpad assembly of at least one RF power amplifier comprises at least one bondpad or a bondbar.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Next, example embodiments will be described in more detail referring to appended drawings, wherein identical or similar components will be referred to using the same reference numerals.

[0026] FIG. 1 illustrates an RF power amplifier with internal DC blocking capacitors, according to example embodiments.

[0027] FIG. 2 illustrates an RF power amplifier system where the RF power amplifier has no internal DC blocking capacitors, according to example embodiments.

[0028] FIG. 3 illustrates an RF power amplifier with internal DC capacitors, according to example embodiments.

[0029] FIG. 4 illustrates an RF power amplifier with internal DC capacitors, according to example embodiments.

[0030] FIG. 5A illustrate an RF power amplifier with internal DC capacitors, according to example embodiments.

[0031] FIG. 5B illustrates a cross-section corresponding to the RF power amplifier of FIG. 5A, according to example embodiments.

[0032] FIG. 6 illustrates a Doherty amplifier in which the RF power amplifier of FIG. 5A is used as main and peak amplifier, according to example embodiments.

DETAILED DESCRIPTION

[0033] FIG. 1 illustrates an RF power amplifier 100, according to example embodiments. RF power amplifier 100 includes a substrate 101, an input lead 102, and a first output lead 103. On substrate 101, which can be embodied as a heat conducting and/or electrically conducting substrate, a first semiconductor die 104 is mounted on which a FET 110 is integrated.

[0034] FET 110 includes a gate bondbar 111 and a drain bondbar 112. A plurality of gate fingers 113 extend in a first direction D1 from gate bondbar 111 towards drain bondbar 112. Similarly, a plurality of drain fingers 114 extend in a second direction D2 from drain bondbar 112 towards gate bondbar 111.

[0035] A plurality of gate bondwires 115 connects gate bondbar 111 to input lead 102. Similarly, a plurality of drain bondwires 116 connects drain bondbar 112 to first output lead 103.

[0036] FET 110 further includes a pair of auxiliary gate bondpads 117 that are connected, using a conductive track 118, to the plurality of gate fingers 113. The position at which the connection is made is indicates using circles.

[0037] Bondwires 119 extend between auxiliary gate bondpads 117 and a pair of second semiconductor dies 120 on which a DC blocking capacitor is integrated. This capacitor has a non-grounded terminal 121 that is electrically connected to a bondwire 119. The other terminal of the DC blocking capacitor is electrically grounded during operation. For example, the other terminal is electrically connected to a conductive substrate of second semiconductor die 120. As the second semiconductor die 120 is mounted on a conductive substrate 101, which is grounded during operation, suitable grounding of the DC blocking capacitor can be achieved.

[0038] In FIG. 1, one bondwire 119 makes an angle a1 relative to an average direction of the plurality of drain bondwires 116, which corresponds to direction D1, whereas the other bondwire 119 makes an angle+a2 relative to this average direction. The manner in which these angles are determined is illustrated using hashed lines. Typically, both a1 and a2 lie in a range between 0 and 120 degrees (e.g., in a range between 0 and 90 degrees, such as between 0 and 60 degrees).

[0039] As illustrated, auxiliary gate bondpad 117 is shifted in a third direction D3 relative to the plurality of gate fingers 113. Moreover, auxiliary gate bondpad 117 is located closer to drain bondbar 112 than to gate bondbar 111.

[0040] By choosing the bondwire length and angle a1, a2 of bondwire 119, the compensation of the gate-drain capacitance of FET 110 can be optimized without having to re-design the layout of first semiconductor die 104.

[0041] FIG. 2 illustrates an RF power amplifier system 1000, according to example embodiments. RF power amplifier system 1000 includes an RF power amplifier 200 and a printed circuit board 1010 on which RF power amplifier 200 is mounted. RF power amplifier 200 has no internal DC blocking capacitors. Instead, RF power amplifier 200 includes a pair of second output leads 103A that are connected on printed circuit board 1010 to respective lumped DC blocking capacitors 1020 (e.g., surface mount device (SMD) capacitors).

[0042] FIGS. 3, 4, and 5A illustrate further embodiments of RF power amplifiers with internal DC capacitors.

[0043] RF power amplifier 300 shown in FIG. 3 differs from RF power amplifier 100 shown in FIG. 1 in that the positions of auxiliary gate bondpads 117 and the positions of second semiconductor dies 120 are different.

[0044] RF power amplifier 400 shown in FIG. 4 differs from RF power amplifier 100 shown in FIG. 1 in that a single second semiconductor die 120 is used. On this semiconductor die, two separate DC blocking capacitors or a single, large DC blocking capacitor can be integrated. In addition, RF power amplifier 400 includes a third semiconductor die 401 on which a matching capacitor is arranged. This matching capacitor has a non-grounded terminal that is connected to the plurality of drain bondwires 116 and to a further plurality of drain bondwires 402 by which the non-grounded terminal is connected to output lead 103.

[0045] RF power amplifier 500 shown in FIG. 5 differs from RF power amplifier 400 shown in FIG. 4 in that single semiconductor die 501 is used on which the DC blocking capacitor(s) and the matching capacitor are integrated. A corresponding cross-section is shown in FIG. 5B.

[0046] RF power amplifier 500 includes a package body 502 of solidified molding compound that fixes substrate 101 relative to input lead 102 and output lead 103. A lid 503 is fixedly connected to package body 502, thereby defining a cavity 504 in which the first semiconductor die 104 and the semiconductor die 501 are arranged.

[0047] FIG. 6 illustrates a Doherty amplifier 2000, according to example embodiments. Doherty amplifier 2000 includes a main amplifier 2010 and a peak amplifier 2020 that are both realized using RF power amplifier 500 and that are mounted on printed circuit board 2001. It should be noted that the power capabilities of the RF power amplifiers 500 may be identical, resulting in a symmetric Doherty amplifier, but they may also be different, resulting in an asymmetric Doherty amplifier.

[0048] Doherty amplifier 2000 includes a Doherty splitter 2030 that receives an RF input signal RFin and that splits RFin into a main signal and a peak signal that are provided to main amplifier 2010 and peak amplifier 2020, respectively. After amplification, Doherty combiner 2040 combines the amplified main and peak signals and outputs the combined signal as the RF output signal RFout. Doherty splitter 2030 and Doherty combiner 2040 are typically formed and/or arranged on printed circuit board 2001.

[0049] Main amplifier 2010 and peak amplifier 2020 are biased differently such that, at low input powers, only main amplifier 2010 is operational. At high input powers, both main amplifier 2010 and peak amplifier 2020 are operational.

[0050] Doherty combiner 2040 provides an impedance inversion function such that, at low powers, main amplifier 2010 is presented with a higher impedance at its drain than at high powers. By using the impedance inversion, efficiency at low input powers can be improved while also obtaining good efficiency at high input powers.

[0051] Together, Doherty combiner 2040 and Doherty splitter 2030 ensure that the amplified signals add up in-phase in Doherty combiner 2040.

[0052] In the above, the present disclosure has been explained using detailed embodiments thereof. However, the present disclosure is not limited to these embodiments. Rather, various modifications to these embodiments are possible without deviating from the scope of the present disclosure, which is defined by the appended claims and their equivalents.